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a="73909310" X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="73909310" X-CSE-ConnectionGUID: DcMg9nmPQqGWiHwMF3Gjag== X-CSE-MsgGUID: dAKDEJrLSFazhBKLONOqCQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="214542797" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas , Sandipan Das Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V3 04/13] target/i386: Adjust maximum number of PMU counters Date: Wed, 4 Mar 2026 10:07:03 -0800 Message-ID: <20260304180713.360471-5-zide.chen@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304180713.360471-1-zide.chen@intel.com> References: <20260304180713.360471-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1772648173180158500 Content-Type: text/plain; charset="utf-8" Changing either MAX_GP_COUNTERS or MAX_FIXED_COUNTERS affects the VMState layout and therefore requires bumping the migration version IDs. Adjust both limits together to avoid repeated VMState version bumps in follow-up patches. To support full-width writes, QEMU needs to handle the alias MSRs starting at 0x4c1. With the current limits, the alias range can extend into MSR_MCG_EXT_CTL (0x4d0). Reducing MAX_GP_COUNTERS from 18 to 15 avoids the overlap while still leaving room for future expansion beyond current hardware (which supports at most 10 GP counters). Increase MAX_FIXED_COUNTERS to 7 to support additional fixed counters (e.g. Topdown metric events). With these changes, bump version_id to prevent migration to older QEMU, and bump minimum_version_id to prevent migration from older QEMU, which could otherwise result in VMState overflows. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- target/i386/cpu.h | 8 ++------ target/i386/machine.c | 4 ++-- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6d3e70395dbd..23d4ee13abfa 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1749,12 +1749,8 @@ typedef struct { #define CPU_NB_REGS CPU_NB_REGS32 #endif =20 -#define MAX_FIXED_COUNTERS 3 -/* - * This formula is based on Intel's MSR. The current size also meets AMD's - * needs. - */ -#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0) +#define MAX_FIXED_COUNTERS 7 +#define MAX_GP_COUNTERS 15 =20 #define NB_OPMASK_REGS 8 =20 diff --git a/target/i386/machine.c b/target/i386/machine.c index 1125c8a64ec5..7d08a05835fc 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -685,8 +685,8 @@ static bool pmu_enable_needed(void *opaque) =20 static const VMStateDescription vmstate_msr_architectural_pmu =3D { .name =3D "cpu/msr_architectural_pmu", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .needed =3D pmu_enable_needed, .fields =3D (const VMStateField[]) { VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), --=20 2.53.0