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a="73909296" X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="73909296" X-CSE-ConnectionGUID: M+LsFPKQQ4uhJhFnuLtQJQ== X-CSE-MsgGUID: h6EC6ouGTjeGI/QGea5xbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="214542788" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas , Sandipan Das Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V3 02/13] target/i386: Don't save/restore PERF_GLOBAL_OVF_CTRL MSRs Date: Wed, 4 Mar 2026 10:07:01 -0800 Message-ID: <20260304180713.360471-3-zide.chen@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304180713.360471-1-zide.chen@intel.com> References: <20260304180713.360471-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1772648170894158500 Content-Type: text/plain; charset="utf-8" From: Dapeng Mi MSR_CORE_PERF_GLOBAL_OVF_CTRL and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR are write-only MSRs and reads always return zero. Saving and restoring these MSRs is therefore unnecessary. Replace VMSTATE_UINT64 with VMSTATE_UNUSED in the VMStateDescription to ignore env.msr_global_ovf_ctrl during migration. This avoids the need to bump version_id and does not introduce any migration incompatibility. cc: Dongli Zhang cc: Sandipan Das Signed-off-by: Dapeng Mi Co-developed-by: Zide Chen Signed-off-by: Zide Chen --- V3: - Remove MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR. --- target/i386/cpu.h | 3 --- target/i386/kvm/kvm.c | 10 ---------- target/i386/machine.c | 4 ++-- 3 files changed, 2 insertions(+), 15 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 016fb1b30bbd..6d3e70395dbd 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -507,11 +507,9 @@ typedef enum X86Seg { #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f -#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 =20 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 -#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 =20 #define MSR_K7_EVNTSEL0 0xc0010000 #define MSR_K7_PERFCTR0 0xc0010004 @@ -2102,7 +2100,6 @@ typedef struct CPUArchState { uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; - uint64_t msr_global_ovf_ctrl; uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS]; uint64_t msr_gp_counters[MAX_GP_COUNTERS]; uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 3b66ec8c42b2..1131c350d352 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4207,8 +4207,6 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState leve= l) if (pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, env->msr_global_status); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, - env->msr_global_ovf_ctrl); =20 /* Now start the PMU. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, @@ -4252,8 +4250,6 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState leve= l) if (pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, env->msr_global_status); - kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_C= LR, - env->msr_global_ovf_ctrl); kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_CTL, env->msr_global_ctrl); } @@ -4769,7 +4765,6 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); - kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); } for (i =3D 0; i < num_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); @@ -4812,7 +4807,6 @@ static int kvm_get_msrs(X86CPU *cpu) if (pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_CTL, 0); kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, 0); - kvm_msr_entry_add(cpu, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, = 0); } } =20 @@ -5135,10 +5129,6 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: env->msr_global_status =3D msrs[i].data; break; - case MSR_CORE_PERF_GLOBAL_OVF_CTRL: - case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: - env->msr_global_ovf_ctrl =3D msrs[i].data; - break; case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_F= IXED_COUNTERS - 1: env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] =3D = msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index c9139612813b..1125c8a64ec5 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -666,7 +666,7 @@ static bool pmu_enable_needed(void *opaque) int i; =20 if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl || - env->msr_global_status || env->msr_global_ovf_ctrl) { + env->msr_global_status) { return true; } for (i =3D 0; i < MAX_FIXED_COUNTERS; i++) { @@ -692,7 +692,7 @@ static const VMStateDescription vmstate_msr_architectur= al_pmu =3D { VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU), VMSTATE_UINT64(env.msr_global_ctrl, X86CPU), VMSTATE_UINT64(env.msr_global_status, X86CPU), - VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU), + VMSTATE_UNUSED(sizeof(uint64_t)), VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COU= NTERS), VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS), VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS), --=20 2.53.0