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a="73909406" X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="73909406" X-CSE-ConnectionGUID: Yn6q0i+jQ4yfIrXTiqiRsQ== X-CSE-MsgGUID: wgySaHQIR42rBkpgqzh75g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="214542866" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas , Sandipan Das Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V3 13/13] target/i386: Add Topdown metrics feature support Date: Wed, 4 Mar 2026 10:07:12 -0800 Message-ID: <20260304180713.360471-14-zide.chen@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304180713.360471-1-zide.chen@intel.com> References: <20260304180713.360471-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1772648189463139100 Content-Type: text/plain; charset="utf-8" From: Dapeng Mi IA32_PERF_CAPABILITIES.PERF_METRICS_AVAILABLE (bit 15) indicates that the CPU provides built-in support for TMA L1 metrics through the PERF_METRICS MSR. Expose it as a user-visible CPU feature ("perf-metrics"), allowing it to be explicitly enabled or disabled and used with migratable guests. Plumb IA32_PERF_METRICS through the KVM MSR get/put paths to be able to save and restore this MSR. Migrate IA32_PERF_METRICS MSR using a new subsection of vmstate_msr_architectural_pmu. Signed-off-by: Dapeng Mi Co-developed-by: Zide Chen Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- V3: New patch --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 3 +++ target/i386/kvm/kvm.c | 10 ++++++++++ target/i386/machine.c | 19 +++++++++++++++++++ 4 files changed, 33 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3ff9f76cf7da..88cfd3529851 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1620,7 +1620,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { NULL, NULL, NULL, NULL, NULL, NULL, "pebs-trap", "pebs-arch-reg", NULL, NULL, NULL, NULL, - NULL, "full-width-write", "pebs-baseline", NULL, + NULL, "full-width-write", "pebs-baseline", "perf-metrics", NULL, "pebs-timing-info", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6a9820c4041a..5d0ed692ae06 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -428,6 +428,7 @@ typedef enum X86Seg { PERF_CAP_PEBS_FMT_SHIFT) #define PERF_CAP_FULL_WRITE (1U << 13) #define PERF_CAP_PEBS_BASELINE (1U << 14) +#define PERF_CAP_TOPDOWN (1U << 15) =20 #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -514,6 +515,7 @@ typedef enum X86Seg { #define MSR_CORE_PERF_FIXED_CTR0 0x309 #define MSR_CORE_PERF_FIXED_CTR1 0x30a #define MSR_CORE_PERF_FIXED_CTR2 0x30b +#define MSR_PERF_METRICS 0x329 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f @@ -2111,6 +2113,7 @@ typedef struct CPUArchState { uint64_t msr_fixed_ctr_ctrl; uint64_t msr_global_ctrl; uint64_t msr_global_status; + uint64_t msr_perf_metrics; uint64_t msr_ds_area; uint64_t msr_pebs_data_cfg; uint64_t msr_pebs_enable; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 8c4564bcbb9e..3f533cd65708 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4295,6 +4295,10 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState lev= el) kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, env->msr_fixed_counters[i]); } + /* SDM: Write IA32_PERF_METRICS after fixed counter 3. */ + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_TOPDOWN) { + kvm_msr_entry_add(cpu, MSR_PERF_METRICS, env->msr_perf= _metrics); + } for (i =3D 0; i < num_pmu_gp_counters; i++) { kvm_msr_entry_add(cpu, perf_cntr_base + i, env->msr_gp_counters[i]); @@ -4868,6 +4872,9 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); } + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_TOPDOWN) { + kvm_msr_entry_add(cpu, MSR_PERF_METRICS, 0); + } for (i =3D 0; i < num_pmu_fixed_counters; i++) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); } @@ -5234,6 +5241,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: env->msr_global_status =3D msrs[i].data; break; + case MSR_PERF_METRICS: + env->msr_perf_metrics =3D msrs[i].data; + break; case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_F= IXED_COUNTERS - 1: env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] =3D = msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 5cff5d5a9db5..6b7141cfead7 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -680,6 +680,24 @@ static const VMStateDescription vmstate_msr_ds_pebs = =3D { VMSTATE_END_OF_LIST()} }; =20 +static bool perf_metrics_enabled(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!env->msr_perf_metrics; +} + +static const VMStateDescription vmstate_msr_perf_metrics =3D { + .name =3D "cpu/msr_architectural_pmu/msr_perf_metrics", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D perf_metrics_enabled, + .fields =3D (const VMStateField[]){ + VMSTATE_UINT64(env.msr_perf_metrics, X86CPU), + VMSTATE_END_OF_LIST()} +}; + static bool pmu_enable_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -721,6 +739,7 @@ static const VMStateDescription vmstate_msr_architectur= al_pmu =3D { }, .subsections =3D (const VMStateDescription * const []) { &vmstate_msr_ds_pebs, + &vmstate_msr_perf_metrics, NULL, }, }; --=20 2.53.0