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a="73909400" X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="73909400" X-CSE-ConnectionGUID: QOqgkkB0QIqoSq/qQOtWlQ== X-CSE-MsgGUID: TfQNgZRaRgydxgPG46P9AA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="214542857" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas , Sandipan Das Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V3 12/13] target/i386: Clean up Intel Debug Store feature dependencies Date: Wed, 4 Mar 2026 10:07:11 -0800 Message-ID: <20260304180713.360471-13-zide.chen@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304180713.360471-1-zide.chen@intel.com> References: <20260304180713.360471-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1772648252075139101 Content-Type: text/plain; charset="utf-8" - 64-bit DS Area (CPUID.01H:ECX[2]) depends on DS (CPUID.01H:EDX[21]). - When PMU is disabled, Debug Store must not be exposed to the guest, which implicitly disables legacy DS-based PEBS. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- V3: - Update title to be more accurate. - Make DTES64 depend on DS. - Mark MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL in previous patch. - Clean up the commit message. V2: New patch. --- target/i386/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2e1dea65d708..3ff9f76cf7da 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1899,6 +1899,10 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_1_ECX, CPUID_EXT_PDCM }, .to =3D { FEAT_PERF_CAPABILITIES, ~0ull }, }, + { + .from =3D { FEAT_1_EDX, CPUID_DTS}, + .to =3D { FEAT_1_ECX, CPUID_EXT_DTES64}, + }, { .from =3D { FEAT_1_ECX, CPUID_EXT_VMX }, .to =3D { FEAT_VMX_PROCBASED_CTLS, ~0ull }, @@ -9471,6 +9475,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **err= p) env->features[FEAT_1_ECX] &=3D ~CPUID_EXT_PDCM; } =20 + env->features[FEAT_1_EDX] &=3D ~CPUID_DTS; env->features[FEAT_7_0_EDX] &=3D ~CPUID_7_0_EDX_ARCH_LBR; } =20 --=20 2.53.0