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a="73909383" X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="73909383" X-CSE-ConnectionGUID: kYqnLPcCT/mdlQAEtDyMnw== X-CSE-MsgGUID: rpio76ldR8a/6Vfir0rCFg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="214542846" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas , Sandipan Das Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V3 10/13] target/i386: Refactor LBR format handling Date: Wed, 4 Mar 2026 10:07:09 -0800 Message-ID: <20260304180713.360471-11-zide.chen@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304180713.360471-1-zide.chen@intel.com> References: <20260304180713.360471-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1772648159128139100 Content-Type: text/plain; charset="utf-8" Detach x86_cpu_pmu_realize() from x86_cpu_realizefn() to keep the latter focused and easier to follow. Introduce a dedicated helper, x86_cpu_apply_lbr_pebs_fmt(), in preparation for adding PEBS format support without duplicating code. Convert PERF_CAP_LBR_FMT into separate mask and shift macros to allow x86_cpu_apply_lbr_pebs_fmt() to be shared with PEBS format handling. No functional change intended. Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- V2: New patch. --- target/i386/cpu.c | 93 +++++++++++++++++++++++++++++++---------------- target/i386/cpu.h | 3 +- 2 files changed, 64 insertions(+), 32 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index da2e67ca1faf..d5e00b41fb04 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9769,6 +9769,65 @@ static bool x86_cpu_update_smp_cache_topo(MachineSta= te *ms, X86CPU *cpu, } #endif =20 +static bool x86_cpu_apply_lbr_pebs_fmt(X86CPU *cpu, uint64_t host_perf_cap, + uint64_t user_req, bool is_lbr_fmt, + Error **errp) +{ + CPUX86State *env =3D &cpu->env; + uint64_t mask; + unsigned shift; + unsigned user_fmt; + const char *name; + + if (is_lbr_fmt) { + mask =3D PERF_CAP_LBR_FMT_MASK; + shift =3D PERF_CAP_LBR_FMT_SHIFT; + name =3D "lbr"; + } else { + return false; + } + + if (user_req !=3D -1) { + env->features[FEAT_PERF_CAPABILITIES] &=3D ~(mask << shift); + env->features[FEAT_PERF_CAPABILITIES] |=3D (user_req << shift); + } + + user_fmt =3D (env->features[FEAT_PERF_CAPABILITIES] >> shift) & mask; + if (user_fmt) { + unsigned host_fmt =3D (host_perf_cap >> shift) & mask; + + if (!cpu->enable_pmu) { + error_setg(errp, "vPMU: %s is unsupported without pmu=3Don", n= ame); + return false; + } + if (user_fmt !=3D host_fmt) { + error_setg(errp, "vPMU: the %s-fmt value (0x%x) does not match= " + "the host value (0x%x).", + name, user_fmt, host_fmt); + return false; + } + } + + return true; +} + +static int x86_cpu_pmu_realize(X86CPU *cpu, Error **errp) +{ + uint64_t host_perf_cap =3D + x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIES); + + /* + * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT + * with user-provided setting. + */ + if (!x86_cpu_apply_lbr_pebs_fmt(cpu, host_perf_cap, + cpu->lbr_fmt, true, errp)) { + return -EINVAL; + } + + return 0; +} + static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -9776,7 +9835,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) X86CPUClass *xcc =3D X86_CPU_GET_CLASS(dev); CPUX86State *env =3D &cpu->env; Error *local_err =3D NULL; - unsigned guest_fmt; =20 if (!kvm_enabled()) cpu->enable_pmu =3D false; @@ -9812,35 +9870,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) goto out; } =20 - /* - * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT - * with user-provided setting. - */ - if (cpu->lbr_fmt !=3D -1) { - env->features[FEAT_PERF_CAPABILITIES] &=3D ~PERF_CAP_LBR_FMT; - env->features[FEAT_PERF_CAPABILITIES] |=3D cpu->lbr_fmt; - } - - /* - * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=3Don and - * 3)vPMU LBR format matches that of host setting. - */ - guest_fmt =3D env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; - if (guest_fmt) { - uint64_t host_perf_cap =3D - x86_cpu_get_supported_feature_word(NULL, FEAT_PERF_CAPABILITIE= S); - unsigned host_lbr_fmt =3D host_perf_cap & PERF_CAP_LBR_FMT; - - if (!cpu->enable_pmu) { - error_setg(errp, "vPMU: LBR is unsupported without pmu=3Don"); - return; - } - if (guest_fmt !=3D host_lbr_fmt) { - error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not matc= h " - "the host value (0x%x).", - guest_fmt, host_lbr_fmt); - return; - } + if (x86_cpu_pmu_realize(cpu, errp)) { + return; } =20 if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpui= d)) { @@ -10430,7 +10461,7 @@ static const Property x86_cpu_properties[] =3D { #endif DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), - DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_= FMT), + DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_= FMT_MASK), =20 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, HYPERV_SPINLOCK_NEVER_NOTIFY), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3a10f3242329..a064bf8ab17e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -420,7 +420,8 @@ typedef enum X86Seg { #define ARCH_CAP_TSX_CTRL_MSR (1<<7) =20 #define MSR_IA32_PERF_CAPABILITIES 0x345 -#define PERF_CAP_LBR_FMT 0x3f +#define PERF_CAP_LBR_FMT_MASK 0x3f +#define PERF_CAP_LBR_FMT_SHIFT 0x0 #define PERF_CAP_FULL_WRITE (1U << 13) #define PERF_CAP_PEBS_BASELINE (1U << 14) =20 --=20 2.53.0