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Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou Reviewed-by: Chao Liu --- target/riscv/vector_helper.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7575e24084..b7105627ed 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -49,6 +49,15 @@ static target_ulong vtype_reserved(CPURISCVState *env, t= arget_ulong vtype) return reserved; } =20 +static inline void reset_ill_vtype(CPURISCVState *env) +{ + /* only set vill bit. */ + env->vill =3D 1; + env->vtype =3D 0; + env->vl =3D 0; + env->vstart =3D 0; +} + target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, target_ulong s2, target_ulong x0) { @@ -93,11 +102,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_= ulong s1, } =20 if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) !=3D 0))= { - /* only set vill bit. */ - env->vill =3D 1; - env->vtype =3D 0; - env->vl =3D 0; - env->vstart =3D 0; + reset_ill_vtype(env); return 0; } =20 @@ -113,11 +118,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target= _ulong s1, } =20 if (cpu->cfg.rvv_vsetvl_x0_vill && x0 && (env->vl !=3D vl)) { - /* only set vill bit. */ - env->vill =3D 1; - env->vtype =3D 0; - env->vl =3D 0; - env->vstart =3D 0; + reset_ill_vtype(env); return 0; } =20 --=20 2.52.0