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Signed-off-by: James Wainwright --- MAINTAINERS | 2 +- disas/meson.build | 3 +- disas/riscv-zbr.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++ disas/riscv-zbr.h | 18 +++++++++++ disas/riscv.c | 4 +++ 5 files changed, 103 insertions(+), 2 deletions(-) create mode 100644 disas/riscv-zbr.c create mode 100644 disas/riscv-zbr.h diff --git a/MAINTAINERS b/MAINTAINERS index 6698e5ff69..a3b747148d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4144,7 +4144,7 @@ M: Alistair Francis L: qemu-riscv@nongnu.org S: Maintained F: tcg/riscv64/ -F: disas/riscv.[ch] +F: disas/riscv*.[ch] =20 S390 TCG target M: Richard Henderson diff --git a/disas/meson.build b/disas/meson.build index bbfa119783..d549b9b072 100644 --- a/disas/meson.build +++ b/disas/meson.build @@ -7,7 +7,8 @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips= .c', 'nanomips.c')) common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files( 'riscv.c', 'riscv-xthead.c', - 'riscv-xventana.c' + 'riscv-xventana.c', + 'riscv-zbr.c' )) common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) diff --git a/disas/riscv-zbr.c b/disas/riscv-zbr.c new file mode 100644 index 0000000000..b8bde6026a --- /dev/null +++ b/disas/riscv-zbr.c @@ -0,0 +1,78 @@ +/* + * QEMU RISC-V Disassembler for Zbr v0.93 (unratified) + * + * Copyright (c) 2023 Rivos Inc + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "disas/riscv.h" +#include "disas/riscv-zbr.h" + +typedef enum { + /* 0 is reserved for rv_op_illegal. */ + rv_op_crc32_b =3D 1, + rv_op_crc32_h =3D 2, + rv_op_crc32_w =3D 3, + rv_op_crc32_d =3D 4, + rv_op_crc32c_b =3D 5, + rv_op_crc32c_h =3D 6, + rv_op_crc32c_w =3D 7, + rv_op_crc32c_d =3D 8, +} rv_zbr_op; + +const rv_opcode_data rv_zbr_opcode_data[] =3D { + { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, + { "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, +}; + +void decode_zbr(rv_decode *dec, rv_isa isa) +{ + rv_inst inst =3D dec->inst; + rv_opcode op =3D rv_op_illegal; + + switch ((inst >> 0) & 0b1111111) { + case 0b0010011: + switch ((inst >> 12) & 0b111) { + case 0b001: + switch ((inst >> 20 & 0b111111111111)) { + case 0b011000010000: + op =3D rv_op_crc32_b; + break; + case 0b011000010001: + op =3D rv_op_crc32_h; + break; + case 0b011000010010: + op =3D rv_op_crc32_w; + break; + case 0b011000010011: + op =3D rv_op_crc32_d; + break; + case 0b011000011000: + op =3D rv_op_crc32c_b; + break; + case 0b011000011001: + op =3D rv_op_crc32c_h; + break; + case 0b011000011010: + op =3D rv_op_crc32c_w; + break; + case 0b011000011011: + op =3D rv_op_crc32c_d; + break; + } + break; + } + break; + } + dec->op =3D op; +} diff --git a/disas/riscv-zbr.h b/disas/riscv-zbr.h new file mode 100644 index 0000000000..327cdaea17 --- /dev/null +++ b/disas/riscv-zbr.h @@ -0,0 +1,18 @@ +/* + * QEMU RISC-V Disassembler for Zbr v0.93 (unratified) + * + * Copyright (c) 2023 Rivos Inc + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef DISAS_RISCV_ZBR_H +#define DISAS_RISCV_ZBR_H + +#include "disas/riscv.h" + +extern const rv_opcode_data rv_zbr_opcode_data[]; + +void decode_zbr(rv_decode *, rv_isa); + +#endif /* DISAS_RISCV_ZBR_H */ diff --git a/disas/riscv.c b/disas/riscv.c index 6f2667482d..ebb77ea4ee 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -27,6 +27,9 @@ #include "disas/riscv-xthead.h" #include "disas/riscv-xventana.h" =20 +/* Unratified extensions */ +#include "disas/riscv-zbr.h" + typedef enum { /* 0 is reserved for rv_op_illegal. */ rv_op_lui =3D 1, @@ -5434,6 +5437,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, = rv_inst inst, { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair }, { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondo= ps }, + { has_zbr_p, rv_zbr_opcode_data, decode_zbr }, }; =20 for (size_t i =3D 0; i < ARRAY_SIZE(decoders); i++) { --=20 2.48.1