From nobody Sun Apr 12 00:58:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772500629888142.8809170755917; Mon, 2 Mar 2026 17:17:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vxENe-00053t-SC; Mon, 02 Mar 2026 20:16:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vxENL-0004zo-Hr for qemu-devel@nongnu.org; Mon, 02 Mar 2026 20:16:40 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vxENE-00088Y-Sn for qemu-devel@nongnu.org; Mon, 02 Mar 2026 20:16:36 -0500 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Cx68JsNqZpG+MWAA--.3085S3; Tue, 03 Mar 2026 09:16:28 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by front1 (Coremail) with SMTP id qMiowJCx_8JfNqZpFmpNAA--.16102S10; Tue, 03 Mar 2026 09:16:28 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: Bibo Mao Subject: [PULL 8/8] target/loongarch: Add some CPUCFG bits with host CPU model Date: Tue, 3 Mar 2026 08:51:01 +0800 Message-Id: <20260303005101.3561064-9-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20260303005101.3561064-1-gaosong@loongson.cn> References: <20260303005101.3561064-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCx_8JfNqZpFmpNAA--.16102S10 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.968, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.495, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1772500632485139100 Content-Type: text/plain; charset="utf-8" From: Bibo Mao Some CPUCFG capability bits depend on KVM host hypervsior and they are detected on QEMU. However some CPUCFG bits are irrelative with hypervsior, here these bits are checked from host machine and set for VM with host CPU model. Signed-off-by: Bibo Mao Reviewed-by: Song Gao Signed-off-by: Song Gao --- target/loongarch/cpu.c | 36 +++++++++++++++++++++++++++++++++++- target/loongarch/cpu.h | 8 ++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 37950456b4..8e8b10505d 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -532,7 +532,7 @@ static uint32_t get_host_cpucfg(int number) =20 static void loongarch_host_initfn(Object *obj) { - uint32_t data; + uint32_t data, cpucfg, field; uint64_t cpuid; LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); =20 @@ -542,6 +542,40 @@ static void loongarch_host_initfn(Object *obj) cpu->env.cpucfg[0] =3D data; } =20 + /* + * There is no exception in KVM hypervisor when these intructions are + * executed if HW support, KVM hypervisor cannot control this. + * + * Set cpucfg bits which cannot be controlled by KVM hypervisor. + */ + data =3D get_host_cpucfg(2); + cpucfg =3D cpu->env.cpucfg[2]; + field =3D FIELD_EX32(data, CPUCFG2, FRECIPE); + cpucfg =3D FIELD_DP32(cpucfg, CPUCFG2, FRECIPE, field); + field =3D FIELD_EX32(data, CPUCFG2, DIV32); + cpucfg =3D FIELD_DP32(cpucfg, CPUCFG2, DIV32, field); + field =3D FIELD_EX32(data, CPUCFG2, LAM_BH); + cpucfg =3D FIELD_DP32(cpucfg, CPUCFG2, LAM_BH, field); + field =3D FIELD_EX32(data, CPUCFG2, LAMCAS); + cpucfg =3D FIELD_DP32(cpucfg, CPUCFG2, LAMCAS, field); + field =3D FIELD_EX32(data, CPUCFG2, LLACQ_SCREL); + cpucfg =3D FIELD_DP32(cpucfg, CPUCFG2, LLACQ_SCREL, field); + field =3D FIELD_EX32(data, CPUCFG2, SCQ); + cpucfg =3D FIELD_DP32(cpucfg, CPUCFG2, SCQ, field); + cpu->env.cpucfg[2] =3D cpucfg; + + data =3D get_host_cpucfg(3); + cpucfg =3D cpu->env.cpucfg[3]; + field =3D FIELD_EX32(data, CPUCFG3, DBAR_HINTS); + cpucfg =3D FIELD_DP32(cpucfg, CPUCFG3, DBAR_HINTS, field); + field =3D FIELD_EX32(data, CPUCFG3, ALDORDER_STA); + cpucfg =3D FIELD_DP32(cpucfg, CPUCFG3, ALDORDER_STA, field); + field =3D FIELD_EX32(data, CPUCFG3, ASTORDER_STA); + cpucfg =3D FIELD_DP32(cpucfg, CPUCFG3, ASTORDER_STA, field); + field =3D FIELD_EX32(data, CPUCFG3, SLDORDER_STA); + cpucfg =3D FIELD_DP32(cpucfg, CPUCFG3, SLDORDER_STA, field); + cpu->env.cpucfg[3] =3D cpucfg; + cpuid =3D get_host_cpu_model(); if (cpuid) { cpu->env.cpu_id =3D cpuid; diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index fda8577a24..d2dfdc8520 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -147,6 +147,7 @@ FIELD(CPUCFG2, LSPW, 21, 1) FIELD(CPUCFG2, LAM, 22, 1) FIELD(CPUCFG2, HPTW, 24, 1) FIELD(CPUCFG2, FRECIPE, 25, 1) +FIELD(CPUCFG2, DIV32, 26, 1) FIELD(CPUCFG2, LAM_BH, 27, 1) FIELD(CPUCFG2, LAMCAS, 28, 1) FIELD(CPUCFG2, LLACQ_SCREL, 29, 1) @@ -165,6 +166,13 @@ FIELD(CPUCFG3, SPW_LVL, 8, 3) FIELD(CPUCFG3, SPW_HP_HF, 11, 1) FIELD(CPUCFG3, RVA, 12, 1) FIELD(CPUCFG3, RVAMAX, 13, 4) +FIELD(CPUCFG3, DBAR_HINTS, 17, 1) +FIELD(CPUCFG3, ALDORDER_CAP, 18, 1) +FIELD(CPUCFG3, ASTORDER_CAP, 19, 1) +FIELD(CPUCFG3, ALDORDER_STA, 20, 1) +FIELD(CPUCFG3, ASTORDER_STA, 21, 1) +FIELD(CPUCFG3, SLDORDER_CAP, 22, 1) +FIELD(CPUCFG3, SLDORDER_STA, 23, 1) =20 /* cpucfg[4] bits */ FIELD(CPUCFG4, CC_FREQ, 0, 32) --=20 2.52.0