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a=ed25519-sha256; t=1772554301; l=6739; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=D9wylAZdPgcJ+aQDVhLFS+pRm1WGV3wZik7OybQsd1Q=; b=XiDfH9X4hc44ZJ0rpDbRgtYCCQlI3weMh+W0pW3K8tUMN4eYRs6PX7czLw7Du5UcS/ExMkzEX cP4lWAsPgI0AB/lWZVP5xT4FnQVjafrjnfS87sKWBecetzBJA+sp2jb X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.322, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.141, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772554143787154100 Reviewed-by: Helge Deller Signed-off-by: Anton Johansson --- target/hppa/cpu.h | 11 ++++++++--- hw/hppa/machine.c | 4 ++-- hw/pci-host/astro.c | 2 +- target/hppa/cpu.c | 9 ++++++++- target/hppa/mem_helper.c | 39 +++++++++++---------------------------- 5 files changed, 30 insertions(+), 35 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 43b4882fb4..487f0f5e9e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -320,6 +320,11 @@ static inline const HPPACPUDef *hppa_def(CPUHPPAState = *env) return HPPA_CPU_GET_CLASS(env_cpu(env))->def; } =20 +static inline uint8_t hppa_phys_addr_bits(CPUHPPAState *env) +{ + return hppa_def(env)->phys_addr_bits; +} + static inline bool hppa_is_pa20(CPUHPPAState *env) { return hppa_def(env)->is_pa20; @@ -352,9 +357,9 @@ static inline vaddr hppa_form_gva(CPUHPPAState *env, ui= nt64_t spc, return hppa_form_gva_mask(env->gva_offset_mask, spc, off); } =20 -hwaddr hppa_abs_to_phys_pa1x(vaddr addr); -hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); -hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); +hwaddr hppa_abs_to_phys_pa1x(CPUHPPAState *env, vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w0(CPUHPPAState *env, vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w1(CPUHPPAState *env, vaddr addr); =20 /* * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 5d0d4de09e..bb6b7dc76c 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -181,12 +181,12 @@ static uint64_t linux_kernel_virt_to_phys(void *opaqu= e, uint64_t addr) =20 static uint64_t translate_pa10(void *dummy, uint64_t addr) { - return hppa_abs_to_phys_pa1x(addr); + return hppa_abs_to_phys_pa1x(cpu_env(first_cpu), addr); } =20 static uint64_t translate_pa20(void *dummy, uint64_t addr) { - return hppa_abs_to_phys_pa2_w0(addr); + return hppa_abs_to_phys_pa2_w0(cpu_env(first_cpu), addr); } =20 static HPPACPU *cpu[HPPA_MAX_CPUS]; diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 00a904277c..d38f81e553 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -303,7 +303,7 @@ static IOMMUTLBEntry astro_translate_iommu(IOMMUMemoryR= egion *iommu, * language which not-coincidentally matches the PSW.W=3D0 mapping. */ if (addr <=3D UINT32_MAX) { - entry =3D hppa_abs_to_phys_pa2_w0(addr); + entry =3D hppa_abs_to_phys_pa2_w0(cpu_env(first_cpu), addr); } else { entry =3D addr; } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index cc755da8be..b04bcfa6a0 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -282,7 +282,14 @@ static void hppa_cpu_class_base_init(ObjectClass *oc, = const void *data) HPPACPUClass *acc =3D HPPA_CPU_CLASS(oc); /* Make sure all CPU models define a HPPACPUDef */ g_assert(!object_class_is_abstract(oc) && data !=3D NULL); - acc->def =3D data; + if (data) { + acc->def =3D data; + /* + * Verify assumptions made in hppa_abs_to_phys_pa2_w1() on the size + * of the physical address space. + */ + g_assert(acc->def->phys_addr_bits <=3D 54); + } } =20 static void hppa_cpu_class_init(ObjectClass *oc, const void *data) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 9199d1e06a..9a11294f75 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -29,29 +29,12 @@ #include "hw/core/cpu.h" #include "trace.h" =20 -/* - * 64-bit (PA-RISC 2.0) machines are assumed to run PA-8700, and 32-bit - * machines 7300LC. This should give 44 and 32 bits of physical address - * space respectively. - * - * CPU model Physical address space bits - * PA-7000--7300LC 32 - * PA-8000--8600 40 - * PA-8700--8900 44 - * - * FIXME: However, the SeaBIOS firmware that is that tested against - * uses 40-bit physical addresses, despite supposedly running a C3700 - * with a PA-8700 cpu, so use 40-bits for 64-bit. - */ -#define HPPA_PHYS_ADDR_SPACE_BITS_PA20 40 -#define HPPA_PHYS_ADDR_SPACE_BITS_PA1X 32 - -hwaddr hppa_abs_to_phys_pa1x(vaddr addr) +hwaddr hppa_abs_to_phys_pa1x(CPUHPPAState *env, vaddr addr) { - return extract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA1X); + return extract64(addr, 0, hppa_phys_addr_bits(env)); } =20 -hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) +hwaddr hppa_abs_to_phys_pa2_w1(CPUHPPAState *env, vaddr addr) { /* * Figure H-8 "62-bit Absolute Accesses when PSW W-bit is 1" describes @@ -64,11 +47,11 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) * Since the supported physical address space is below 54 bits, the * H-8 algorithm is moot and all that is left is to truncate. */ - QEMU_BUILD_BUG_ON(HPPA_PHYS_ADDR_SPACE_BITS_PA20 > 54); - return sextract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); + const uint8_t pa =3D hppa_phys_addr_bits(env); + return sextract64(addr, 0, pa); } =20 -hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) +hwaddr hppa_abs_to_phys_pa2_w0(CPUHPPAState *env, vaddr addr) { /* * See Figure H-10, "Absolute Accesses when PSW W-bit is 0", @@ -89,7 +72,7 @@ hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) * is what can be seen on physical machines too. */ addr =3D (uint32_t)addr; - addr |=3D -1ull << (HPPA_PHYS_ADDR_SPACE_BITS_PA20 - 4); + addr |=3D -1ull << (hppa_phys_addr_bits(env) - 4); } return addr; } @@ -233,13 +216,13 @@ int hppa_get_physical_address(CPUHPPAState *env, vadd= r addr, int mmu_idx, if (MMU_IDX_MMU_DISABLED(mmu_idx)) { switch (mmu_idx) { case MMU_ABS_W_IDX: - phys =3D hppa_abs_to_phys_pa2_w1(addr); + phys =3D hppa_abs_to_phys_pa2_w1(env, addr); break; case MMU_ABS_IDX: if (hppa_is_pa20(env)) { - phys =3D hppa_abs_to_phys_pa2_w0(addr); + phys =3D hppa_abs_to_phys_pa2_w0(env, addr); } else { - phys =3D hppa_abs_to_phys_pa1x(addr); + phys =3D hppa_abs_to_phys_pa1x(env, addr); } break; default: @@ -580,7 +563,7 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong = r1, /* Align per the page size. */ ent->pa &=3D TARGET_PAGE_MASK << mask_shift; /* Ignore the bits beyond physical address space. */ - ent->pa =3D sextract64(ent->pa, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); + ent->pa =3D sextract64(ent->pa, 0, hppa_phys_addr_bits(env)); =20 ent->t =3D extract64(r2, 61, 1); ent->d =3D extract64(r2, 60, 1); --=20 2.52.0