From nobody Sat Apr 11 23:07:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1772554242; cv=none; d=zohomail.com; s=zohoarc; b=cVuON8VG9KAajMaLCAoVRgDyKqHPkx8D95WjxiR3C5wvvtZ9r5EOBA+wtrkYUVlDWZYLCihyHEqRbrhFUkRfpj/8yQp+qbtGZkJrOv1Ad7VuAT1PvFGN9tSDeZhUskFHqJMx/nwP5y1eHEJGMNH90zi33ZPwfTDfNspGXx+utPo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772554242; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=wDmHN0idygJwsT7yupDS5Js7du7AcI+kANWtIfJrTc4=; b=JN8uZF1639FyByMpJ1jzPRRMhfmS7pBxcAea9Rn0LS7ObSn7/H+CMh8r3du0oAeNSqEkmcCi6f6skHcpQIWNim03XpaEzdmZoSocx6Q5m70NzdAZM5eyDMPpsxvHKKwkMxo6rSK2Sux3xTTr27icut47bIoJWMr+efLyXSkzdw8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772554242687434.4017395580547; Tue, 3 Mar 2026 08:10:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vxSHz-00037T-RJ; Tue, 03 Mar 2026 11:08:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vxSHx-00034h-Gz for qemu-devel@nongnu.org; Tue, 03 Mar 2026 11:08:01 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vxSHu-0004tH-Ct for qemu-devel@nongnu.org; Tue, 03 Mar 2026 11:08:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=wDmHN0idygJwsT7yupDS5Js7du7AcI+kANWtIfJrTc4=; b=tUQdtF1RpsDUvZI UEQ4cDC/qFM7iAP8O7Pdt5W2ir3IeCQS6kxx4oGYDrTKDtgV5IxaaBadI7w2l5Wkl0dLlp1dN6z/t ynscGsOQbdYdXGfbSgfc1aGzRwm/I4k6qYQshEYg1Y2Xa/BqedKS3Rza3oGQ2tAc1tOgZPIJa3Z1D X4=; Date: Tue, 03 Mar 2026 17:11:28 +0100 Subject: [PATCH v5 1/4] hppa: Restructure CPU Class heirarchy MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-hppa-c3600-v5-1-277bfe6b40b8@rev.ng> References: <20260303-hppa-c3600-v5-0-277bfe6b40b8@rev.ng> In-Reply-To: <20260303-hppa-c3600-v5-0-277bfe6b40b8@rev.ng> To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , Anton Johansson X-Developer-Signature: v=1; a=ed25519-sha256; t=1772554301; l=6878; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=QZx6MxbU+jQI78caN/HWtT+asuMMqXM6wk6LNQt4SWk=; b=+PqMUtVeEGD8CO2m8ZxgeNO3+ZlaAdDu1tUnYwF3DtdsDsLzlsEO63OObM2d8nOc6nzQeiPmV XHQSyGMMrQYAyaKeqSVAmPV5tQR9WdjKH7sqpp1K2RbakSQ8xcu4Mgl X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.322, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.141, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772554245060154100 Clarifies current CPU model names, assuming 32-bit HPPA runs a PA-7300LC whereas 64-bit runs a PA-8700. The PA-8500 model is added, which will later be used by the A400 machine. All CPU models are made into children of the now abstract TYPE_HPPA_CPU base class. References to "hppa/hppa64" models in test cases are also updated. Reviewed-by: Helge Deller Signed-off-by: Anton Johansson --- target/hppa/cpu-qom.h | 8 +++++++- hw/hppa/machine.c | 21 +++++++++++++-------- linux-user/hppa/elfload.c | 2 +- target/hppa/cpu.c | 25 ++++++++++++++++++++----- tests/qtest/machine-none-test.c | 2 +- 5 files changed, 42 insertions(+), 16 deletions(-) diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index 5c454bf543..7541c25b3d 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -23,7 +23,13 @@ #include "hw/core/cpu.h" =20 #define TYPE_HPPA_CPU "hppa-cpu" -#define TYPE_HPPA64_CPU "hppa64-cpu" + +#define HPPA_CPU_TYPE_SUFFIX "-" TYPE_HPPA_CPU +#define HPPA_CPU_TYPE_NAME(name) (name HPPA_CPU_TYPE_SUFFIX) + +#define TYPE_HPPA_CPU_PA_7300LC HPPA_CPU_TYPE_NAME("pa-7300lc") +#define TYPE_HPPA_CPU_PA_8500 HPPA_CPU_TYPE_NAME("pa-8500") +#define TYPE_HPPA_CPU_PA_8700 HPPA_CPU_TYPE_NAME("pa-8700") =20 OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU) =20 diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index f55e84529f..5d0d4de09e 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -801,13 +801,13 @@ static void hppa_machine_common_class_init(ObjectClas= s *oc, const void *data) static void HP_B160L_machine_init_class_init(ObjectClass *oc, const void *= data) { static const char * const valid_cpu_types[] =3D { - TYPE_HPPA_CPU, + TYPE_HPPA_CPU_PA_7300LC, NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "HP B160L workstation"; - mc->default_cpu_type =3D TYPE_HPPA_CPU; + mc->default_cpu_type =3D TYPE_HPPA_CPU_PA_7300LC; mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_B160L_init; mc->is_default =3D true; @@ -817,13 +817,13 @@ static void HP_B160L_machine_init_class_init(ObjectCl= ass *oc, const void *data) static void HP_C3700_machine_init_class_init(ObjectClass *oc, const void *= data) { static const char * const valid_cpu_types[] =3D { - TYPE_HPPA64_CPU, + TYPE_HPPA_CPU_PA_8700, NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "HP C3700 workstation"; - mc->default_cpu_type =3D TYPE_HPPA64_CPU; + mc->default_cpu_type =3D TYPE_HPPA_CPU_PA_8700; mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_C3700_init; mc->max_cpus =3D HPPA_MAX_CPUS; @@ -833,13 +833,13 @@ static void HP_C3700_machine_init_class_init(ObjectCl= ass *oc, const void *data) static void HP_A400_machine_init_class_init(ObjectClass *oc, const void *d= ata) { static const char * const valid_cpu_types[] =3D { - TYPE_HPPA64_CPU, + TYPE_HPPA_CPU_PA_8500, NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "HP A400-44 workstation"; - mc->default_cpu_type =3D TYPE_HPPA64_CPU; + mc->default_cpu_type =3D TYPE_HPPA_CPU_PA_8500; mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_A400_init; mc->max_cpus =3D HPPA_MAX_CPUS; @@ -849,13 +849,18 @@ static void HP_A400_machine_init_class_init(ObjectCla= ss *oc, const void *data) static void HP_715_machine_init_class_init(ObjectClass *oc, const void *da= ta) { static const char * const valid_cpu_types[] =3D { - TYPE_HPPA_CPU, + TYPE_HPPA_CPU_PA_7300LC, NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "HP 715/64 workstation"; - mc->default_cpu_type =3D TYPE_HPPA_CPU; + /* + * Although the 715 workstation should use a 7100LC, it can be safely + * modeled as a 7300LC as the difference is a moving of the L1 data ca= che + * to on-chip. + */ + mc->default_cpu_type =3D TYPE_HPPA_CPU_PA_7300LC; mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_715_init; /* can only support up to max. 8 CPUs due inventory major numbers */ diff --git a/linux-user/hppa/elfload.c b/linux-user/hppa/elfload.c index 4600708702..7f7ece6dc1 100644 --- a/linux-user/hppa/elfload.c +++ b/linux-user/hppa/elfload.c @@ -8,7 +8,7 @@ =20 const char *get_elf_cpu_model(uint32_t eflags) { - return "hppa"; + return "pa-7300lc"; } =20 const char *get_elf_platform(CPUState *cs) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 714f3bbdaf..910a919923 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -207,7 +207,9 @@ static void hppa_cpu_initfn(Object *obj) { CPUHPPAState *env =3D cpu_env(CPU(obj)); =20 - env->is_pa20 =3D !!object_dynamic_cast(obj, TYPE_HPPA64_CPU); + env->is_pa20 =3D !!object_dynamic_cast(obj, TYPE_HPPA_CPU_PA_8500) || + !!object_dynamic_cast(obj, TYPE_HPPA_CPU_PA_8700); + } =20 static void hppa_cpu_reset_hold(Object *obj, ResetType type) @@ -236,9 +238,14 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType= type) =20 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) { - g_autofree char *typename =3D g_strconcat(cpu_model, "-cpu", NULL); + ObjectClass *oc; + char *typename; + + typename =3D g_strdup_printf(HPPA_CPU_TYPE_NAME("%s"), cpu_model); + oc =3D object_class_by_name(typename); + g_free(typename); =20 - return object_class_by_name(typename); + return oc; } =20 #ifndef CONFIG_USER_ONLY @@ -314,12 +321,20 @@ static const TypeInfo hppa_cpu_type_infos[] =3D { .instance_size =3D sizeof(HPPACPU), .instance_align =3D __alignof(HPPACPU), .instance_init =3D hppa_cpu_initfn, - .abstract =3D false, + .abstract =3D true, .class_size =3D sizeof(HPPACPUClass), .class_init =3D hppa_cpu_class_init, }, { - .name =3D TYPE_HPPA64_CPU, + .name =3D TYPE_HPPA_CPU_PA_7300LC, + .parent =3D TYPE_HPPA_CPU, + }, + { + .name =3D TYPE_HPPA_CPU_PA_8500, + .parent =3D TYPE_HPPA_CPU, + }, + { + .name =3D TYPE_HPPA_CPU_PA_8700, .parent =3D TYPE_HPPA_CPU, }, }; diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-tes= t.c index b6a87d27ed..f871056fa4 100644 --- a/tests/qtest/machine-none-test.c +++ b/tests/qtest/machine-none-test.c @@ -48,7 +48,7 @@ static struct arch2cpu cpus_map[] =3D { { "tricore", "tc1796" }, { "xtensa", "dc233c" }, { "xtensaeb", "fsf" }, - { "hppa", "hppa" }, + { "hppa", "pa-7300lc" }, { "riscv64", "rv64" }, { "riscv32", "rv32" }, { "rx", "rx62n" }, --=20 2.52.0 From nobody Sat Apr 11 23:07:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=DHiMP2gsRiouzbzyaVlVV/Jul3SQWrBQapVvZ+Un+gc=; b=odkPVwY3d+30jHg MDAfAy2kQReExkF6sWLp7ZuglfVtzInh310Wedf45Vj92PYBjGefoGokgjjgw2xtrQeZuPL+yqtob y6c9x6QKwekyT/jqGtr1vA4V8F7aqxYJ2lPDfqad+E8n6nS9Wk8NMPRrMNyw13XoLjWU5YksoM9Xd hM=; Date: Tue, 03 Mar 2026 17:11:29 +0100 Subject: [PATCH v5 2/4] hppa: Introduce HPPACPUDef MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-hppa-c3600-v5-2-277bfe6b40b8@rev.ng> References: <20260303-hppa-c3600-v5-0-277bfe6b40b8@rev.ng> In-Reply-To: <20260303-hppa-c3600-v5-0-277bfe6b40b8@rev.ng> To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , Anton Johansson X-Developer-Signature: v=1; a=ed25519-sha256; t=1772554301; l=4495; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=zxAV25/04DWo+NOxJWlRaG0/QxsZu2z0IOZo2QXFUy0=; b=sYXfJDVFLzkc/0f4uK7K4oZMU7lrpeF2nX6MlRddMuG2QAla3MmaseuTvCDmVT7ii6LsTAPXq /oXoe/cLA+6Dte4gc7BIa32NxH6//VEYpQgYvnqYukSeavhaby0L9pC X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.322, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.141, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772554134980158500 In preparation for handling different physical address spaces sizes (32, 40, 44 bits) a CPU model configuration struct is added to HPPACPUClass. Two fields are added describing the size of the physical address space, and whether or not the CPU uses the PA-RISC 2.0 architecture. The latter was previously a field in CPUHPPAState. phys_addr_bits is currently set but unused, and will be used in the following commit. Likewise, PA-8700 is moved to use 44 bit physical addresses in a followup commit to not bisection. Reviewed-by: Helge Deller Signed-off-by: Anton Johansson --- target/hppa/cpu.h | 24 ++++++++++++++++++++---- target/hppa/cpu.c | 31 +++++++++++++++++++++---------- 2 files changed, 41 insertions(+), 14 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 092e647ccf..43b4882fb4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -270,8 +270,6 @@ typedef struct CPUArchState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - bool is_pa20; - target_ulong kernel_entry; /* Linux kernel was loaded here */ target_ulong cmdline_or_bootorder; target_ulong initrd_base, initrd_end; @@ -290,6 +288,18 @@ struct ArchCPU { QEMUTimer *alarm_timer; }; =20 +/** + * HPPACPUDef: + * @phys_addr_bits: Number of bits in the physical address space. + * @is_pa20: Whether the CPU model follows the PA-RISC 2.0 or 1.1 spec. + * + * Configuration options for a HPPA CPU model. + */ +typedef struct HPPACPUDef { + uint8_t phys_addr_bits; + bool is_pa20; +} HPPACPUDef; + /** * HPPACPUClass: * @parent_realize: The parent class' realize handler. @@ -302,11 +312,17 @@ struct HPPACPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; + const HPPACPUDef *def; }; =20 -static inline bool hppa_is_pa20(const CPUHPPAState *env) +static inline const HPPACPUDef *hppa_def(CPUHPPAState *env) +{ + return HPPA_CPU_GET_CLASS(env_cpu(env))->def; +} + +static inline bool hppa_is_pa20(CPUHPPAState *env) { - return env->is_pa20; + return hppa_def(env)->is_pa20; } =20 static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 910a919923..cc755da8be 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -203,15 +203,6 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error= **errp) tcg_cflags_set(cs, CF_PCREL); } =20 -static void hppa_cpu_initfn(Object *obj) -{ - CPUHPPAState *env =3D cpu_env(CPU(obj)); - - env->is_pa20 =3D !!object_dynamic_cast(obj, TYPE_HPPA_CPU_PA_8500) || - !!object_dynamic_cast(obj, TYPE_HPPA_CPU_PA_8700); - -} - static void hppa_cpu_reset_hold(Object *obj, ResetType type) { HPPACPUClass *scc =3D HPPA_CPU_GET_CLASS(obj); @@ -286,6 +277,14 @@ static const TCGCPUOps hppa_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 +static void hppa_cpu_class_base_init(ObjectClass *oc, const void *data) +{ + HPPACPUClass *acc =3D HPPA_CPU_CLASS(oc); + /* Make sure all CPU models define a HPPACPUDef */ + g_assert(!object_class_is_abstract(oc) && data !=3D NULL); + acc->def =3D data; +} + static void hppa_cpu_class_init(ObjectClass *oc, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -320,22 +319,34 @@ static const TypeInfo hppa_cpu_type_infos[] =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(HPPACPU), .instance_align =3D __alignof(HPPACPU), - .instance_init =3D hppa_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(HPPACPUClass), .class_init =3D hppa_cpu_class_init, + .class_base_init =3D hppa_cpu_class_base_init, }, { .name =3D TYPE_HPPA_CPU_PA_7300LC, .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 32, + .is_pa20 =3D false, + }, }, { .name =3D TYPE_HPPA_CPU_PA_8500, .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 40, + .is_pa20 =3D true, + }, }, { .name =3D TYPE_HPPA_CPU_PA_8700, .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 40, + .is_pa20 =3D true, + }, }, }; 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a=ed25519-sha256; t=1772554301; l=6739; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=D9wylAZdPgcJ+aQDVhLFS+pRm1WGV3wZik7OybQsd1Q=; b=XiDfH9X4hc44ZJ0rpDbRgtYCCQlI3weMh+W0pW3K8tUMN4eYRs6PX7czLw7Du5UcS/ExMkzEX cP4lWAsPgI0AB/lWZVP5xT4FnQVjafrjnfS87sKWBecetzBJA+sp2jb X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.322, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.141, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772554143787154100 Reviewed-by: Helge Deller Signed-off-by: Anton Johansson --- target/hppa/cpu.h | 11 ++++++++--- hw/hppa/machine.c | 4 ++-- hw/pci-host/astro.c | 2 +- target/hppa/cpu.c | 9 ++++++++- target/hppa/mem_helper.c | 39 +++++++++++---------------------------- 5 files changed, 30 insertions(+), 35 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 43b4882fb4..487f0f5e9e 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -320,6 +320,11 @@ static inline const HPPACPUDef *hppa_def(CPUHPPAState = *env) return HPPA_CPU_GET_CLASS(env_cpu(env))->def; } =20 +static inline uint8_t hppa_phys_addr_bits(CPUHPPAState *env) +{ + return hppa_def(env)->phys_addr_bits; +} + static inline bool hppa_is_pa20(CPUHPPAState *env) { return hppa_def(env)->is_pa20; @@ -352,9 +357,9 @@ static inline vaddr hppa_form_gva(CPUHPPAState *env, ui= nt64_t spc, return hppa_form_gva_mask(env->gva_offset_mask, spc, off); } =20 -hwaddr hppa_abs_to_phys_pa1x(vaddr addr); -hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); -hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); +hwaddr hppa_abs_to_phys_pa1x(CPUHPPAState *env, vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w0(CPUHPPAState *env, vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w1(CPUHPPAState *env, vaddr addr); =20 /* * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 5d0d4de09e..bb6b7dc76c 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -181,12 +181,12 @@ static uint64_t linux_kernel_virt_to_phys(void *opaqu= e, uint64_t addr) =20 static uint64_t translate_pa10(void *dummy, uint64_t addr) { - return hppa_abs_to_phys_pa1x(addr); + return hppa_abs_to_phys_pa1x(cpu_env(first_cpu), addr); } =20 static uint64_t translate_pa20(void *dummy, uint64_t addr) { - return hppa_abs_to_phys_pa2_w0(addr); + return hppa_abs_to_phys_pa2_w0(cpu_env(first_cpu), addr); } =20 static HPPACPU *cpu[HPPA_MAX_CPUS]; diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 00a904277c..d38f81e553 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -303,7 +303,7 @@ static IOMMUTLBEntry astro_translate_iommu(IOMMUMemoryR= egion *iommu, * language which not-coincidentally matches the PSW.W=3D0 mapping. */ if (addr <=3D UINT32_MAX) { - entry =3D hppa_abs_to_phys_pa2_w0(addr); + entry =3D hppa_abs_to_phys_pa2_w0(cpu_env(first_cpu), addr); } else { entry =3D addr; } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index cc755da8be..b04bcfa6a0 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -282,7 +282,14 @@ static void hppa_cpu_class_base_init(ObjectClass *oc, = const void *data) HPPACPUClass *acc =3D HPPA_CPU_CLASS(oc); /* Make sure all CPU models define a HPPACPUDef */ g_assert(!object_class_is_abstract(oc) && data !=3D NULL); - acc->def =3D data; + if (data) { + acc->def =3D data; + /* + * Verify assumptions made in hppa_abs_to_phys_pa2_w1() on the size + * of the physical address space. + */ + g_assert(acc->def->phys_addr_bits <=3D 54); + } } =20 static void hppa_cpu_class_init(ObjectClass *oc, const void *data) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 9199d1e06a..9a11294f75 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -29,29 +29,12 @@ #include "hw/core/cpu.h" #include "trace.h" =20 -/* - * 64-bit (PA-RISC 2.0) machines are assumed to run PA-8700, and 32-bit - * machines 7300LC. This should give 44 and 32 bits of physical address - * space respectively. - * - * CPU model Physical address space bits - * PA-7000--7300LC 32 - * PA-8000--8600 40 - * PA-8700--8900 44 - * - * FIXME: However, the SeaBIOS firmware that is that tested against - * uses 40-bit physical addresses, despite supposedly running a C3700 - * with a PA-8700 cpu, so use 40-bits for 64-bit. - */ -#define HPPA_PHYS_ADDR_SPACE_BITS_PA20 40 -#define HPPA_PHYS_ADDR_SPACE_BITS_PA1X 32 - -hwaddr hppa_abs_to_phys_pa1x(vaddr addr) +hwaddr hppa_abs_to_phys_pa1x(CPUHPPAState *env, vaddr addr) { - return extract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA1X); + return extract64(addr, 0, hppa_phys_addr_bits(env)); } =20 -hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) +hwaddr hppa_abs_to_phys_pa2_w1(CPUHPPAState *env, vaddr addr) { /* * Figure H-8 "62-bit Absolute Accesses when PSW W-bit is 1" describes @@ -64,11 +47,11 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) * Since the supported physical address space is below 54 bits, the * H-8 algorithm is moot and all that is left is to truncate. */ - QEMU_BUILD_BUG_ON(HPPA_PHYS_ADDR_SPACE_BITS_PA20 > 54); - return sextract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); + const uint8_t pa =3D hppa_phys_addr_bits(env); + return sextract64(addr, 0, pa); } =20 -hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) +hwaddr hppa_abs_to_phys_pa2_w0(CPUHPPAState *env, vaddr addr) { /* * See Figure H-10, "Absolute Accesses when PSW W-bit is 0", @@ -89,7 +72,7 @@ hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) * is what can be seen on physical machines too. */ addr =3D (uint32_t)addr; - addr |=3D -1ull << (HPPA_PHYS_ADDR_SPACE_BITS_PA20 - 4); + addr |=3D -1ull << (hppa_phys_addr_bits(env) - 4); } return addr; } @@ -233,13 +216,13 @@ int hppa_get_physical_address(CPUHPPAState *env, vadd= r addr, int mmu_idx, if (MMU_IDX_MMU_DISABLED(mmu_idx)) { switch (mmu_idx) { case MMU_ABS_W_IDX: - phys =3D hppa_abs_to_phys_pa2_w1(addr); + phys =3D hppa_abs_to_phys_pa2_w1(env, addr); break; case MMU_ABS_IDX: if (hppa_is_pa20(env)) { - phys =3D hppa_abs_to_phys_pa2_w0(addr); + phys =3D hppa_abs_to_phys_pa2_w0(env, addr); } else { - phys =3D hppa_abs_to_phys_pa1x(addr); + phys =3D hppa_abs_to_phys_pa1x(env, addr); } break; default: @@ -580,7 +563,7 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong = r1, /* Align per the page size. */ ent->pa &=3D TARGET_PAGE_MASK << mask_shift; /* Ignore the bits beyond physical address space. */ - ent->pa =3D sextract64(ent->pa, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); + ent->pa =3D sextract64(ent->pa, 0, hppa_phys_addr_bits(env)); =20 ent->t =3D extract64(r2, 61, 1); ent->d =3D extract64(r2, 60, 1); --=20 2.52.0 From nobody Sat Apr 11 23:07:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1772554134; cv=none; d=zohomail.com; s=zohoarc; b=iRI4+uFckxUbQXCQr1B7VC5Mpm+uO97QkUBXyOy1UhmNg+l+WVF0snsEsOMBbpAtMZBLtLhv0tUs0LRnjZBIyZcciHQjecP1JMuvLy53UJ0+0DmmkQ0oNRsoxSSM7FfrdJ/jFhjvypq/kDs+A0sA4hD8EO3f4c8UQYzH/E8pVx8= ARC-Message-Signature: i=1; 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Date: Tue, 03 Mar 2026 17:11:31 +0100 Subject: [PATCH v5 4/4] hppa: Use 44 bit physical addresses for PA-8700 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260303-hppa-c3600-v5-4-277bfe6b40b8@rev.ng> References: <20260303-hppa-c3600-v5-0-277bfe6b40b8@rev.ng> In-Reply-To: <20260303-hppa-c3600-v5-0-277bfe6b40b8@rev.ng> To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , Anton Johansson X-Developer-Signature: v=1; a=ed25519-sha256; t=1772554301; l=1705; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=u5SQAlRQN5Nij60p9+jamxH9PUO8l8fPlBFoHvYtsa0=; b=CD9Yy6aLUy3qXhSqWcPZM7T0+LuoskSUcQFiertKHlrUCzc7xvMH7ZrPgMt40K5SzERhTnchh 2CtNgEJaPmgCpSiUi5NuZjW8hI9/X+RYHyXLgkOzYk95N2RJ7c5xETr X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.322, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.141, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772554136518158501 This is in line with the PA-8700 specification which demands 44 bits. However, this change breaks the SeaBIOS functional tests as the firmware assumes 40 bit physical addresses. Therefore, change the functional tests to instead run on an A400 which has the expected physical address space size. Reviewed-by: Helge Deller Signed-off-by: Anton Johansson --- target/hppa/cpu.c | 2 +- tests/functional/hppa/test_seabios.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index b04bcfa6a0..bf54aac96c 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -351,7 +351,7 @@ static const TypeInfo hppa_cpu_type_infos[] =3D { .name =3D TYPE_HPPA_CPU_PA_8700, .parent =3D TYPE_HPPA_CPU, .class_data =3D &(const HPPACPUDef) { - .phys_addr_bits =3D 40, + .phys_addr_bits =3D 44, .is_pa20 =3D true, }, }, diff --git a/tests/functional/hppa/test_seabios.py b/tests/functional/hppa/= test_seabios.py index 661b2464e1..bdb9d534ef 100755 --- a/tests/functional/hppa/test_seabios.py +++ b/tests/functional/hppa/test_seabios.py @@ -12,7 +12,7 @@ class HppaSeabios(QemuSystemTest): =20 timeout =3D 5 - MACH_BITS =3D {'B160L': 32, 'C3700': 64} + MACH_BITS =3D {'B160L': 32, 'A400': 64} =20 def boot_seabios(self): mach =3D self.machine @@ -28,7 +28,7 @@ def test_hppa_32(self): self.boot_seabios() =20 def test_hppa_64(self): - self.set_machine('C3700') + self.set_machine('A400') self.boot_seabios() =20 if __name__ =3D=3D '__main__': --=20 2.52.0