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charset="utf-8" This makes it easier to add new MMIO registers for tracing and removes the unnecessary complexity introduced by amdvi_mmio_(low/high) array. Signed-off-by: Sairaj Kodilkar Reviewed-by: Vasant Hegde Reviewed-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 76 ++++++++++++++++----------------------------- hw/i386/amd_iommu.h | 4 --- 2 files changed, 27 insertions(+), 53 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 789e09d6f2bc..f5aa9c763d02 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -35,29 +35,6 @@ #include "kvm/kvm_i386.h" #include "qemu/iova-tree.h" =20 -/* used AMD-Vi MMIO registers */ -const char *amdvi_mmio_low[] =3D { - "AMDVI_MMIO_DEVTAB_BASE", - "AMDVI_MMIO_CMDBUF_BASE", - "AMDVI_MMIO_EVTLOG_BASE", - "AMDVI_MMIO_CONTROL", - "AMDVI_MMIO_EXCL_BASE", - "AMDVI_MMIO_EXCL_LIMIT", - "AMDVI_MMIO_EXT_FEATURES", - "AMDVI_MMIO_PPR_BASE", - "UNHANDLED" -}; -const char *amdvi_mmio_high[] =3D { - "AMDVI_MMIO_COMMAND_HEAD", - "AMDVI_MMIO_COMMAND_TAIL", - "AMDVI_MMIO_EVTLOG_HEAD", - "AMDVI_MMIO_EVTLOG_TAIL", - "AMDVI_MMIO_STATUS", - "AMDVI_MMIO_PPR_HEAD", - "AMDVI_MMIO_PPR_TAIL", - "UNHANDLED" -}; - struct AMDVIAddressSpace { PCIBus *bus; /* PCIBus (for bus number) */ uint8_t devfn; /* device function */ @@ -1484,31 +1461,31 @@ static void amdvi_cmdbuf_run(AMDVIState *s) } } =20 -static inline uint8_t amdvi_mmio_get_index(hwaddr addr) -{ - uint8_t index =3D (addr & ~0x2000) / 8; - - if ((addr & 0x2000)) { - /* high table */ - index =3D index >=3D AMDVI_MMIO_REGS_HIGH ? AMDVI_MMIO_REGS_HIGH := index; - } else { - index =3D index >=3D AMDVI_MMIO_REGS_LOW ? AMDVI_MMIO_REGS_LOW : i= ndex; +static inline +const char *amdvi_mmio_get_name(hwaddr addr) +{ + /* Return MMIO names as string literals */ + switch (addr) { +#define MMIO_REG_TO_STRING(mmio_reg) case mmio_reg: return #mmio_reg + MMIO_REG_TO_STRING(AMDVI_MMIO_DEVICE_TABLE); + MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_BASE); + MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_BASE); + MMIO_REG_TO_STRING(AMDVI_MMIO_CONTROL); + MMIO_REG_TO_STRING(AMDVI_MMIO_EXCL_BASE); + MMIO_REG_TO_STRING(AMDVI_MMIO_EXCL_LIMIT); + MMIO_REG_TO_STRING(AMDVI_MMIO_EXT_FEATURES); + MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_HEAD); + MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_TAIL); + MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_HEAD); + MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_TAIL); + MMIO_REG_TO_STRING(AMDVI_MMIO_STATUS); + MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_BASE); + MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_HEAD); + MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_TAIL); +#undef MMIO_REG_TO_STRING + default: + return "UNHANDLED"; } - - return index; -} - -static void amdvi_mmio_trace_read(hwaddr addr, unsigned size) -{ - uint8_t index =3D amdvi_mmio_get_index(addr); - trace_amdvi_mmio_read(amdvi_mmio_low[index], addr, size, addr & ~0x07); -} - -static void amdvi_mmio_trace_write(hwaddr addr, unsigned size, uint64_t va= l) -{ - uint8_t index =3D amdvi_mmio_get_index(addr); - trace_amdvi_mmio_write(amdvi_mmio_low[index], addr, size, val, - addr & ~0x07); } =20 static uint64_t amdvi_mmio_read(void *opaque, hwaddr addr, unsigned size) @@ -1528,7 +1505,7 @@ static uint64_t amdvi_mmio_read(void *opaque, hwaddr = addr, unsigned size) } else if (size =3D=3D 8) { val =3D amdvi_readq(s, addr); } - amdvi_mmio_trace_read(addr, size); + trace_amdvi_mmio_read(amdvi_mmio_get_name(addr), addr, size, addr & ~0= x07); =20 return val; } @@ -1684,7 +1661,8 @@ static void amdvi_mmio_write(void *opaque, hwaddr add= r, uint64_t val, return; } =20 - amdvi_mmio_trace_write(addr, size, val); + trace_amdvi_mmio_write(amdvi_mmio_get_name(addr), addr, size, val, off= set); + switch (addr & ~0x07) { case AMDVI_MMIO_CONTROL: amdvi_mmio_reg_write(s, size, val, addr); diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 302ccca5121f..ca4ff9fffee3 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -45,10 +45,6 @@ #define AMDVI_CAPAB_FLAG_IOTLBSUP (1 << 24) #define AMDVI_CAPAB_INIT_TYPE (3 << 16) =20 -/* No. of used MMIO registers */ -#define AMDVI_MMIO_REGS_HIGH 7 -#define AMDVI_MMIO_REGS_LOW 8 - /* MMIO registers */ #define AMDVI_MMIO_DEVICE_TABLE 0x0000 #define AMDVI_MMIO_COMMAND_BASE 0x0008 --=20 2.34.1 From nobody Fri Apr 10 17:41:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Current code uses 32 bit destination ID irrespective of the fact that guest has enabled x2APIC support through control register[XTEn] and completely depends on command line parameter xtsup=3Don. This is not a correct hardware behaviour and can cause problems in the guest which has not enabled XT mode. Introduce new flag "xten", which is enabled when guest writes 1 to the control register bit 50 (XTEn). Also, add a new subsection in `VMStateDescription` for backward compatibility during vm migration. Signed-off-by: Sairaj Kodilkar Reviewed-by: Vasant Hegde Reviewed-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 21 +++++++++++++++++++-- hw/i386/amd_iommu.h | 4 +++- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index f5aa9c763d02..4a86e62a3b92 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1523,6 +1523,8 @@ static void amdvi_handle_control_write(AMDVIState *s) s->cmdbuf_enabled =3D s->enabled && !!(control & AMDVI_MMIO_CONTROL_CMDBUFLEN); s->ga_enabled =3D !!(control & AMDVI_MMIO_CONTROL_GAEN); + s->xten =3D !!(control & AMDVI_MMIO_CONTROL_XTEN) && s->xtsup && + s->ga_enabled; =20 /* update the flags depending on the control register */ if (s->cmdbuf_enabled) { @@ -1996,7 +1998,7 @@ static int amdvi_int_remap_ga(AMDVIState *iommu, irq->vector =3D irte.hi.fields.vector; irq->dest_mode =3D irte.lo.fields_remap.dm; irq->redir_hint =3D irte.lo.fields_remap.rq_eoi; - if (iommu->xtsup) { + if (iommu->xten) { irq->dest =3D irte.lo.fields_remap.destination | (irte.hi.fields.destination_hi << 24); } else { @@ -2379,6 +2381,7 @@ static void amdvi_init(AMDVIState *s) s->mmio_enabled =3D false; s->enabled =3D false; s->cmdbuf_enabled =3D false; + s->xten =3D false; =20 /* reset MMIO */ memset(s->mmior, 0, AMDVI_MMIO_SIZE); @@ -2443,6 +2446,16 @@ static void amdvi_sysbus_reset(DeviceState *dev) amdvi_reset_address_translation_all(s); } =20 +static const VMStateDescription vmstate_xt =3D { + .name =3D "amd-iommu-xt", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_BOOL(xten, AMDVIState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_amdvi_sysbus_migratable =3D { .name =3D "amd-iommu", .version_id =3D 1, @@ -2487,7 +2500,11 @@ static const VMStateDescription vmstate_amdvi_sysbus= _migratable =3D { VMSTATE_UINT8_ARRAY(romask, AMDVIState, AMDVI_MMIO_SIZE), VMSTATE_UINT8_ARRAY(w1cmask, AMDVIState, AMDVI_MMIO_SIZE), VMSTATE_END_OF_LIST() - } + }, + .subsections =3D (const VMStateDescription *const []) { + &vmstate_xt, + NULL + } }; =20 static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index ca4ff9fffee3..d39019b216af 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -102,6 +102,7 @@ #define AMDVI_MMIO_CONTROL_COMWAITINTEN (1ULL << 4) #define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12) #define AMDVI_MMIO_CONTROL_GAEN (1ULL << 17) +#define AMDVI_MMIO_CONTROL_XTEN (1ULL << 50) =20 /* MMIO status register bits */ #define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) @@ -414,7 +415,8 @@ struct AMDVIState { =20 /* Interrupt remapping */ bool ga_enabled; - bool xtsup; + bool xtsup; /* xtsup=3Don command line */ + bool xten; /* guest controlled, x2apic mode enabled */ =20 /* DMA address translation */ bool dma_remap; --=20 2.34.1 From nobody Fri Apr 10 17:41:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8205 Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=Sairaj.ArunKodilkar@amd.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1772452401724158500 When MMIO 0x18[IntCapXTEn]=3D1, interrupts originating from the IOMMU itsel= f are sent based on the programming in XT IOMMU Interrupt Control Registers in MM= IO 0x170-0x180 instead of the programming in the IOMMU's MSI capability regist= ers. The guest programs these registers with appropriate vector and destination ID instead of writing to PCI MSI capability. Current AMD vIOMMU is capable of generating interrupts only through PCI MSI capability and does not care about xt mode. Because of this AMD vIOMMU cannot generate event log interrupts when the guest has enabled xt mode. Introduce a new flag "intcapxten" which is set when guest writes control register [IntCapXTEn] (bit 51) and use vector and destination field in the XT MMIO register (0x170) to support XT mode. Signed-off-by: Sairaj Kodilkar Reviewed-by: Vasant Hegde Reviewed-by: Alejandro Jimenez --- hw/i386/amd_iommu.c | 47 ++++++++++++++++++++++++++++++++++++++------ hw/i386/amd_iommu.h | 17 ++++++++++++++++ hw/i386/trace-events | 1 + 3 files changed, 59 insertions(+), 6 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 4a86e62a3b92..bd24fdee7cfe 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -192,18 +192,38 @@ static void amdvi_assign_andq(AMDVIState *s, hwaddr a= ddr, uint64_t val) amdvi_writeq_raw(s, addr, amdvi_readq(s, addr) & val); } =20 +static void amdvi_build_xt_msi_msg(AMDVIState *s, MSIMessage *msg) +{ + union mmio_xt_intr xt_reg; + struct X86IOMMUIrq irq; + + xt_reg.val =3D amdvi_readq(s, AMDVI_MMIO_XT_GEN_INTR); + + irq.vector =3D xt_reg.vector; + irq.delivery_mode =3D xt_reg.delivery_mode; + irq.dest_mode =3D xt_reg.destination_mode; + irq.dest =3D (xt_reg.destination_hi << 24) | xt_reg.destination_lo; + irq.trigger_mode =3D 0; + irq.redir_hint =3D 0; + + x86_iommu_irq_to_msi_message(&irq, msg); +} + static void amdvi_generate_msi_interrupt(AMDVIState *s) { MSIMessage msg =3D {}; - MemTxAttrs attrs =3D { - .requester_id =3D pci_requester_id(&s->pci->dev) - }; =20 - if (msi_enabled(&s->pci->dev)) { + if (s->intcapxten) { + trace_amdvi_generate_msi_interrupt("XT GEN"); + amdvi_build_xt_msi_msg(s, &msg); + } else if (msi_enabled(&s->pci->dev)) { + trace_amdvi_generate_msi_interrupt("MSI"); msg =3D msi_get_message(&s->pci->dev, 0); - address_space_stl_le(&address_space_memory, msg.address, msg.data, - attrs, NULL); + } else { + trace_amdvi_generate_msi_interrupt("NO MSI"); + return; } + apic_get_class(NULL)->send_msi(&msg); } =20 static uint32_t get_next_eventlog_entry(AMDVIState *s) @@ -1482,6 +1502,7 @@ const char *amdvi_mmio_get_name(hwaddr addr) MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_BASE); MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_HEAD); MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_TAIL); + MMIO_REG_TO_STRING(AMDVI_MMIO_XT_GEN_INTR); #undef MMIO_REG_TO_STRING default: return "UNHANDLED"; @@ -1525,6 +1546,15 @@ static void amdvi_handle_control_write(AMDVIState *s) s->ga_enabled =3D !!(control & AMDVI_MMIO_CONTROL_GAEN); s->xten =3D !!(control & AMDVI_MMIO_CONTROL_XTEN) && s->xtsup && s->ga_enabled; + /* + * IntCapXTEn controls whether IOMMU-originated interrupts are sent ba= sed + * on the information in XT IOMMU Interrupt Control Registers rather t= han + * the IOMMU=E2=80=99s MSI capability registers. Therefore it requires= IOMMU + * x2APIC support capabilities (i.e. XTSup=3D1), but it is independent= of + * whether a driver chooses to enable x2APIC mode for interrupt remapp= ing + * (i.e. XTEn=3D1). + */ + s->intcapxten =3D !!(control & AMDVI_MMIO_CONTROL_INTCAPXTEN) && s->xt= sup; =20 /* update the flags depending on the control register */ if (s->cmdbuf_enabled) { @@ -1732,6 +1762,9 @@ static void amdvi_mmio_write(void *opaque, hwaddr add= r, uint64_t val, case AMDVI_MMIO_STATUS: amdvi_mmio_reg_write(s, size, val, addr); break; + case AMDVI_MMIO_XT_GEN_INTR: + amdvi_mmio_reg_write(s, size, val, addr); + break; } } =20 @@ -2382,6 +2415,7 @@ static void amdvi_init(AMDVIState *s) s->enabled =3D false; s->cmdbuf_enabled =3D false; s->xten =3D false; + s->intcapxten =3D false; =20 /* reset MMIO */ memset(s->mmior, 0, AMDVI_MMIO_SIZE); @@ -2452,6 +2486,7 @@ static const VMStateDescription vmstate_xt =3D { .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { VMSTATE_BOOL(xten, AMDVIState), + VMSTATE_BOOL(intcapxten, AMDVIState), VMSTATE_END_OF_LIST() } }; diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index d39019b216af..72139bb0c70b 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -53,6 +53,7 @@ #define AMDVI_MMIO_EXCL_BASE 0x0020 #define AMDVI_MMIO_EXCL_LIMIT 0x0028 #define AMDVI_MMIO_EXT_FEATURES 0x0030 +#define AMDVI_MMIO_XT_GEN_INTR 0x0170 #define AMDVI_MMIO_COMMAND_HEAD 0x2000 #define AMDVI_MMIO_COMMAND_TAIL 0x2008 #define AMDVI_MMIO_EVENT_HEAD 0x2010 @@ -103,6 +104,7 @@ #define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12) #define AMDVI_MMIO_CONTROL_GAEN (1ULL << 17) #define AMDVI_MMIO_CONTROL_XTEN (1ULL << 50) +#define AMDVI_MMIO_CONTROL_INTCAPXTEN (1ULL << 51) =20 /* MMIO status register bits */ #define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) @@ -339,6 +341,20 @@ struct irte_ga { union irte_ga_hi hi; }; =20 +union mmio_xt_intr { + uint64_t val; + struct { + uint64_t rsvd_1:2, + destination_mode:1, + rsvd_2:5, + destination_lo:24, + vector:8, + delivery_mode:1, + rsvd_3:15, + destination_hi:8; + }; +}; + #define TYPE_AMD_IOMMU_DEVICE "amd-iommu" OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE) =20 @@ -417,6 +433,7 @@ struct AMDVIState { bool ga_enabled; bool xtsup; /* xtsup=3Don command line */ bool xten; /* guest controlled, x2apic mode enabled */ + bool intcapxten; /* guest controlled, IOMMU x2apic interrupts enabled = */ =20 /* DMA address translation */ bool dma_remap; diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 5fa5e93b68dc..a1dfade20f18 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -118,6 +118,7 @@ amdvi_ir_intctl(uint8_t val) "int_ctl 0x%"PRIx8 amdvi_ir_target_abort(const char *str) "%s" amdvi_ir_delivery_mode(const char *str) "%s" amdvi_ir_irte_ga_val(uint64_t hi, uint64_t lo) "hi 0x%"PRIx64" lo 0x%"PRIx= 64 +amdvi_generate_msi_interrupt(const char *str) "Mode: %s" =20 # vmport.c vmport_register(unsigned char command, void *func, void *opaque) "command:= 0x%02x func: %p opaque: %p" --=20 2.34.1