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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1772447833; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iyKs2XjxalZIh1rEgOJiZBWSDMGmfe3TX4GJ7G8ZqkQ=; b=MlDhAvAdy6achPMpb+W4nJmmeUZJjXoteofvh7zeLI7kV0HL61o+ZK4TskhLwaD4FIhYWm KnnaZYVNct5/s90skRkucdIMP3u/Lbi2dcxY9BZSJr7g166oIVMEGt026xfGTAnsU9CfaW JAqUfmLp2SkdoyXx/0/JJSmUl/Wdl8o= X-MC-Unique: L--x-rIZOJ-8HCkq0YeSpw-1 X-Mimecast-MFC-AGG-ID: L--x-rIZOJ-8HCkq0YeSpw_1772447828 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, sebott@redhat.com, peterx@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v7 6/7] target/arm/helper: Define cpreg migration tolerance for DGBDTR_EL0 Date: Mon, 2 Mar 2026 11:35:28 +0100 Message-ID: <20260302103640.1362564-7-eric.auger@redhat.com> In-Reply-To: <20260302103640.1362564-1-eric.auger@redhat.com> References: <20260302103640.1362564-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We want to remove AArch32 DBGDTRTX which was erroneously exposed. This was attempted by 655659a74a36b ("target/arm: Correct encoding of Debug Communications Channel registers") but it was discovered that the removal of this debug register broke forward migration on TCG. Now we have the cpreg migration tolerance infrastructure, we can declare one for the DBGDTRTX. This allow to revert the reinstate patch. Signed-off-by: Eric Auger --- target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7389f2988c4..3cba62705dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6426,9 +6426,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fgt =3D FGT_CLIDR_EL1, .resetvalue =3D GET_IDREG(isar, CLIDR) }; + uint64_t dbgtr_el0_kvmidx =3D + cpreg_to_kvm_id(ENCODE_CP_REG(14, 0, 1, 0, 5, 3, 0)); + define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); define_debug_regs(cpu); + arm_register_cpreg_mig_tolerance(cpu, dbgtr_el0_kvmidx, + 0, 0, ToleranceNotOnBothEnds); } else { define_arm_cp_regs(cpu, not_v7_cp_reginfo); } --=20 2.53.0