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Mon, 02 Mar 2026 00:48:59 -0800 (PST) X-Received: by 2002:a05:600c:46c4:b0:483:7783:5373 with SMTP id 5b1f17b1804b1-483c9c0f20dmr196013365e9.23.1772441339407; Mon, 02 Mar 2026 00:48:59 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Ani Sinha , Jon Kohler , Pawan Gupta Subject: [PULL 094/102] target/i386: introduce ClearwaterForest-v3 to expose ITS_NO Date: Mon, 2 Mar 2026 09:47:40 +0100 Message-ID: <20260302084749.474955-28-pbonzini@redhat.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260302084338.473368-1-pbonzini@redhat.com> References: <20260302084338.473368-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.012, RCVD_IN_VALIDITY_RPBL_BLOCKED=1.188, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1772441841161158500 Content-Type: text/plain; charset="utf-8" From: Jon Kohler Expose ITS_NO by default, as users using Clearwater Forest and higher CPU models would not be able to live migrate to lower CPU hosts due to missing features. In that case, they would not be vulnerable to ITS. its-no was originally added on [1], but needs to be exposed on the individual CPU models for the guests to see by default. Note: Version 1 already exposes ARCH_CAP_BHI_NO, which would already mark the CPU as invulnerable to ITS (at least in Linux); however, expose ITS_NO for completeness. [1] 74978391b2da ("target/i386: Make ITS_NO available to guests") Cc: Pawan Gupta Signed-off-by: Jon Kohler Link: https://lore.kernel.org/r/20251106174626.49930-6-jon@nutanix.com Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2a869f5b739..01b64940b17 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5964,6 +5964,14 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { { /* end of list */ }, } }, + { + .version =3D 3, + .note =3D "with cet-ss, cet-ibt, ITS_NO", + .props =3D (PropValue[]) { + { "its-no", "on" }, + { /* end of list */ }, + } + }, { /* end of list */ }, }, }, --=20 2.53.0