From nobody Sun Apr 12 00:57:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1772452497; cv=none; d=zohomail.com; s=zohoarc; b=XUHkh9F2UfL03+y43zNc1WBIV/QCzYuWly4TK3tqGxoXaBHUVdhLo3gBP7JpRWumh2Po4GV9uiRA7GYIQBArRB0p24RiRd4KugjlY0Mk2/6Pp9WoPCofoOyIrxjduSoZ2aQ6QMZYaCZGQh+Z4TmTU6/vF2viQSalaVuHJZU9Xk4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772452497; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=OujbK1RP5GohieE6ZQBEX97A1GJy1akPuD5ViAOCRb4=; b=CEbwE98JY3UPkQAnBt9Pp3DoUuWXsyVyHTay5CwhrUEXrq4Mo4KyLY/BHYwsmKftz4bFBmDlqfcDnyXEwA0KqcqEuu9kOsyo7VBEZUg4Gk43GIVKJRiam5Mbc3xHGdzUDXUbAg0TlHAe48Rp9pnULI8pwM3mOzhcB0V5tIDDhnY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772452497625245.8138368428214; Mon, 2 Mar 2026 03:54:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vx1qk-00017z-3v; Mon, 02 Mar 2026 06:54:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vx1qU-0000xE-Oj for qemu-devel@nongnu.org; Mon, 02 Mar 2026 06:53:54 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vx1qS-0007j4-1s for qemu-devel@nongnu.org; Mon, 02 Mar 2026 06:53:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=OujbK1RP5GohieE6ZQBEX97A1GJy1akPuD5ViAOCRb4=; b=jRea4hCqnrQIZor xDkjy/KYlpq6H3MkjYjy1jQ4UbNzWJZCIIYnun+jzMWgBWLW0WPTIrfIJRu/1SuwKZ212op9Z3gkI l7SjVLXZKurLZTRwZeADtNBUdfXon8SFNGF48ysrwxcdo/R4KvScYVu+Q9dcIoUq9RAEzV/haNDMq RA=; Date: Mon, 02 Mar 2026 12:56:44 +0100 Subject: [PATCH v4 2/4] hppa: Introduce HPPACPUDef MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260302-hppa-c3600-v4-2-447a800da8cc@rev.ng> References: <20260302-hppa-c3600-v4-0-447a800da8cc@rev.ng> In-Reply-To: <20260302-hppa-c3600-v4-0-447a800da8cc@rev.ng> To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller , Anton Johansson X-Developer-Signature: v=1; a=ed25519-sha256; t=1772452649; l=4452; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=zO4MBnIxiTPAVkkQNmorkziyIeF6F+tBE7Q7Qb9zrzc=; b=tUK/5UVBpGEASold/3p3fMRi0p/9VDYdH4Ok1zqkO2sZQTERjdYTv4KQq6Afm3IhQ4TgWef1k SkE5CnMRrKzAduirCvhYF4R0t9i2cOPbhqkbpruH7RsCFAp+oatSn9R X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.012, RCVD_IN_VALIDITY_RPBL_BLOCKED=1.188, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772452497956158500 In preparation for handling different physical address spaces sizes (32, 40, 44 bits) a CPU model configuration struct is added to HPPACPUClass. Two fields are added describing the size of the physical address space, and whether or not the CPU uses the PA-RISC 2.0 architecture. The latter was previously a field in CPUHPPAState. phys_addr_bits is currently set but unused, and will be used in the following commit. Likewise, PA-8700 is moved to use 44 bit physical addresses in a followup commit to not bisection. Signed-off-by: Anton Johansson Reviewed-by: Helge Deller --- target/hppa/cpu.h | 24 ++++++++++++++++++++---- target/hppa/cpu.c | 31 +++++++++++++++++++++---------- 2 files changed, 41 insertions(+), 14 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 092e647ccf..43b4882fb4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -270,8 +270,6 @@ typedef struct CPUArchState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - bool is_pa20; - target_ulong kernel_entry; /* Linux kernel was loaded here */ target_ulong cmdline_or_bootorder; target_ulong initrd_base, initrd_end; @@ -290,6 +288,18 @@ struct ArchCPU { QEMUTimer *alarm_timer; }; =20 +/** + * HPPACPUDef: + * @phys_addr_bits: Number of bits in the physical address space. + * @is_pa20: Whether the CPU model follows the PA-RISC 2.0 or 1.1 spec. + * + * Configuration options for a HPPA CPU model. + */ +typedef struct HPPACPUDef { + uint8_t phys_addr_bits; + bool is_pa20; +} HPPACPUDef; + /** * HPPACPUClass: * @parent_realize: The parent class' realize handler. @@ -302,11 +312,17 @@ struct HPPACPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; + const HPPACPUDef *def; }; =20 -static inline bool hppa_is_pa20(const CPUHPPAState *env) +static inline const HPPACPUDef *hppa_def(CPUHPPAState *env) +{ + return HPPA_CPU_GET_CLASS(env_cpu(env))->def; +} + +static inline bool hppa_is_pa20(CPUHPPAState *env) { - return env->is_pa20; + return hppa_def(env)->is_pa20; } =20 static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 910a919923..cc755da8be 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -203,15 +203,6 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error= **errp) tcg_cflags_set(cs, CF_PCREL); } =20 -static void hppa_cpu_initfn(Object *obj) -{ - CPUHPPAState *env =3D cpu_env(CPU(obj)); - - env->is_pa20 =3D !!object_dynamic_cast(obj, TYPE_HPPA_CPU_PA_8500) || - !!object_dynamic_cast(obj, TYPE_HPPA_CPU_PA_8700); - -} - static void hppa_cpu_reset_hold(Object *obj, ResetType type) { HPPACPUClass *scc =3D HPPA_CPU_GET_CLASS(obj); @@ -286,6 +277,14 @@ static const TCGCPUOps hppa_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 +static void hppa_cpu_class_base_init(ObjectClass *oc, const void *data) +{ + HPPACPUClass *acc =3D HPPA_CPU_CLASS(oc); + /* Make sure all CPU models define a HPPACPUDef */ + g_assert(!object_class_is_abstract(oc) && data !=3D NULL); + acc->def =3D data; +} + static void hppa_cpu_class_init(ObjectClass *oc, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -320,22 +319,34 @@ static const TypeInfo hppa_cpu_type_infos[] =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(HPPACPU), .instance_align =3D __alignof(HPPACPU), - .instance_init =3D hppa_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(HPPACPUClass), .class_init =3D hppa_cpu_class_init, + .class_base_init =3D hppa_cpu_class_base_init, }, { .name =3D TYPE_HPPA_CPU_PA_7300LC, .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 32, + .is_pa20 =3D false, + }, }, { .name =3D TYPE_HPPA_CPU_PA_8500, .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 40, + .is_pa20 =3D true, + }, }, { .name =3D TYPE_HPPA_CPU_PA_8700, .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 40, + .is_pa20 =3D true, + }, }, }; =20 --=20 2.52.0