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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.86.212; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.966, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.722, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1772315327001158500 Content-Type: text/plain; charset="utf-8" Now that we expose AccessFrequencyRegs, expose HV_X64_MSR_APIC_FREQUENCY as= well for the case when the Hyper-V LAPIC is not used. If the Hyper-V LAPIC is used, this will be handled by the hypervisor instea= d of the VMM, hence gating it on !whpx_irqchip_in_kernel(). Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index da2ba36060..69a3c42ba0 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -45,6 +45,8 @@ #include =20 #define HYPERV_APIC_BUS_FREQUENCY (200000000ULL) +/* for kernel-irqchip=3Doff */ +#define HV_X64_MSR_APIC_FREQUENCY 0x40000023 =20 static const WHV_REGISTER_NAME whpx_register_names[] =3D { =20 @@ -1787,6 +1789,7 @@ int whpx_vcpu_run(CPUState *cpu) WHV_REGISTER_VALUE reg_values[3] =3D {0}; WHV_REGISTER_NAME reg_names[3]; UINT32 reg_count; + bool is_known_msr =3D 0;=20 =20 reg_names[0] =3D WHvX64RegisterRip; reg_names[1] =3D WHvX64RegisterRax; @@ -1796,6 +1799,12 @@ int whpx_vcpu_run(CPUState *cpu) vcpu->exit_ctx.VpContext.Rip + vcpu->exit_ctx.VpContext.InstructionLength; =20 + if (vcpu->exit_ctx.MsrAccess.MsrNumber =3D=3D HV_X64_MSR_APIC_= FREQUENCY + && !vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite + && !whpx_irqchip_in_kernel()) { + is_known_msr =3D 1; + reg_values[1].Reg32 =3D (uint32_t)X86_CPU(cpu)->env.apic_b= us_freq; + } /* * For all unsupported MSR access we: * ignore writes @@ -1804,8 +1813,10 @@ int whpx_vcpu_run(CPUState *cpu) reg_count =3D vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite ? 1 : 3; =20 - warn_report("WHPX: Unsupported MSR access (0x%x), IsWrite=3D%i= ",=20 + if (!is_known_msr) { + warn_report("WHPX: Unsupported MSR access (0x%x), IsWrite= =3D%i",=20 vcpu->exit_ctx.MsrAccess.MsrNumber, vcpu->exit_ctx.MsrAcce= ss.AccessInfo.IsWrite); + } =20 hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters( whpx->partition, @@ -1973,6 +1984,10 @@ int whpx_init_vcpu(CPUState *cpu) } } =20 + /* When not using the Hyper-V APIC, the frequency is 1 GHz */ + if (!whpx_irqchip_in_kernel()) { + env->apic_bus_freq =3D 1000000000; + } =20 vcpu->interruptable =3D true; cpu->vcpu_dirty =3D true; @@ -2186,7 +2201,6 @@ int whpx_accel_init(AccelState *as, MachineState *ms) synthetic_features.Bank0.Hv1 =3D 1; synthetic_features.Bank0.AccessPartitionReferenceCounter =3D 1; synthetic_features.Bank0.AccessPartitionReferenceTsc =3D 1; - /* if kernel-irqchip=3Doff, HV_X64_MSR_APIC_FREQUENCY =3D 0. */ synthetic_features.Bank0.AccessFrequencyRegs =3D 1; synthetic_features.Bank0.AccessVpIndex =3D 1; synthetic_features.Bank0.AccessHypercallRegs =3D 1; --=20 2.50.1 (Apple Git-155)