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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.86.232; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.966, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.722, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1772315318177158500 Content-Type: text/plain; charset="utf-8" At the point in time in which we setup the partition, the vCPUs aren't available yet. So enable them by default for now like what the MSHV backend does. AccessFrequencyRegs is shared for both the LAPIC frequency reporting and th= e TSC frequency. To still benefit from the fixed TSC frequency reporting when kernel-irqchip= =3Doff, still enable AccessFrequencyRegs anyway. Signed-off-by: Mohamed Mediouni --- target/i386/whpx/whpx-all.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index ccc52d1f96..e7e0a50da6 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -2152,6 +2152,40 @@ int whpx_accel_init(AccelState *as, MachineState *ms) goto error; } =20 + /* Enable synthetic processor features */ + WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS synthetic_features; + memset(&synthetic_features, 0, sizeof(WHV_SYNTHETIC_PROCESSOR_FEATURES= _BANKS)); + synthetic_features.BanksCount =3D 1; + + synthetic_features.Bank0.HypervisorPresent =3D 1; + synthetic_features.Bank0.Hv1 =3D 1; + synthetic_features.Bank0.AccessPartitionReferenceCounter =3D 1; + synthetic_features.Bank0.AccessPartitionReferenceTsc =3D 1; + /* if kernel-irqchip=3Doff, HV_X64_MSR_APIC_FREQUENCY =3D 0. */ + synthetic_features.Bank0.AccessFrequencyRegs =3D 1; + synthetic_features.Bank0.AccessVpIndex =3D 1; + synthetic_features.Bank0.AccessHypercallRegs =3D 1; + synthetic_features.Bank0.TbFlushHypercalls =3D 1; + + if (whpx_irqchip_in_kernel()) { + synthetic_features.Bank0.AccessSynicRegs =3D 1; + synthetic_features.Bank0.AccessSyntheticTimerRegs =3D 1; + synthetic_features.Bank0.AccessIntrCtrlRegs =3D 1; + synthetic_features.Bank0.SyntheticClusterIpi =3D 1; + synthetic_features.Bank0.DirectSyntheticTimers =3D 1; + } + + hr =3D whp_dispatch.WHvSetPartitionProperty( + whpx->partition, + WHvPartitionPropertyCodeSyntheticProcessorFeaturesBanks, + &synthetic_features, + sizeof(WHV_SYNTHETIC_PROCESSOR_FEATURES_BANKS)); + if (FAILED(hr)) { + error_report("WHPX: Failed to set synthetic features, hr=3D%08lx",= hr); + ret =3D -EINVAL; + goto error; + } + /* Register for MSR and CPUID exits */ memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY)); prop.ExtendedVmExits.X64MsrExit =3D 1; --=20 2.50.1 (Apple Git-155)