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Fri, 27 Feb 2026 00:56:51 -0800 (PST) From: Manos Pitsidianakis Date: Fri, 27 Feb 2026 10:56:46 +0200 Subject: [PATCH v5 1/2] hvf/arm: handle FEAT_SME2 migration MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260227-sme2-hvf-v5-1-1c60a92910c8@linaro.org> References: <20260227-sme2-hvf-v5-0-1c60a92910c8@linaro.org> In-Reply-To: <20260227-sme2-hvf-v5-0-1c60a92910c8@linaro.org> To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Phil_Mathieu-Daud=C3=A9?= , Alexander Graf , Mads Ynddal , Peter Maydell , qemu-arm@nongnu.org, Mohamed Mediouni , Manos Pitsidianakis X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=23343; i=manos.pitsidianakis@linaro.org; h=from:subject:message-id; bh=V7uflc0vil9/pJsxLunFwh0B38DLYq9u2yo0IwW6PrE=; b=LS0tLS1CRUdJTiBQR1AgTUVTU0FHRS0tLS0tCgpvd0VCYlFLUy9aQU5Bd0FLQVhjcHgzQi9mZ 25RQWNzbVlnQnBvVnhRUmxuZC9hOUx5R0Vwc3ptK3JYTFBIOUZiClFzVS9COUVtZ0ZMZ3pQbGpi U1NKQWpNRUFBRUtBQjBXSVFUTVhCdE9SS0JXODRkd0hSQjNLY2R3ZjM0SjBBVUMKYWFGY1VBQUt DUkIzS2Nkd2YzNEowUFhFRC80cUZWQmFnOG9pMDlZS0dGUGtCSlRhWHhSditYUy90V1lweTdjNA pBSFl5N3djaFV1aWNyUy9ZelpOYVdNbWg1dFo5dm5YeDVRc0N0WHdXc3paQzFiVlZkd3gzMnBUb kVjb0ZXY1NmCnhiRC9KbFd1OVVpRFVVYktPREpaZ080VEdsQk11MytWKzZMRDgzVWQwWTVDZ1Z5 THV4ZjkrWUlaRzU2YjgrSXAKVjJYOFBUSXNpeHBmZ2xqRXAzby9ZUWRMR3JDMTJsb2orNE9FSHg 0dzFhQkFmQlV0aEhkK2Jpd0hyN2lrajNUSQppaVptVEJlK1E5YTVFVmxvT2ViT2RYYjVvOXVuUj VXMDhiM2ZTUUYydFlBMDNHOW1OcHRjMThnd2dxd2FjMTlUCit0WVNzTDhXUWwrYTA1WkdpbXNFN EpsS25QS0NESXpERFJnTWVDbHdveUtFb0xteXNqZVAwY3l5T3FXSENpQ1oKVUU1MDRCeFZtSEh6 ZjdadFRHVC9nS0JtejRzN2NPWWtzakNEZkNhTFdiRi9DRWVYQjNhZ3ZtdmNoSENsODArNQp5UWZ oNFVuM2FBZndRZktGN0l4WmFXbmVGMC9EME1UU2E3d1JmbFhUbmlZck1SRFExK2JwTjJ4TU5jWX VEZnhXCkJudmkrV3N2TTB0UUNOV1F1QUErZWdTcDBKVmViUW1pMnV0VFh2TkxyUHNQOWJsTTJmS 0E3RWdjdUtTVGJFd3oKUlBkTTM4ZzNpdzhJbHYxVkdaR25PVkxRR29sQlZHTTNPSkYyUWtING8w VUJpVWpjU3M4T21pa3JZUHRhWTZQaQp3VFBEdE9DQ21nRk5aVGpSWnFISzUwRUJDRjBRN1g4U3Q 1emJkQkhqeG9iTHh5USt2anZDU3l6OWtWVlJ1WTVtCmcySVVDUT09Cj1vVjE1Ci0tLS0tRU5EIF BHUCBNRVNTQUdFLS0tLS0K X-Developer-Key: i=manos.pitsidianakis@linaro.org; a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1772182680616158500 SME2 support adds the following state for HVF guests: - Vector registers Z0, ... , Z31 (introduced by FEAT_SVE but HVF does not support it) - Predicate registers P0, .., P15 (also FEAT_SVE) - ZA register - ZT0 register - PSTATE.{SM,ZA} bits (SVCR pseudo-register) - SMPRI_EL1 which handles the PE's priority in the SMCU - TPIDR2_EL0 the thread local ID register for SME Signed-off-by: Manos Pitsidianakis --- target/arm/hvf/hvf.c | 294 +++++++++++++++++++++++++++++++++++++= +++- target/arm/hvf/hvf_sme_stubs.h | 158 ++++++++++++++++++++++ target/arm/hvf/sysreg.c.inc | 8 ++ target/arm/hvf_arm.h | 41 ++++++ target/arm/machine.c | 2 +- 5 files changed, 500 insertions(+), 3 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index d79469ca27f794139b8073e25fc16d470b1942d5..3d194680cc87e78835098df2e0e= 7987ed544c553 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -395,6 +395,60 @@ static const struct hvf_reg_match hvf_fpreg_match[] = =3D { { HV_SIMD_FP_REG_Q31, offsetof(CPUARMState, vfp.zregs[31]) }, }; =20 +static const struct hvf_reg_match hvf_sme2_zreg_match[] =3D { + { HV_SME_Z_REG_0, offsetof(CPUARMState, vfp.zregs[0]) }, + { HV_SME_Z_REG_1, offsetof(CPUARMState, vfp.zregs[1]) }, + { HV_SME_Z_REG_2, offsetof(CPUARMState, vfp.zregs[2]) }, + { HV_SME_Z_REG_3, offsetof(CPUARMState, vfp.zregs[3]) }, + { HV_SME_Z_REG_4, offsetof(CPUARMState, vfp.zregs[4]) }, + { HV_SME_Z_REG_5, offsetof(CPUARMState, vfp.zregs[5]) }, + { HV_SME_Z_REG_6, offsetof(CPUARMState, vfp.zregs[6]) }, + { HV_SME_Z_REG_7, offsetof(CPUARMState, vfp.zregs[7]) }, + { HV_SME_Z_REG_8, offsetof(CPUARMState, vfp.zregs[8]) }, + { HV_SME_Z_REG_9, offsetof(CPUARMState, vfp.zregs[9]) }, + { HV_SME_Z_REG_10, offsetof(CPUARMState, vfp.zregs[10]) }, + { HV_SME_Z_REG_11, offsetof(CPUARMState, vfp.zregs[11]) }, + { HV_SME_Z_REG_12, offsetof(CPUARMState, vfp.zregs[12]) }, + { HV_SME_Z_REG_13, offsetof(CPUARMState, vfp.zregs[13]) }, + { HV_SME_Z_REG_14, offsetof(CPUARMState, vfp.zregs[14]) }, + { HV_SME_Z_REG_15, offsetof(CPUARMState, vfp.zregs[15]) }, + { HV_SME_Z_REG_16, offsetof(CPUARMState, vfp.zregs[16]) }, + { HV_SME_Z_REG_17, offsetof(CPUARMState, vfp.zregs[17]) }, + { HV_SME_Z_REG_18, offsetof(CPUARMState, vfp.zregs[18]) }, + { HV_SME_Z_REG_19, offsetof(CPUARMState, vfp.zregs[19]) }, + { HV_SME_Z_REG_20, offsetof(CPUARMState, vfp.zregs[20]) }, + { HV_SME_Z_REG_21, offsetof(CPUARMState, vfp.zregs[21]) }, + { HV_SME_Z_REG_22, offsetof(CPUARMState, vfp.zregs[22]) }, + { HV_SME_Z_REG_23, offsetof(CPUARMState, vfp.zregs[23]) }, + { HV_SME_Z_REG_24, offsetof(CPUARMState, vfp.zregs[24]) }, + { HV_SME_Z_REG_25, offsetof(CPUARMState, vfp.zregs[25]) }, + { HV_SME_Z_REG_26, offsetof(CPUARMState, vfp.zregs[26]) }, + { HV_SME_Z_REG_27, offsetof(CPUARMState, vfp.zregs[27]) }, + { HV_SME_Z_REG_28, offsetof(CPUARMState, vfp.zregs[28]) }, + { HV_SME_Z_REG_29, offsetof(CPUARMState, vfp.zregs[29]) }, + { HV_SME_Z_REG_30, offsetof(CPUARMState, vfp.zregs[30]) }, + { HV_SME_Z_REG_31, offsetof(CPUARMState, vfp.zregs[31]) }, +}; + +static const struct hvf_reg_match hvf_sme2_preg_match[] =3D { + { HV_SME_P_REG_0, offsetof(CPUARMState, vfp.pregs[0]) }, + { HV_SME_P_REG_1, offsetof(CPUARMState, vfp.pregs[1]) }, + { HV_SME_P_REG_2, offsetof(CPUARMState, vfp.pregs[2]) }, + { HV_SME_P_REG_3, offsetof(CPUARMState, vfp.pregs[3]) }, + { HV_SME_P_REG_4, offsetof(CPUARMState, vfp.pregs[4]) }, + { HV_SME_P_REG_5, offsetof(CPUARMState, vfp.pregs[5]) }, + { HV_SME_P_REG_6, offsetof(CPUARMState, vfp.pregs[6]) }, + { HV_SME_P_REG_7, offsetof(CPUARMState, vfp.pregs[7]) }, + { HV_SME_P_REG_8, offsetof(CPUARMState, vfp.pregs[8]) }, + { HV_SME_P_REG_9, offsetof(CPUARMState, vfp.pregs[9]) }, + { HV_SME_P_REG_10, offsetof(CPUARMState, vfp.pregs[10]) }, + { HV_SME_P_REG_11, offsetof(CPUARMState, vfp.pregs[11]) }, + { HV_SME_P_REG_12, offsetof(CPUARMState, vfp.pregs[12]) }, + { HV_SME_P_REG_13, offsetof(CPUARMState, vfp.pregs[13]) }, + { HV_SME_P_REG_14, offsetof(CPUARMState, vfp.pregs[14]) }, + { HV_SME_P_REG_15, offsetof(CPUARMState, vfp.pregs[15]) }, +}; + /* * QEMU uses KVM system register ids in the migration format. * Conveniently, HVF uses the same encoding of the op* and cr* parameters @@ -406,22 +460,201 @@ static const struct hvf_reg_match hvf_fpreg_match[] = =3D { #define HVF_TO_KVMID(HVF) \ (CP_REG_ARM64 | CP_REG_SIZE_U64 | CP_REG_ARM64_SYSREG | (HVF)) =20 -/* Verify this at compile-time. */ +/* + * Verify this at compile-time. + * + * SME2 registers are guarded by a runtime availability attribute instead = of a + * compile-time def, so verify those at runtime in hvf_arch_init_vcpu() be= low. + */ =20 #define DEF_SYSREG(HVF_ID, ...) \ QEMU_BUILD_BUG_ON(HVF_ID !=3D KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARG= S__))); +#define DEF_SYSREG_15_02(...) =20 #include "sysreg.c.inc" =20 #undef DEF_SYSREG +#undef DEF_SYSREG_15_02 =20 #define DEF_SYSREG(HVF_ID, op0, op1, crn, crm, op2) HVF_ID, +#define DEF_SYSREG_15_02(...) =20 static const hv_sys_reg_t hvf_sreg_list[] =3D { #include "sysreg.c.inc" }; =20 #undef DEF_SYSREG +#undef DEF_SYSREG_15_02 + +#define DEF_SYSREG(...) +#define DEF_SYSREG_15_02(HVF_ID, op0, op1, crn, crm, op2) HVF_ID, + +API_AVAILABLE(macos(15.2)) +static const hv_sys_reg_t hvf_sreg_list_sme2[] =3D { +#include "sysreg.c.inc" +}; + +#undef DEF_SYSREG +#undef DEF_SYSREG_15_02 + +/* + * For FEAT_SME2 migration, we need to store PSTATE.{SM,ZA} bits which are + * accessible with the SVCR pseudo-register. However, in the HVF API this = is + * not exposed as a system-register (i.e. HVF_SYS_REG_SVCR) but a custom + * struct, hv_vcpu_sme_state_t. So we need to define our own KVMID in orde= r to + * store it in cpreg_values and make it migrateable. + */ +#define SVCR KVMID_AA64_SYS_REG64(3, 3, 4, 2, 2) + +API_AVAILABLE(macos(15.2)) +static void hvf_arch_put_sme(CPUState *cpu) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + const size_t svl_bytes =3D hvf_arm_sme2_get_svl(); + const size_t z_size =3D svl_bytes; + const size_t preg_size =3D DIV_ROUND_UP(z_size, 8); + const size_t za_size =3D svl_bytes * svl_bytes; + hv_vcpu_sme_state_t sme_state =3D { 0 }; + hv_return_t ret; + uint64_t svcr; + int n; + + /* + * Set PSTATE.{SM,ZA} bits + */ + svcr =3D arm_cpu->cpreg_values[arm_cpu->cpreg_array_len - 1]; + env->svcr =3D svcr; + + /* + * Construct SVCR (PSTATE.{SM,ZA}) state to pass to HVF: + */ + sme_state.streaming_sve_mode_enabled =3D FIELD_EX64(env->svcr, SVCR, S= M) > 0; + sme_state.za_storage_enabled =3D FIELD_EX64(env->svcr, SVCR, ZA) > 0; + ret =3D hv_vcpu_set_sme_state(cpu->accel->fd, &sme_state); + assert_hvf_ok(ret); + + /* + * We only care about Z/P registers if we're in streaming SVE mode, i.= e. + * PSTATE.SM is set, because only then can instructions that access th= em be + * used. We don't care about the register values otherwise. This is be= cause + * when the processing unit exits/enters this mode, it zeroes out those + * registers. + */ + if (sme_state.streaming_sve_mode_enabled) { + for (n =3D 0; n < ARRAY_SIZE(hvf_sme2_zreg_match); ++n) { + ret =3D hv_vcpu_set_sme_z_reg(cpu->accel->fd, + hvf_sme2_zreg_match[n].reg, + (uint8_t *)&env->vfp.zregs[n].d[0], + z_size); + assert_hvf_ok(ret); + } + + for (n =3D 0; n < ARRAY_SIZE(hvf_sme2_preg_match); ++n) { + ret =3D hv_vcpu_set_sme_p_reg(cpu->accel->fd, + hvf_sme2_preg_match[n].reg, + (uint8_t *)&env->vfp.pregs[n].p[0], + preg_size); + assert_hvf_ok(ret); + } + } + + /* + * If PSTATE.ZA bit is set then ZA and ZT0 are valid, otherwise they a= re + * zeroed out. + */ + if (sme_state.za_storage_enabled) { + hv_sme_zt0_uchar64_t tmp =3D { 0 }; + + memcpy(&tmp, &env->za_state.zt0, 64); + ret =3D hv_vcpu_set_sme_zt0_reg(cpu->accel->fd, &tmp); + assert_hvf_ok(ret); + + ret =3D hv_vcpu_set_sme_za_reg(cpu->accel->fd, + (uint8_t *)&env->za_state.za, + za_size); + assert_hvf_ok(ret); + } + + return; +} + +API_AVAILABLE(macos(15.2)) +static void hvf_arch_get_sme(CPUState *cpu) +{ + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + const size_t svl_bytes =3D hvf_arm_sme2_get_svl(); + const size_t z_size =3D svl_bytes; + const size_t preg_size =3D DIV_ROUND_UP(z_size, 8); + const size_t za_size =3D svl_bytes * svl_bytes; + hv_vcpu_sme_state_t sme_state =3D { 0 }; + hv_return_t ret; + uint64_t svcr; + int n; + + /* + * Get SVCR (PSTATE.{SM,ZA}) state from HVF: + */ + ret =3D hv_vcpu_get_sme_state(cpu->accel->fd, &sme_state); + assert_hvf_ok(ret); + + /* + * Set SVCR first because changing it will zero out Z/P regs + */ + svcr =3D + (sme_state.za_storage_enabled ? R_SVCR_ZA_MASK : 0) + | (sme_state.streaming_sve_mode_enabled ? R_SVCR_SM_MASK : 0); + + aarch64_set_svcr(env, svcr, R_SVCR_ZA_MASK | R_SVCR_SM_MASK); + arm_cpu->cpreg_values[arm_cpu->cpreg_array_len - 1] =3D svcr; + + /* + * We only care about Z/P registers if we're in streaming SVE mode, i.= e. + * PSTATE.SM is set, because only then can instructions that access th= em be + * used. We don't care about the register values otherwise. This is be= cause + * when the processing unit exits/enters this mode, it zeroes out those + * registers. + */ + if (sme_state.streaming_sve_mode_enabled) { + for (n =3D 0; n < ARRAY_SIZE(hvf_sme2_zreg_match); ++n) { + ret =3D hv_vcpu_get_sme_z_reg(cpu->accel->fd, + hvf_sme2_zreg_match[n].reg, + (uint8_t *)&env->vfp.zregs[n].d[0], + z_size); + assert_hvf_ok(ret); + } + + for (n =3D 0; n < ARRAY_SIZE(hvf_sme2_preg_match); ++n) { + ret =3D hv_vcpu_get_sme_p_reg(cpu->accel->fd, + hvf_sme2_preg_match[n].reg, + (uint8_t *)&env->vfp.pregs[n].p[0], + preg_size); + assert_hvf_ok(ret); + } + } + + /* + * If PSTATE.ZA bit is set then ZA and ZT0 are valid, otherwise they a= re + * zeroed out. + */ + if (sme_state.za_storage_enabled) { + hv_sme_zt0_uchar64_t tmp =3D { 0 }; + + /* Get ZT0 in a tmp vector, and then copy it to env.za_state.zt0 */ + ret =3D hv_vcpu_get_sme_zt0_reg(cpu->accel->fd, &tmp); + assert_hvf_ok(ret); + + memcpy(&env->za_state.zt0, &tmp, 64); + ret =3D hv_vcpu_get_sme_za_reg(cpu->accel->fd, + (uint8_t *)&env->za_state.za, + za_size); + assert_hvf_ok(ret); + + } + + return; +} =20 static uint32_t hvf_reg2cp_reg(uint32_t reg) { @@ -534,6 +767,10 @@ int hvf_arch_get_registers(CPUState *cpu) uint64_t kvm_id =3D arm_cpu->cpreg_indexes[i]; int hvf_id =3D KVMID_TO_HVF(kvm_id); =20 + if (kvm_id =3D=3D HVF_TO_KVMID(SVCR)) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_id) { @@ -627,6 +864,13 @@ int hvf_arch_get_registers(CPUState *cpu) =20 arm_cpu->cpreg_values[i] =3D val; } + if (cpu_isar_feature(aa64_sme, arm_cpu)) { + if (__builtin_available(macOS 15.2, *)) { + hvf_arch_get_sme(cpu); + } else { + g_assert_not_reached(); + } + } assert(write_list_to_cpustate(arm_cpu)); =20 aarch64_restore_sp(env, arm_current_el(env)); @@ -643,6 +887,18 @@ int hvf_arch_put_registers(CPUState *cpu) hv_simd_fp_uchar16_t fpval; int i, n; =20 + /* + * Set SVCR first because changing it will zero out Z/P (including NEO= N) + * regs + */ + if (cpu_isar_feature(aa64_sme, arm_cpu)) { + if (__builtin_available(macOS 15.2, *)) { + hvf_arch_put_sme(cpu); + } else { + g_assert_not_reached(); + } + } + for (i =3D 0; i < ARRAY_SIZE(hvf_reg_match); i++) { val =3D *(uint64_t *)((void *)env + hvf_reg_match[i].offset); ret =3D hv_vcpu_set_reg(cpu->accel->fd, hvf_reg_match[i].reg, val); @@ -672,6 +928,10 @@ int hvf_arch_put_registers(CPUState *cpu) uint64_t kvm_id =3D arm_cpu->cpreg_indexes[i]; int hvf_id =3D KVMID_TO_HVF(kvm_id); =20 + if (kvm_id =3D=3D HVF_TO_KVMID(SVCR)) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_id) { @@ -985,6 +1245,18 @@ int hvf_arch_init_vcpu(CPUState *cpu) hv_return_t ret; int i; =20 + if (__builtin_available(macOS 15.2, *)) { + sregs_match_len +=3D ARRAY_SIZE(hvf_sreg_list_sme2) + 1; + +#define DEF_SYSREG_15_02(HVF_ID, ...) \ + g_assert(HVF_ID =3D=3D KVMID_TO_HVF(KVMID_AA64_SYS_REG64(__VA_ARGS= __))); +#define DEF_SYSREG(...) + +#include "sysreg.c.inc" + +#undef DEF_SYSREG +#undef DEF_SYSREG_15_02 + } env->aarch64 =3D true; =20 /* system count frequency sanity check */ @@ -1005,7 +1277,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); =20 /* Populate cp list for all known sysregs */ - for (i =3D 0; i < sregs_match_len; i++) { + for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_list); i++) { hv_sys_reg_t hvf_id =3D hvf_sreg_list[i]; uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); uint32_t key =3D kvm_to_cpreg_id(kvm_id); @@ -1016,6 +1288,24 @@ int hvf_arch_init_vcpu(CPUState *cpu) arm_cpu->cpreg_indexes[sregs_cnt++] =3D kvm_id; } } + if (__builtin_available(macOS 15.2, *)) { + for (i =3D 0; i < ARRAY_SIZE(hvf_sreg_list_sme2); i++) { + hv_sys_reg_t hvf_id =3D hvf_sreg_list_sme2[i]; + uint64_t kvm_id =3D HVF_TO_KVMID(hvf_id); + uint32_t key =3D kvm_to_cpreg_id(kvm_id); + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(arm_cpu->cp_regs= , key); + + if (ri) { + assert(!(ri->type & ARM_CP_NO_RAW)); + arm_cpu->cpreg_indexes[sregs_cnt++] =3D kvm_id; + } + } + /* + * Add SVCR last. It is elsewhere assumed its index is after + * hvf_sreg_list and hvf_sreg_list_sme2. + */ + arm_cpu->cpreg_indexes[sregs_cnt++] =3D HVF_TO_KVMID(SVCR); + } arm_cpu->cpreg_array_len =3D sregs_cnt; arm_cpu->cpreg_vmstate_array_len =3D sregs_cnt; =20 diff --git a/target/arm/hvf/hvf_sme_stubs.h b/target/arm/hvf/hvf_sme_stubs.h new file mode 100644 index 0000000000000000000000000000000000000000..9c679b711017448681e532b88ce= 10a07ebfd5122 --- /dev/null +++ b/target/arm/hvf/hvf_sme_stubs.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +typedef int32_t hv_return_t; +typedef uint64_t hv_vcpu_t; + +static inline bool hvf_arm_sme2_supported(void) +{ + return false; +} + +static inline uint32_t hvf_arm_sme2_get_svl(void) +{ + g_assert_not_reached(); +} + +typedef enum hv_sme_p_reg_t { + HV_SME_P_REG_0, + HV_SME_P_REG_1, + HV_SME_P_REG_2, + HV_SME_P_REG_3, + HV_SME_P_REG_4, + HV_SME_P_REG_5, + HV_SME_P_REG_6, + HV_SME_P_REG_7, + HV_SME_P_REG_8, + HV_SME_P_REG_9, + HV_SME_P_REG_10, + HV_SME_P_REG_11, + HV_SME_P_REG_12, + HV_SME_P_REG_13, + HV_SME_P_REG_14, + HV_SME_P_REG_15, +} hv_sme_p_reg_t; + +typedef __attribute__((ext_vector_type(64))) uint8_t hv_sme_zt0_uchar64_t; + +typedef enum hv_sme_z_reg_t { + HV_SME_Z_REG_0, + HV_SME_Z_REG_1, + HV_SME_Z_REG_2, + HV_SME_Z_REG_3, + HV_SME_Z_REG_4, + HV_SME_Z_REG_5, + HV_SME_Z_REG_6, + HV_SME_Z_REG_7, + HV_SME_Z_REG_8, + HV_SME_Z_REG_9, + HV_SME_Z_REG_10, + HV_SME_Z_REG_11, + HV_SME_Z_REG_12, + HV_SME_Z_REG_13, + HV_SME_Z_REG_14, + HV_SME_Z_REG_15, + HV_SME_Z_REG_16, + HV_SME_Z_REG_17, + HV_SME_Z_REG_18, + HV_SME_Z_REG_19, + HV_SME_Z_REG_20, + HV_SME_Z_REG_21, + HV_SME_Z_REG_22, + HV_SME_Z_REG_23, + HV_SME_Z_REG_24, + HV_SME_Z_REG_25, + HV_SME_Z_REG_26, + HV_SME_Z_REG_27, + HV_SME_Z_REG_28, + HV_SME_Z_REG_29, + HV_SME_Z_REG_30, + HV_SME_Z_REG_31, +} hv_sme_z_reg_t; + +enum { + HV_SYS_REG_SMCR_EL1, + HV_SYS_REG_SMPRI_EL1, + HV_SYS_REG_TPIDR2_EL0, + HV_SYS_REG_ID_AA64ZFR0_EL1, + HV_SYS_REG_ID_AA64SMFR0_EL1, +}; + +typedef struct { + bool streaming_sve_mode_enabled; + bool za_storage_enabled; +} hv_vcpu_sme_state_t; + +static inline hv_return_t hv_sme_config_get_max_svl_bytes(size_t *value) +{ + g_assert_not_reached(); +} + +static inline hv_return_t hv_vcpu_get_sme_state(hv_vcpu_t vcpu, + hv_vcpu_sme_state_t *sme_s= tate) +{ + g_assert_not_reached(); +} + +static inline hv_return_t hv_vcpu_set_sme_state(hv_vcpu_t vcpu, + const hv_vcpu_sme_state_t = *sme_state) +{ + g_assert_not_reached(); +} + +static inline hv_return_t hv_vcpu_get_sme_z_reg(hv_vcpu_t vcpu, + hv_sme_z_reg_t reg, + uint8_t *value, + size_t length) +{ + g_assert_not_reached(); +} + +static inline hv_return_t hv_vcpu_set_sme_z_reg(hv_vcpu_t vcpu, + hv_sme_z_reg_t reg, + const uint8_t *value, + size_t length) +{ + g_assert_not_reached(); +} + +static inline hv_return_t hv_vcpu_get_sme_p_reg(hv_vcpu_t vcpu, + hv_sme_p_reg_t reg, + uint8_t *value, + size_t length) +{ + g_assert_not_reached(); +} + +static inline hv_return_t hv_vcpu_set_sme_p_reg(hv_vcpu_t vcpu, + hv_sme_p_reg_t reg, + const uint8_t *value, + size_t length) +{ + g_assert_not_reached(); +} + +static inline hv_return_t hv_vcpu_get_sme_za_reg(hv_vcpu_t vcpu, + uint8_t *value, + size_t length) +{ + g_assert_not_reached(); +} + +static inline hv_return_t hv_vcpu_set_sme_za_reg(hv_vcpu_t vcpu, + const uint8_t *value, + size_t length) +{ + g_assert_not_reached(); +} + +static inline hv_return_t hv_vcpu_get_sme_zt0_reg(hv_vcpu_t vcpu, + hv_sme_zt0_uchar64_t *va= lue) +{ + g_assert_not_reached(); +} + +static inline hv_return_t hv_vcpu_set_sme_zt0_reg(hv_vcpu_t vcpu, + const hv_sme_zt0_uchar64= _t *value) +{ + g_assert_not_reached(); +} diff --git a/target/arm/hvf/sysreg.c.inc b/target/arm/hvf/sysreg.c.inc index 067a8603fa785593ed0879cea26d036b0ec2823e..7a2f880f784b7610b14a6eb91fe= c1817e98bfd2e 100644 --- a/target/arm/hvf/sysreg.c.inc +++ b/target/arm/hvf/sysreg.c.inc @@ -145,3 +145,11 @@ DEF_SYSREG(HV_SYS_REG_TPIDRRO_EL0, 3, 3, 13, 0, 3) DEF_SYSREG(HV_SYS_REG_CNTV_CTL_EL0, 3, 3, 14, 3, 1) DEF_SYSREG(HV_SYS_REG_CNTV_CVAL_EL0, 3, 3, 14, 3, 2) DEF_SYSREG(HV_SYS_REG_SP_EL1, 3, 4, 4, 1, 0) + +DEF_SYSREG_15_02(HV_SYS_REG_SMCR_EL1, 3, 0, 1, 2, 6) +DEF_SYSREG_15_02(HV_SYS_REG_SMPRI_EL1, 3, 0, 1, 2, 4) +DEF_SYSREG_15_02(HV_SYS_REG_TPIDR2_EL0, 3, 3, 13, 0, 5) +DEF_SYSREG_15_02(HV_SYS_REG_ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4) +DEF_SYSREG_15_02(HV_SYS_REG_ID_AA64SMFR0_EL1, 3, 0, 0, 4, 5) +DEF_SYSREG_15_02(HV_SYS_REG_SMPRI_EL1, 3, 0, 1, 2, 4) +DEF_SYSREG_15_02(HV_SYS_REG_SMCR_EL1, 3, 0, 1, 2, 6) diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index 5d19d82e5ded66bc02da10523c0f7138840ecff3..6b1c3b9792dfd7d81ef747d8a66= 76a23fd212d84 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -22,4 +22,45 @@ void hvf_arm_init_debug(void); =20 void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 +/* + * We need access to types from macOS SDK >=3D15.2, so expose stubs if the + * headers are not available until we raise our minimum macOS version. + */ +#ifdef __MAC_OS_X_VERSION_MAX_ALLOWED + #if (__MAC_OS_X_VERSION_MAX_ALLOWED >=3D 150200) + #include "system/hvf_int.h" + + static inline bool hvf_arm_sme2_supported(void) + { + if (__builtin_available(macOS 15.2, *)) { + size_t svl_bytes; + hv_return_t result =3D hv_sme_config_get_max_svl_bytes(&svl_by= tes); + if (result =3D=3D HV_UNSUPPORTED) { + return false; + } + assert_hvf_ok(result); + return svl_bytes > 0; + } else { + return false; + } + } + + static inline uint32_t hvf_arm_sme2_get_svl(void) + { + if (__builtin_available(macOS 15.2, *)) { + size_t svl_bytes; + hv_return_t result =3D hv_sme_config_get_max_svl_bytes(&svl_by= tes); + assert_hvf_ok(result); + return svl_bytes; + } else { + abort(); + } + } + #else /* (__MAC_OS_X_VERSION_MAX_ALLOWED >=3D 150200) */ + #include "hvf/hvf_sme_stubs.h" + #endif /* (__MAC_OS_X_VERSION_MAX_ALLOWED >=3D 150200) */ +#else /* ifdef __MAC_OS_X_VERSION_MAX_ALLOWED */ + #include "hvf/hvf_sme_stubs.h" +#endif /* ifdef __MAC_OS_X_VERSION_MAX_ALLOWED */ + #endif diff --git a/target/arm/machine.c b/target/arm/machine.c index bbaae3444928985813b7dcc91888784d06cfe305..81a506ce4cc09493dd7faed8865= 2d8d246e23187 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -231,7 +231,7 @@ static bool sve_needed(void *opaque) { ARMCPU *cpu =3D opaque; =20 - return cpu_isar_feature(aa64_sve, cpu); + return cpu_isar_feature(aa64_sve, cpu) || cpu_isar_feature(aa64_sme, c= pu); } =20 /* The first two words of each Zreg is stored in VFP state. */ --=20 2.47.3 From nobody Mon Mar 2 08:49:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1772182658; cv=none; d=zohomail.com; s=zohoarc; b=QuXPQ8HRZ9IkQ5v6UrcWEjWofjk1ptMu2rgtfj2aL/dK5e4W+24i/m1zUja7l4AiCUT2Io9Kh0qVbuZQjax2z/RJgfNdxMLcBMShEvUkhUZjqnN53ikxVQegbQ/NfRhr439B9AInHa8Hmswyi/gJH/Bm+iL1S0wb0/2DZ30hpQI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772182658; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Fri, 27 Feb 2026 00:56:52 -0800 (PST) From: Manos Pitsidianakis Date: Fri, 27 Feb 2026 10:56:47 +0200 Subject: [PATCH v5 2/2] hvf/arm: expose FEAT_SME2 to guest if available MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260227-sme2-hvf-v5-2-1c60a92910c8@linaro.org> References: <20260227-sme2-hvf-v5-0-1c60a92910c8@linaro.org> In-Reply-To: <20260227-sme2-hvf-v5-0-1c60a92910c8@linaro.org> To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Phil_Mathieu-Daud=C3=A9?= , Alexander Graf , Mads Ynddal , Peter Maydell , qemu-arm@nongnu.org, Mohamed Mediouni , Manos Pitsidianakis X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3015; i=manos.pitsidianakis@linaro.org; h=from:subject:message-id; bh=DSE/MXyaOS7n6x2sc6v69f4/nWX+OmFzPuV6RjDvJgs=; b=LS0tLS1CRUdJTiBQR1AgTUVTU0FHRS0tLS0tCgpvd0VCYlFLUy9aQU5Bd0FLQVhjcHgzQi9mZ 25RQWNzbVlnQnBvVnhRRzd0ZWNyY0EvTm9tWmJBbm9UUFZvcmt5CjlnK2Q2a040dm9ZZ3RaUG9h MytKQWpNRUFBRUtBQjBXSVFUTVhCdE9SS0JXODRkd0hSQjNLY2R3ZjM0SjBBVUMKYWFGY1VBQUt DUkIzS2Nkd2YzNEowSEc4RC80amJuaXJ4bWdGM3ppYXRkWXE4aHo3cktIUkkxT3I0dmgvcU1raw owWWlWQWh1ait3K1RWSDJObVNaOWEzaitFSEFDeUdUY0VkMWJERHFzYjJpMUlRK1VpcW00b0ROV 2syeU5raG9WCjE0RkpJU2tXVE45YTVPaGtrZHBlUG00M0lmM25BSVJ5TlB2WC8wTXFydFFTV2Rq YzVnZDBWaUh3TTFpbitaOHMKYm1FdTV0cytmVE1xZC9IMzE2aVo3UUp1UVhuOCtTcTd5aVJnUWZ 4VURpVk1FbjJTZkRxdklyWC81TVZWSjdEMgoxMUx6Wi9iYXFYVDk2djdaSVBFSERqeEdsTHBwRG 9qM21LSjEzUFh5dXFaaFpVMjM1aW9PZjNBaURnTXRYSHN1CkQrRngxekduVnBHSVhIZ2pyT2poa XBXdlhrQXVldnpUN3llNUlmNDZKaCtvSG5zWCs4Qm1PZWgzc0JLZDRvVTAKU3dWSmZFMVk4MDRZ QjR2VTh5VDBUbzBZMytsQ2VCMm9LT0ZsWnpDdzBWaGcrTWxydE93TjdiSWxJWlY3VXVhRAoycXJ ld09aLzBDeUNEdnF0aDZxU0hNMXpzSXJNU2RvZHN5dFdpczEwY1kyanB2Y0VTNVNOYVhReFZ4ZG ZvSFNGClg2R3BDTDJLa0pLTWc1QlpSdTh4WXkzcWpBQWRMSTlMU3JZaGRaZGdyVkdqV3hXZTBNW WpOUUV6TlVENm5ndm8KWEFzTzVnTjlkelJ5TEF4RWlIT3VLcVRKVlJIanlkbTZaTzhpZG92WDE3 dVpqMFVtZUtiTWdhV3Z6cXNhMy9odwo4Q1g0S014NlFGVkZGdnUvRzBRcnE1NUh2N1pIbG96UDd kbnZIbUdtdVhTejBWeWR0YUhnK1pQZWRic2pzVVl5CnlhbnhQdz09Cj1GKzFZCi0tLS0tRU5EIF BHUCBNRVNTQUdFLS0tLS0K X-Developer-Key: i=manos.pitsidianakis@linaro.org; a=openpgp; fpr=7C721DF9DB3CC7182311C0BF68BC211D47B421E1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=manos.pitsidianakis@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1772182660382158500 Starting from M4 cores and MacOS 15.2 SDK, HVF can virtualise FEAT_SME2. Signed-off-by: Manos Pitsidianakis --- target/arm/hvf/hvf.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 3d194680cc87e78835098df2e0e7987ed544c553..bc650c682ea6b0f1b6a144a2ccd= bb3e8aaec29b4 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -315,6 +315,7 @@ typedef struct ARMHostCPUFeatures { uint64_t features; uint64_t midr; uint32_t reset_sctlr; + uint32_t sme_vq_supported; const char *dtb_compatible; } ARMHostCPUFeatures; =20 @@ -1121,18 +1122,18 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCP= UFeatures *ahcf) =20 clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 - /* - * Disable SME, which is not properly handled by QEMU hvf yet. - * To allow this through we would need to: - * - make sure that the SME state is correctly handled in the - * get_registers/put_registers functions - * - get the SME-specific CPU properties to work with accelerators - * other than TCG - * - fix any assumptions we made that SME implies SVE (since - * on the M4 there is SME but not SVE) - */ - SET_IDREG(&host_isar, ID_AA64PFR1, - GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK= ); + if (hvf_arm_sme2_supported()) { + t =3D GET_IDREG(&host_isar, ID_AA64PFR1); + t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* FEAT_SME2 */ + SET_IDREG(&host_isar, ID_AA64PFR1, t); + + t =3D GET_IDREG(&host_isar, ID_AA64SMFR0); + t =3D FIELD_DP64(t, ID_AA64SMFR0, SMEVER, 1); /* FEAT_SME2 */ + SET_IDREG(&host_isar, ID_AA64SMFR0, t); + } else { + SET_IDREG(&host_isar, ID_AA64PFR1, + GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MA= SK); + } =20 ahcf->isar =3D host_isar; =20 @@ -1148,6 +1149,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) */ ahcf->reset_sctlr |=3D 0x00800000; =20 + ahcf->sme_vq_supported =3D hvf_arm_sme2_supported() ? hvf_arm_sme2_get= _svl() : 0; + /* Make sure we don't advertise AArch32 support for EL0/EL1 */ if ((GET_IDREG(&host_isar, ID_AA64PFR0) & 0xff) !=3D 0x11) { return false; @@ -1199,6 +1202,7 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) cpu->env.features =3D arm_host_cpu_features.features; cpu->midr =3D arm_host_cpu_features.midr; cpu->reset_sctlr =3D arm_host_cpu_features.reset_sctlr; + cpu->sme_vq.supported =3D arm_host_cpu_features.sme_vq_supported; } =20 void hvf_arch_vcpu_destroy(CPUState *cpu) @@ -1339,6 +1343,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); assert_hvf_ok(ret); =20 + aarch64_add_sme_properties(OBJECT(cpu)); return 0; } =20 --=20 2.47.3