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d="scan'208";a="315126421" Date: Fri, 27 Feb 2026 13:54:31 +0100 Subject: [PATCH v2 2/3] include/exec: Provide the cpu_internal_tswap() functions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260227-semihosting-cpu-tswap-v2-2-cbdcdf39dd15@eonerc.rwth-aachen.de> References: <20260227-semihosting-cpu-tswap-v2-0-cbdcdf39dd15@eonerc.rwth-aachen.de> In-Reply-To: <20260227-semihosting-cpu-tswap-v2-0-cbdcdf39dd15@eonerc.rwth-aachen.de> To: CC: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , =?utf-8?q?Martin_Kr=C3=B6ning?= X-Mailer: b4 0.14.3 X-Originating-IP: [134.99.235.10] X-ClientProxiedBy: rwthex-s1-a.rwth-ad.de (2a00:8a60:1:e500::26:152) To rwthex-s2-a.rwth-ad.de (2a00:8a60:1:e500::26:154) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:48; envelope-from=martin.kroening@eonerc.rwth-aachen.de; helo=mail-out-3.itc.rwth-aachen.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: =?utf-8?q?Martin_Kr=C3=B6ning?= From: =?utf-8?q?Martin_Kr=C3=B6ning?= via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772196986779158500 These functions are needed to support semihosting on CPUs that support runtime-configurable endianness. They should not be used in other contexts. Signed-off-by: Martin Kr=C3=B6ning --- include/exec/tswap.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/include/exec/tswap.h b/include/exec/tswap.h index 9e94fa0021..6d9301129d 100644 --- a/include/exec/tswap.h +++ b/include/exec/tswap.h @@ -10,6 +10,7 @@ =20 #include "qemu/bswap.h" #include "qemu/target-info.h" +#include "hw/core/cpu.h" =20 /* * If we're in target-specific code, we can hard-code the swapping @@ -72,4 +73,39 @@ static inline void tswap64s(uint64_t *s) } #endif =20 +/* + * If we're in semihosting code, have to swap depending on the currently + * configured endianness of the CPU. These functions should not be used in + * other contexts. + */ +#define cpu_internal_needs_bswap(cpu) \ + (HOST_BIG_ENDIAN !=3D cpu_internal_is_big_endian(cpu)) + +static inline uint16_t cpu_internal_tswap16(CPUState *cpu, uint16_t s) +{ + if (target_needs_bswap() || cpu_internal_needs_bswap(cpu)) { + return bswap16(s); + } else { + return s; + } +} + +static inline uint32_t cpu_internal_tswap32(CPUState *cpu, uint32_t s) +{ + if (target_needs_bswap() || cpu_internal_needs_bswap(cpu)) { + return bswap32(s); + } else { + return s; + } +} + +static inline uint64_t cpu_internal_tswap64(CPUState *cpu, uint64_t s) +{ + if (target_needs_bswap() || cpu_internal_needs_bswap(cpu)) { + return bswap64(s); + } else { + return s; + } +} + #endif /* TSWAP_H */ --=20 Git-155)