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d="scan'208";a="177606919" Date: Fri, 27 Feb 2026 13:54:30 +0100 Subject: [PATCH v2 1/3] include/hw/core: Rename virtio_is_big_endian to internal_is_big_endian MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260227-semihosting-cpu-tswap-v2-1-cbdcdf39dd15@eonerc.rwth-aachen.de> References: <20260227-semihosting-cpu-tswap-v2-0-cbdcdf39dd15@eonerc.rwth-aachen.de> In-Reply-To: <20260227-semihosting-cpu-tswap-v2-0-cbdcdf39dd15@eonerc.rwth-aachen.de> To: CC: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , =?utf-8?q?Martin_Kr=C3=B6ning?= X-Mailer: b4 0.14.3 X-Originating-IP: [134.99.235.10] X-ClientProxiedBy: rwthex-s1-a.rwth-ad.de (2a00:8a60:1:e500::26:152) To rwthex-s2-a.rwth-ad.de (2a00:8a60:1:e500::26:154) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:45; envelope-from=martin.kroening@eonerc.rwth-aachen.de; helo=mail-out-2a.itc.rwth-aachen.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: =?utf-8?q?Martin_Kr=C3=B6ning?= From: =?utf-8?q?Martin_Kr=C3=B6ning?= via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772196991416158500 These functions are needed to do semihosting on CPUs that support runtime-configurable endiannes. This commit renames them and allows using them for semihosting, but makes sure to signal that these functions should not be used in other circumstances. Signed-off-by: Martin Kr=C3=B6ning --- hw/core/cpu-system.c | 6 +++--- hw/virtio/virtio.c | 2 +- include/hw/core/cpu.h | 4 ++-- include/hw/core/sysemu-cpu-ops.h | 6 +++--- target/arm/cpu.c | 4 ++-- target/ppc/cpu_init.c | 2 +- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/hw/core/cpu-system.c b/hw/core/cpu-system.c index 4a91c3e8ec..273b9b7c22 100644 --- a/hw/core/cpu-system.c +++ b/hw/core/cpu-system.c @@ -127,10 +127,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPU= State *cpu, return (*cpu->cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); } =20 -bool cpu_virtio_is_big_endian(CPUState *cpu) +bool cpu_internal_is_big_endian(CPUState *cpu) { - if (cpu->cc->sysemu_ops->virtio_is_big_endian) { - return cpu->cc->sysemu_ops->virtio_is_big_endian(cpu); + if (cpu->cc->sysemu_ops->internal_is_big_endian) { + return cpu->cc->sysemu_ops->internal_is_big_endian(cpu); } return target_big_endian(); } diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index e9d5532952..f6454971ab 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -2317,7 +2317,7 @@ static enum virtio_device_endian virtio_default_endia= n(void) =20 static enum virtio_device_endian virtio_current_cpu_endian(void) { - if (cpu_virtio_is_big_endian(current_cpu)) { + if (cpu_internal_is_big_endian(current_cpu)) { return VIRTIO_DEVICE_ENDIAN_BIG; } else { return VIRTIO_DEVICE_ENDIAN_LITTLE; diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 7d2f4459d2..04e1f970ca 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -782,13 +782,13 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr a= ddr); int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 /** - * cpu_virtio_is_big_endian: + * cpu_internal_is_big_endian: * @cpu: CPU =20 * Returns %true if a CPU which supports runtime configurable endianness * is currently big-endian. */ -bool cpu_virtio_is_big_endian(CPUState *cpu); +bool cpu_internal_is_big_endian(CPUState *cpu); =20 /** * cpu_has_work: diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 877892373f..7b2d2d2610 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -77,13 +77,13 @@ typedef struct SysemuCPUOps { int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, DumpState *s); /** - * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts + * @internal_is_big_endian: Callback to return %true if a CPU which su= pports * runtime configurable endianness is currently big-endian. * Non-configurable CPUs can use the default implementation of this me= thod. * This method should not be used by any callers other than the pre-1.0 - * virtio devices. + * virtio devices and the semihosting interface. */ - bool (*virtio_is_big_endian)(CPUState *cpu); + bool (*internal_is_big_endian)(CPUState *cpu); =20 /** * @legacy_vmsd: Legacy state for migration. diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7e3e84b4bb..98d09ac065 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -756,7 +756,7 @@ static void arm_cpu_set_irq(void *opaque, int irq, int = level) } } =20 -static bool arm_cpu_virtio_is_big_endian(CPUState *cs) +static bool arm_cpu_internal_is_big_endian(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -2299,7 +2299,7 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, - .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, + .internal_is_big_endian =3D arm_cpu_internal_is_big_endian, .legacy_vmsd =3D &vmstate_arm_cpu, }; #endif diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 3d932a5642..191f5726f6 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7480,7 +7480,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops =3D { .get_phys_page_debug =3D ppc_cpu_get_phys_page_debug, .write_elf32_note =3D ppc32_cpu_write_elf32_note, .write_elf64_note =3D ppc64_cpu_write_elf64_note, - .virtio_is_big_endian =3D ppc_cpu_is_big_endian, + .internal_is_big_endian =3D ppc_cpu_is_big_endian, .legacy_vmsd =3D &vmstate_ppc_cpu, }; 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d="scan'208";a="315126421" Date: Fri, 27 Feb 2026 13:54:31 +0100 Subject: [PATCH v2 2/3] include/exec: Provide the cpu_internal_tswap() functions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260227-semihosting-cpu-tswap-v2-2-cbdcdf39dd15@eonerc.rwth-aachen.de> References: <20260227-semihosting-cpu-tswap-v2-0-cbdcdf39dd15@eonerc.rwth-aachen.de> In-Reply-To: <20260227-semihosting-cpu-tswap-v2-0-cbdcdf39dd15@eonerc.rwth-aachen.de> To: CC: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , =?utf-8?q?Martin_Kr=C3=B6ning?= X-Mailer: b4 0.14.3 X-Originating-IP: [134.99.235.10] X-ClientProxiedBy: rwthex-s1-a.rwth-ad.de (2a00:8a60:1:e500::26:152) To rwthex-s2-a.rwth-ad.de (2a00:8a60:1:e500::26:154) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:48; envelope-from=martin.kroening@eonerc.rwth-aachen.de; helo=mail-out-3.itc.rwth-aachen.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: =?utf-8?q?Martin_Kr=C3=B6ning?= From: =?utf-8?q?Martin_Kr=C3=B6ning?= via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772196986779158500 These functions are needed to support semihosting on CPUs that support runtime-configurable endianness. They should not be used in other contexts. Signed-off-by: Martin Kr=C3=B6ning --- include/exec/tswap.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/include/exec/tswap.h b/include/exec/tswap.h index 9e94fa0021..6d9301129d 100644 --- a/include/exec/tswap.h +++ b/include/exec/tswap.h @@ -10,6 +10,7 @@ =20 #include "qemu/bswap.h" #include "qemu/target-info.h" +#include "hw/core/cpu.h" =20 /* * If we're in target-specific code, we can hard-code the swapping @@ -72,4 +73,39 @@ static inline void tswap64s(uint64_t *s) } #endif =20 +/* + * If we're in semihosting code, have to swap depending on the currently + * configured endianness of the CPU. These functions should not be used in + * other contexts. + */ +#define cpu_internal_needs_bswap(cpu) \ + (HOST_BIG_ENDIAN !=3D cpu_internal_is_big_endian(cpu)) + +static inline uint16_t cpu_internal_tswap16(CPUState *cpu, uint16_t s) +{ + if (target_needs_bswap() || cpu_internal_needs_bswap(cpu)) { + return bswap16(s); + } else { + return s; + } +} + +static inline uint32_t cpu_internal_tswap32(CPUState *cpu, uint32_t s) +{ + if (target_needs_bswap() || cpu_internal_needs_bswap(cpu)) { + return bswap32(s); + } else { + return s; + } +} + +static inline uint64_t cpu_internal_tswap64(CPUState *cpu, uint64_t s) +{ + if (target_needs_bswap() || cpu_internal_needs_bswap(cpu)) { + return bswap64(s); + } else { + return s; + } +} + #endif /* TSWAP_H */ --=20 Git-155) From nobody Mon Mar 2 08:46:52 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@rwth-aachen.de; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="22715524" Date: Fri, 27 Feb 2026 13:54:32 +0100 Subject: [PATCH v2 3/3] semihosting/uaccess: Use the cpu_internal_tswap() functions MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260227-semihosting-cpu-tswap-v2-3-cbdcdf39dd15@eonerc.rwth-aachen.de> References: <20260227-semihosting-cpu-tswap-v2-0-cbdcdf39dd15@eonerc.rwth-aachen.de> In-Reply-To: <20260227-semihosting-cpu-tswap-v2-0-cbdcdf39dd15@eonerc.rwth-aachen.de> To: CC: =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , =?utf-8?q?Martin_Kr=C3=B6ning?= X-Mailer: b4 0.14.3 X-Originating-IP: [134.99.235.10] X-ClientProxiedBy: rwthex-s1-a.rwth-ad.de (2a00:8a60:1:e500::26:152) To rwthex-s2-a.rwth-ad.de (2a00:8a60:1:e500::26:154) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:8a60:1:e501::5:49; envelope-from=martin.kroening@eonerc.rwth-aachen.de; helo=mail-out-4.itc.rwth-aachen.de X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: =?utf-8?q?Martin_Kr=C3=B6ning?= From: =?utf-8?q?Martin_Kr=C3=B6ning?= via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772196987055158500 The semihosting ABI [1] states: > Multi-byte values in memory must be formatted as pure little-endian or pu= re > big-endian to match the endianness mapping configuration of the processor. This commits ensures that semihosting data is properly byte-swapped if the guest's CPU is currently in a different runtime-configurable endianness than the host's CPU. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3258 Buglink: https://github.com/taiki-e/semihosting/issues/18 [1]: https://github.com/ARM-software/abi-aa/blob/2025Q1/semihosting/semihos= ting.rst#the-semihosting-interface Signed-off-by: Martin Kr=C3=B6ning --- include/semihosting/uaccess.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/semihosting/uaccess.h b/include/semihosting/uaccess.h index 2093a49827..0911e3b31d 100644 --- a/include/semihosting/uaccess.h +++ b/include/semihosting/uaccess.h @@ -28,7 +28,7 @@ ({ uint64_t val_ =3D 0; \ int ret_ =3D cpu_memory_rw_debug(env_cpu(env), (addr), \ &val_, sizeof(val_), 0); \ - (val) =3D tswap64(val_); ret_; }) + (val) =3D cpu_internal_tswap64(cs, val_); ret_; }) =20 /** * get_user_u32: @@ -39,7 +39,7 @@ ({ uint32_t val_ =3D 0; \ int ret_ =3D cpu_memory_rw_debug(env_cpu(env), (addr), \ &val_, sizeof(val_), 0); \ - (val) =3D tswap32(val_); ret_; }) + (val) =3D cpu_internal_tswap32(cs, val_); ret_; }) =20 /** * get_user_u8: @@ -65,7 +65,7 @@ * Returns: 0 on success, -1 on error. */ #define put_user_u64(val, addr) \ - ({ uint64_t val_ =3D tswap64(val); \ + ({ uint64_t val_ =3D cpu_internal_tswap64(cs, val); \ cpu_memory_rw_debug(env_cpu(env), (addr), &val_, sizeof(val_), 1); = }) =20 /** @@ -74,7 +74,7 @@ * Returns: 0 on success, -1 on error. */ #define put_user_u32(val, addr) \ - ({ uint32_t val_ =3D tswap32(val); \ + ({ uint32_t val_ =3D cpu_internal_tswap32(cs, val); \ cpu_memory_rw_debug(env_cpu(env), (addr), &val_, sizeof(val_), 1); = }) =20 /** --=20 Git-155)