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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4399c75b8afsm407235f8f.23.2026.02.26.07.55.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Feb 2026 07:55:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1772121351; x=1772726151; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ZfBUJaYraA8yxuxaiXVVUn603JpjW9lcSMUyJUScvg0=; b=H+zAsPKnzipjVL8CmSxqh3n34WT8ctXV0UoyzUyzt9vKsbxUefrP4Drt8PJydxX9MH 9DntlvTK1IJDsgklsxPUKZeGdIf4x0ErSMy8F9cdr4LEEw1ec9MKoq47GKpcM7cOIXja Yh7LjfRpPVpQT1XBtFNBDI7IJYuhPRPjyNjYOTftBKFULOXnh/jqtwbQZB+yDu2mSqMD fCAuBOhqy53gQtWSrW2UOHUiDww/aH/THL0hddaJdtN7c8RIWcMpaeojPo2rt9dAdE8G Mp6UJtDiYlJxZYSdSeLR1DGvhPnsWNDw6BptxjfAUymvt6YPNMEI9+9+L2RGTp3rgkvR 0tvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772121351; x=1772726151; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ZfBUJaYraA8yxuxaiXVVUn603JpjW9lcSMUyJUScvg0=; b=QeSXUmp4O87sTb9JPmsF954+5JTCgPL89EJNjIzD2sHOXRi3qUpW3jF0bMNeDypfwz Db9twb42zap1qwHu8dn6aoko9Hw0aLUhBBqSaapjEcjPdFf4huKtOAg9M0yxjca2uUhx wygK4dKwDLFeX6oGm74ZHRXUO8OE7j1PlS3viRKu/vdd664JQaOB1UHUnnsYkR/xfczA zkj4HMZ+01p8ssYIZNSVKARDjLGNTdKSYBL7R7n+Prm6sDYrovjhUDuZhMx4F6dS4oyY gRN5fRpaGw5CvxOnwTC9ZtywvqoJBW+Xllcp0hZ7sbmY/+qyqUQECKTq2srsuLZ6xbBK pGtw== X-Gm-Message-State: AOJu0YxFl9BoAG49kSHarfI5TuhGlljrRLJ1RFA+tjh78O4TvAzZ65sY HFWxgVp2vtNmMjCS1beQpyMhxd8poQuGT6Ji8+STqgOdLgiz1F6U7y2hc+RyzVBHVXLRPV8bzi9 kVwwC X-Gm-Gg: ATEYQzz0I2Daj105BycRpPGHQLWYdB191Qi69XFwzd9YiaFD9RnqYEyG6ku4IOvP3+v TChJHw4VzDt2XGiCULbNEi8jvegLJpR9ZJvoY0wHo4JoDi5dkhoiUg379fVRh+aeqAZKBBlwcPp 89KjmcV3zP8ugoTb4swDTeDfKdE9glvj+sujdhQdNnhoNorjl5y0nRN/oKXCNeMtKdHGWxP8gLs id+RGTWrXFUe/VKgDKyqqC2hxK3YTMVVkmj0gb54lIHw+mBPMdKR6zpse92R4Wczz8PNwxqY/zK l4wtfIBozt2G5UFRw3lSkDkut0SVeMgeZQX+KDaFg9YREhtEMFAE8xRPXZTWqj/jeDlO1kcZHqk YPtc3heeDq5owu9eNWLwTrroap4wJtUJ4OBqSSX/l3U0c3Dur45CYvQkZm4t4O5QspvUxWSpipt AdzmTybh4AVUDZJE3gr0ohuB7CcVV5X8FRRsdn4h9/GzRNBwjPgBv++QUdYQjc/FKwg9X/OZaJV cDM4ztCag5Vj7wvM7QHimAhzr2gBrQ= X-Received: by 2002:a05:6000:290b:b0:439:8d77:4dad with SMTP id ffacd0b85a97d-43994305b07mr8859477f8f.55.1772121350521; Thu, 26 Feb 2026 07:55:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/20] target/arm: Move kvm test out of cpu_arm_set_sve Date: Thu, 26 Feb 2026 15:55:28 +0000 Message-ID: <20260226155535.1171290-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226155535.1171290-1-peter.maydell@linaro.org> References: <20260226155535.1171290-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1772121556101158500 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Introduce a set of stub property callbacks for when we really don't want to be able to enable SVE. Register the real or stub funtions in aarch64_add_sve_properties depending on whether or not SVE is available. Adjust aarch64_a64fx_initfn to initialize the set of supported vector sizes before calling aarch64_add_sve_properties. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20260216034432.23912-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 48 ++++++++++++++++++++++++++++++++++++------ target/arm/tcg/cpu64.c | 2 +- 2 files changed, 42 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 209ab5c344..58215216c5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -300,6 +300,30 @@ static void cpu_arm_set_vq(Object *obj, Visitor *v, co= nst char *name, vq_map->init |=3D 1 << (vq - 1); } =20 +static void prop_bool_get_false(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D false; + visit_type_bool(v, name, &value, errp); +} + +static void prop_bool_set_false(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value; + + if (visit_type_bool(v, name, &value, errp) && value) { + error_setg(errp, "'%s' feature not supported by %s on this host", + name, current_accel_name()); + } +} + +static void prop_add_stub_bool(Object *obj, const char *name) +{ + object_property_add(obj, name, "bool", prop_bool_get_false, + prop_bool_set_false, NULL, NULL); +} + static bool cpu_arm_get_sve(Object *obj, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -309,12 +333,6 @@ static bool cpu_arm_get_sve(Object *obj, Error **errp) static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); - - if (value && kvm_enabled() && !kvm_arm_sve_supported()) { - error_setg(errp, "'sve' feature not supported by KVM on this host"= ); - return; - } - FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR0, SVE, value); } =20 @@ -471,7 +489,23 @@ void aarch64_add_sve_properties(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); uint32_t vq; =20 - object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); + /* + * For hw virtualization, we have already probed the set of vector + * lengths supported. If there are none, the host doesn't support + * SVE at all. In which case we register a stub property, to allow + * -cpu max,sve=3Doff + * to always be valid. + * + * For TCG, this function is only called for cpu models which + * support SVE. The error message in the stub is written + * assuming host virtualiation is being used. + */ + if (cpu->sve_vq.supported) { + object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_= sve); + } else { + assert(!tcg_enabled()); + prop_add_stub_bool(obj, "sve"); + } =20 for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { char name[8]; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index fa80e48d2b..84857fb706 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -524,10 +524,10 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->gic_pribits =3D 5; =20 /* The A64FX supports only 128, 256 and 512 bit vector lengths */ - aarch64_add_sve_properties(obj); cpu->sve_vq.supported =3D (1 << 0) /* 128bit */ | (1 << 1) /* 256bit */ | (1 << 3); /* 512bit */ + aarch64_add_sve_properties(obj); =20 cpu->isar.reset_pmcr_el0 =3D 0x46014040; =20 --=20 2.43.0