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Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8921 Received-SPF: permerror client-ip=2a01:111:f403:c107::1; envelope-from=skolothumtho@nvidia.com; helo=PH8PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103466154158500 Install an event handler on the CMDQV vEVENTQ fd to read and propagate host received CMDQV errors to the guest. The handler runs in QEMU=E2=80=99s main loop, using a non-blocking fd regis= tered via qemu_set_fd_handler(). Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 58 +++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 3 +++ 2 files changed, 61 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 8cde459b4f..99b85e698f 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -9,8 +9,10 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "trace.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/core/irq.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 @@ -487,6 +489,43 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr = offset, uint64_t value, } } =20 +static void tegra241_cmdqv_event_read(void *opaque) +{ + Tegra241CMDQV *cmdqv =3D opaque; + IOMMUFDVeventq *veventq =3D cmdqv->veventq; + struct { + struct iommufd_vevent_header hdr; + struct iommu_vevent_tegra241_cmdqv vevent; + } buf; + Error *local_err; + + if (!smmuv3_accel_event_read_validate(veventq, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQ= V, + &buf, sizeof(buf), &local_err)) { + warn_report_err_once(local_err); + return; + } + + if (buf.vevent.lvcmdq_err_map[0] || buf.vevent.lvcmdq_err_map[1]) { + cmdqv->vintf_cmdq_err_map[0] =3D + buf.vevent.lvcmdq_err_map[0] & 0xffffffff; + cmdqv->vintf_cmdq_err_map[1] =3D + (buf.vevent.lvcmdq_err_map[0] >> 32) & 0xffffffff; + cmdqv->vintf_cmdq_err_map[2] =3D + buf.vevent.lvcmdq_err_map[1] & 0xffffffff; + cmdqv->vintf_cmdq_err_map[3] =3D + (buf.vevent.lvcmdq_err_map[1] >> 32) & 0xffffffff; + for (int i =3D 0; i < 4; i++) { + cmdqv->cmdq_err_map[i] =3D cmdqv->vintf_cmdq_err_map[i]; + } + cmdqv->vi_err_map[0] |=3D 0x1; + qemu_irq_pulse(cmdqv->irq); + trace_tegra241_cmdqv_err_map( + cmdqv->vintf_cmdq_err_map[3], cmdqv->vintf_cmdq_err_map[2], + cmdqv->vintf_cmdq_err_map[1], cmdqv->vintf_cmdq_err_map[0]); + } +} + static void tegra241_cmdqv_free_veventq(SMMUv3State *s) { SMMUv3AccelState *accel =3D s->s_accel; @@ -496,6 +535,7 @@ static void tegra241_cmdqv_free_veventq(SMMUv3State *s) if (!veventq) { return; } + qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL); close(veventq->veventq_fd); iommufd_backend_free_id(veventq->viommu->iommufd, veventq->veventq_id); g_free(veventq); @@ -510,6 +550,7 @@ static bool tegra241_cmdqv_alloc_veventq(SMMUv3State *s= , Error **errp) IOMMUFDVeventq *veventq; uint32_t veventq_id; uint32_t veventq_fd; + int flags; =20 if (cmdqv->veventq) { return true; @@ -523,13 +564,30 @@ static bool tegra241_cmdqv_alloc_veventq(SMMUv3State = *s, Error **errp) return false; } =20 + flags =3D fcntl(veventq_fd, F_GETFL); + if (flags < 0) { + error_setg(errp, "Failed to get flags for vEVENTQ fd"); + goto free_veventq; + } + if (fcntl(veventq_fd, F_SETFL, O_NONBLOCK | flags) < 0) { + error_setg(errp, "Failed to set O_NONBLOCK on vEVENTQ fd"); + goto free_veventq; + } + veventq =3D g_new(IOMMUFDVeventq, 1); veventq->veventq_id =3D veventq_id; veventq->veventq_fd =3D veventq_fd; veventq->viommu =3D accel->viommu; cmdqv->veventq =3D veventq; =20 + /* Set up event handler for veventq fd */ + qemu_set_fd_handler(veventq_fd, tegra241_cmdqv_event_read, NULL, cmdqv= ); return true; + +free_veventq: + close(veventq_fd); + iommufd_backend_free_id(viommu->iommufd, veventq_id); + return false; } =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 3457536fb0..76bda0efef 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -72,6 +72,9 @@ smmuv3_accel_unset_iommu_device(int devfn, uint32_t devid= ) "devfn=3D0x%x (idev dev smmuv3_accel_translate_ste(uint32_t vsid, uint32_t hwpt_id, uint64_t ste_1= , uint64_t ste_0) "vSID=3D0x%x hwpt_id=3D0x%x ste=3D%"PRIx64":%"PRIx64 smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_i= d) "vSID=3D0x%x ste type=3D%s hwpt_id=3D0x%x" =20 +# tegra241-cmdqv +tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" --=20 2.43.0