From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103176; cv=pass; d=zohomail.com; s=zohoarc; b=iEZ5AqebOAVCcmdHtqDPz8bSTbbGOsH64gZONXu9tPfUsBZKi7flDnYn4ZzV7c7eNHUGMAdzqm07h5VCFnLuCLXFW2B6YPeZyeHwMo73dq52ZD7imYnCqrkKDkZRuRzc9s6yaZBqwZoVc8o6DqbJ9sHT8GlYIpIrkNDImF0GZF4= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103176; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+ONLCUQq6/niJ1wZevZA1o31zgACYvo7hNkXNtpPUJ8=; b=BQxCiHKWD0JgGmkj9rnQg47cZwfyYpMl6do/J2BkOZsAcN/lUkblwq6xctvOxVMYuPGo9Bnx8fa/9tYNJCR3CjjkSYLa/8JVgV4mz3PaZqTKA370rZSTKxsX1hm7CuEcMjwVOHPY08HKjya0vUBnBv3o2rhwDIUC9o73gzi7YSg= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103176563364.53943475759297; Thu, 26 Feb 2026 02:52:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYyG-0003uD-TM; Thu, 26 Feb 2026 05:51:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyF-0003tu-MX; Thu, 26 Feb 2026 05:51:51 -0500 Received: from mail-eastusazlp17011000f.outbound.protection.outlook.com ([2a01:111:f403:c100::f] helo=BL2PR02CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyE-0000eI-56; Thu, 26 Feb 2026 05:51:51 -0500 Received: from DM6PR07CA0113.namprd07.prod.outlook.com (2603:10b6:5:330::16) by LV2PR12MB5966.namprd12.prod.outlook.com (2603:10b6:408:171::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.11; Thu, 26 Feb 2026 10:51:42 +0000 Received: from DM2PEPF00003FC8.namprd04.prod.outlook.com (2603:10b6:5:330:cafe::a3) by DM6PR07CA0113.outlook.office365.com (2603:10b6:5:330::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:51:44 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC8.mail.protection.outlook.com (10.167.23.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:51:42 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:28 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:25 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ZNra6h9dOK3mpHlI5U2qqSkb6zJaTCh2PmOCHTQ+6SF6x6U4yAdmsUQm5MQhOorEUO2dKQ8Lp/kTs2q+wcgonIxaNax0+4ccOQJB85uyiULKmfQdXZ7eLcrQjFN0qRuO3gboW4GEO6yx0R+jdhGteZkv+9SFPs7HrVaRg5dlaD9DFmJC+E91j1NJT3G746QttnwnNpe5k6vT/3Q1CXz/bMzidfpPNm8fqhSyhLykfsRDeu9tOcrALSUp5yUCuBD2D+5ZhNUe7W6SeeZ1nV7ThXUh6mLJBUgqlJb4zSLMfUqIuHq5Few9KCFCN4ftO2aSmgaHkmdfT0kxACPcgSL5+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+ONLCUQq6/niJ1wZevZA1o31zgACYvo7hNkXNtpPUJ8=; b=Nu4leG+sfXhC0DJrXjL/Gx0uKegQS3/nkdSX9V9AngqTTgQCXsLyCKJWeUoqiHpzoCjJTcxPKLb01iGdGGIUS8TGgPxkcb6tGloPB68nEnvDryu5DndaM9DdDil3FsCiNICn6OKjrq/dBuY2JqMkioNmxQFzdIv7ipEBhBjX1r6Djefy0+9C7WZjl+YG5rHjSL7sX6CrrIaoNhG+p7DXBdSUIIscPHZ4nXKJ6fN6AHMv+7a6lLsU2vek6bSrLhSzAwgfXjj0kCGnS7gK2nK+NA4lf9KemE+YePGuCvbtEGWbVvbdWIDIWDBu+UCr6bBMZjmivm4da0Sf9bcnGRDX7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+ONLCUQq6/niJ1wZevZA1o31zgACYvo7hNkXNtpPUJ8=; b=au4wyf5GXSAWlzOM8PjYgSN0sr9z7Fyi5mJhUnOyGaV2DDfiJ5MFuLQou2K/9GW/u8DLW1Pn6qbIyiCxEgmP0bJoKAZ40iqvm3AhJ43jkDms9y15YgmhMQ2MJgi/R6eaRFAScO+JiOpUlbTql6EABN4rhUBff0H73sQw6AdaQiW2t2Mj+erEpMqJmvmf6Gvv2BEwTmye5TXEYWKvFvI4msfpad8RT3mT+KpQZ6KL+eUE+NsgcTWfmtbhxFDpXYTCA0yTSxYCNPzrSPjG/Uy20elKc1FeDaPk0mB7EeZ+nr+uPihvyetly9QnRzIIW4MiaxY1/Vz6gY399s+Qx0Z4GQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 01/32] backends/iommufd: Update iommufd_backend_get_device_info Date: Thu, 26 Feb 2026 10:50:25 +0000 Message-ID: <20260226105056.897-2-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC8:EE_|LV2PR12MB5966:EE_ X-MS-Office365-Filtering-Correlation-Id: 07c9f858-11db-4a54-1596-08de75250726 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: 8xLwQ1fkY/AtkRFVaAr+nAwxKDYTQZlz6moqfBxYK1c1OSPjFdDnHxUkKce3Sn6AcoVB6pmJr+5t56eWTU3ZhnKyFBZ/wPkYe972/j6ur3V7g5ouuX/wF5pe9lvI/iIEnoToHUFs8ZsWNCxOQrlrrbLK0ZmSoNAqgILldOIJDPDgyGKootrAjvorxZoW6JI2MGQ3BvfAVcfmV0HUuzb1TgNykj4TJGNkTPrr5xURueo43PsgB2nTfZDw2ptPXFHfeE0y6Psig01UJ8BczLcdy6ZJqX2pI/67ebPAxGFt+VfZoNno7ZFjnUjmUAeSWdKyEBN4uq8KYAcP32Khaw24HlpNF80/F/XeP0srZ4e8a/6mJkr0gfVdNct/hLFuLMjCll/1unOmCZHsRbh3za1iq3IB2msbrvNe5YUdgfNRoRgvhT67FdnyV3U4EvmDUUgYlqxTWN+76bj3GmhRFVpJhkdCb3f2eIPtHjVRNRhZQGMt/h15qTDQXDxzz2kkzgfa1rtWjbWY1U3vD3tiMFRBGfPG8ZxpBhMHuvNSiFVAqZmkB2R2tOJkwJwcwijqx11iDOBfB1WJfDHnpuqa7C80bvYqJXj7XgqTauMKrMsvhXqhN/Lg4l5nb42npCbLfNumwy5HdBYRMD9KieznuMHd6WaqsKxsZkMDHye5Uk9b93ovPOWpGotIMX6d2TKyRf5yVd79hU9noN3ta59Z7QSqApSq042pQtZs2Ebq0gmqzPecQkh0w+1X9z04YmrwAj55UIT2zKJ9iFqoTFlZiKA+OVl7Xu2y9RVRD0aM+a197qHG4Hsz7IwjGnIPSiD7XRc8SbL1hQ3mz2yxW3zvbzlLVA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: uWJqoYURJm/UnKLg1UEVYlooh/+I76FkKm57SUf+ZvQmVeBR6iWDK2VtOrrQDO+0TfO+5MqDoorxmA3u0S1xEjKF3kf7BJ/gLivwLP6IkLgmG2L7X8+4qDTO4gjKTIChMhMzwHrG381nxXn9k88NAtubTyqUaoSXD60HM1257oErJvf76v9vWxGcXoAdGfygCQRx2xiAYNyQ1N0H/uB00K0L1ABuEuFI92uFkz3GnRStrhOl5yW5rw2SiqMS3zuLqv83URR+fxnnjve8uiqRfRLfhdPetoXzONCT+pkNs2lSN21YLOSqmotvvmPuY0qvbX8WR65LYpFpRLnZyC0EO3u3faI90prk8tcs1tlst/oLHrpsz9XetBJ87TApoMzRMnZ9tYDnrTNpuG9lPUzK6DrRkGOJ95ZhDyWMtXdL1lrj7oe6txCk66Aq0XJW0lt9 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:51:42.5744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07c9f858-11db-4a54-1596-08de75250726 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5966 Received-SPF: permerror client-ip=2a01:111:f403:c100::f; envelope-from=skolothumtho@nvidia.com; helo=BL2PR02CU003.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103176913158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen The updated IOMMUFD uAPI introduces the ability for userspace to request a specific hardware info data type via IOMMU_GET_HW_INFO. Update iommufd_backend_get_device_info() to set IOMMU_HW_INFO_FLAG_INPUT_TYPE when a non-zero type is supplied, and adjust all callers to pass a type value explicitly initialised to zero (IOMMU_HW_INFO_TYPE_DEFAULT) when no specific type is requested. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- backends/iommufd.c | 7 +++++++ hw/arm/smmuv3-accel.c | 2 +- hw/vfio/iommufd.c | 4 ++-- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/backends/iommufd.c b/backends/iommufd.c index acfab907c0..5daefe505e 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -387,16 +387,23 @@ bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend = *be, return true; } =20 +/* + * @type can carry a desired HW info type defined in the uapi headers. If = caller + * doesn't have one, indicating it wants the default type, then @type shou= ld be + * zeroed (i.e. IOMMU_HW_INFO_TYPE_DEFAULT). + */ bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid, uint32_t *type, void *data, uint32_t = len, uint64_t *caps, uint8_t *max_pasid_lo= g2, Error **errp) { struct iommu_hw_info info =3D { + .flags =3D (*type) ? IOMMU_HW_INFO_FLAG_INPUT_TYPE : 0, .size =3D sizeof(info), .dev_id =3D devid, .data_len =3D len, .data_uptr =3D (uintptr_t)data, + .in_data_type =3D *type, }; =20 if (ioctl(be->fd, IOMMU_GET_HW_INFO, &info)) { diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index f2fd926160..2c4228b7bd 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -127,7 +127,7 @@ smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDev= iceIOMMUFD *idev, Error **errp) { struct iommu_hw_info_arm_smmuv3 info; - uint32_t data_type; + uint32_t data_type =3D IOMMU_HW_INFO_TYPE_DEFAULT; uint64_t caps; =20 if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 131612eb83..3854f8b9fd 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -349,7 +349,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, ERRP_GUARD(); IOMMUFDBackend *iommufd =3D vbasedev->iommufd; VFIOContainer *bcontainer =3D VFIO_IOMMU(container); - uint32_t type, flags =3D 0; + uint32_t type =3D IOMMU_HW_INFO_TYPE_DEFAULT, flags =3D 0; uint64_t hw_caps; VendorCaps caps; VFIOIOASHwpt *hwpt; @@ -938,7 +938,7 @@ static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *= hiod, void *opaque, HostIOMMUDeviceIOMMUFD *idev; HostIOMMUDeviceCaps *caps =3D &hiod->caps; VendorCaps *vendor_caps =3D &caps->vendor_caps; - enum iommu_hw_info_type type; + uint32_t type =3D IOMMU_HW_INFO_TYPE_DEFAULT; uint8_t max_pasid_log2; uint64_t hw_caps; =20 --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103464; cv=pass; d=zohomail.com; s=zohoarc; b=W5L9SSB+9jl0xsvmDIipqM8W3qe/YpN8HOLbiSWC22i8T1IAR189O1Bt/zDZWNLambqGF+yglz8q0ziBKt/dTHRSXIwmyhw5vZrWxrSBYmcBDYf7nsyWoOZNONwDT8142LdtbTmofWf9Yune4mYCS2TOovBrCWRQoFAsLqRwADY= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103464; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4QPCro/BMPpVMIt9J5MQcjWLKO4Ir/6GgdQ/3tmy7+E=; b=iof/GGh/9XbMDh3YIpJS8H3+CMxwN+UpJede68k4WvqjzhQ/j0dQcsG3p2+HR7NFPrlRm9MqWLlCkT8v5EAbCWVbyzjCdVJ9LHUei7f0TLt+TC0kZw7XBTGFp38kQoiAQFsxyNG40bwMSLRhE+qvkKVSnZXKDja4yzh5srCXpy8= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177210346402873.2446508911188; Thu, 26 Feb 2026 02:57:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYyX-0004Cy-87; Thu, 26 Feb 2026 05:52:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyV-0004Bc-Bz; Thu, 26 Feb 2026 05:52:07 -0500 Received: from mail-westus2azlp170100005.outbound.protection.outlook.com ([2a01:111:f403:c005::5] helo=CO1PR03CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyT-0000h0-PE; Thu, 26 Feb 2026 05:52:07 -0500 Received: from SA1P222CA0115.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c5::24) by CY1PR12MB9604.namprd12.prod.outlook.com (2603:10b6:930:108::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.13; Thu, 26 Feb 2026 10:51:56 +0000 Received: from SN1PEPF000397AF.namprd05.prod.outlook.com (2603:10b6:806:3c5:cafe::78) by SA1P222CA0115.outlook.office365.com (2603:10b6:806:3c5::24) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:51:56 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397AF.mail.protection.outlook.com (10.167.248.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:51:55 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:32 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:29 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=nh24uY7/SXE/879/JjamxwCoQnIZwKKFIMMQj19gIkbvPftONx0ey0+Q9H+jObTxvPxCR5GiXCZkwli2xjb9BxjOUIKg7iCAer/1R1Y2P5INYG4VKJZVCRz2ga/8htoXGNEmXtxzc4RvSZSHa6jNL33PYE9xivANl3oKWBkqR9cYYQt/GYDK1RFEhSpj/zVmKwupOtyzKV3DEGfxdAd4Vac92X6PssoZjjxbO80rBJ1G75wcc5FF5XtP5ovEllgR/Mi6yI3r543Atrw62CZIsOF4vRPbc9dhr77vRtuyl4j/X580gx5xsT7Hd3nRqImcuXEGIkbwViOYjpWkFrTNKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4QPCro/BMPpVMIt9J5MQcjWLKO4Ir/6GgdQ/3tmy7+E=; b=QhX2tck3LvSevWSgKjfII5uDvjJW0AQuqXl5P7mQgBkAN/LYmJcNuDxJKVHWI9z2SZyqo6xw/12DxruPrnGBnDjw2I5GuTiNWJawgFaAKEJIKRR4Wb2qDhBZ1Yz0qjIxzXBl/wNfXFMkoSxlBGLd+khpCw3Ca4Q71YdIepYrUa858HHzLBTMiXXSvHRIQqyzT9YaZqIoWFdfvyeVKZw//WnaB8rrURlsQOCmetGbmXRGjkhPzu66iFu373knhqb+sMCiEg271jNkqPPbUs7Lwv+2i6viXN8FGThrPNVbQaOetoPtY4f9zRkvv1oO8/smUt0RtBBjK62OPiLrOUxksw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4QPCro/BMPpVMIt9J5MQcjWLKO4Ir/6GgdQ/3tmy7+E=; b=YnJEoo+pRE3H0Gwxl4q+2upTj8WF2cp5raZvAJCVxfZhx0ENLnkjGvzxq1upzpun1EoJzKMc2pNOwUUX9hr7WzO49qj2fMdORk5NLogbdlPdiw0YJc6gdyUvg3bY3SfnYOZkqhLhvfl+TIhrIotG/+tVbI+1QCmU4fOTYuAjwOeVERwFn3Mr9QPf9yOjk6CagXWevVtJ0EaNG9gSQysuzrcQRiaHz0YyYHj3yzhOu3/k9ZA2DMuAtzVyhtWLujRPLNUlMUqcHpqO6U7WrRXxOsKbc+EgqCN3s4iVhLXKXUfpCECxWLssIO5BScPwmAmuEAZjQUwdU162fwjTMShnlw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 02/32] backends/iommufd: Update iommufd_backend_alloc_viommu to allow user ptr Date: Thu, 26 Feb 2026 10:50:26 +0000 Message-ID: <20260226105056.897-3-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|CY1PR12MB9604:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c24e5d4-afec-4206-31c2-08de75250ef8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|376014|7416014|82310400026; X-Microsoft-Antispam-Message-Info: f70oVBjFpuJXSZg9dGs81DdR7oYuHTBYxdPReSuw/xO/E048XVtCW7iNy4S9vtYbSh3bweLiIgrGJA+wu+3k745+XaBV60F/nxh1fwFjxwVF6OT2+4Oa+kyHvtm9WCg4N9cTPABe2FG6ISlF7P4+AQMZ9PA+REWfCrL3IK/+WjU96W2pg1lfxb65+4p218sEMdLG2YUkkAYSnovjIFiZLvdtRWO/PyvSrwz/2E+7rpKXG9F1TbotjRIPQOQpXOqV+vbm4j2KkQ+VPOo31MD2XsCq8F4jiObSWJ6el6Z64IXJfNzr0mvKspSC7In9en756F3z/VeeNs8WTtCb0WaP84H+C1jBVhAp7/hRj7eEHSp12uVeusZHeF1c133zYMfW9oIBbNm6sMhzqqBffi6E7U6IgZ3cfxcSgQ3dmSBD2BRfD8srt2y8+tXAKtGVnMYaufmK1vfpAoz8GURQA5cvbPUvGQyTaKNPTCHIfyUdSM5O9K2xX6zgKy3XictTYqaau1m49bSs0MnysZvLFo4+EbAd1Mvb+aKKm2OkhNYBaxFjKv97nZMVUcw6FwDOLq3NLl1D3aMdGq4GexP9xNsObbx3F+pwIS2jGNdviwk+WKmRXspKiOE7WT5eFO0RwZzq0KOpRmkc7NRA5k2jLEirc99QoPNhdBNqN8Vqm0paTDV8KwIGtZmQnw6p1qGLj5B8cyE5bYqVNMXhYdaY17xRlMyImfzzL9OLK+fXZ7wI6LIVQtXZ4UhtFfbJUlZaqyRqyKJxni8zTnjFqUQXvvcjdjJaWWagOvr6gcFFA+vCofRJn/0M8/3ptJksd8wi4RVs7sgntj0UPFVLsi3Z4ox8Hg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(7416014)(82310400026); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qqwzCH8jq6StyQwFMNR8q7ChVBj9a+DckPgkyd3Z9XxzVVmW4lc0dP33SvWzIgJ1G9LsiOKHQ7LZrWu3d90kvaHK9KsP9kbcMh2cYCXkoLlQp9LZiSkcZjW4Dxlbwr1a1oq3gP5WqsmkqwaE11QilUxEFqv5sfg3Akj0fgv7CieOktAsgZt9IgPIT872i7ekjMaVMVSsQ09jfqEX2Jl/Of3c+5iZ52wscUcWd9sKZEy7vGcnGDgkigFrAvGpI/ikKn8z9Qjb8s6IvVndGG8Mbrr8MCCjwPeeVbHswO1mDCqYg/FaWFxVbrXX7VRYIEy5v45ld0KNAdgNxI0QjhYPLMK9cJsYrjHssi6pOLPc/TS1FjsyeEaa0Al/URgC8mhe44u8lbkk7l+gHf6O7l9LM3yWUuKSiFwW/yDNrSzWo1XpVyVHqxz7Otnix7fmUXOu X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:51:55.6460 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c24e5d4-afec-4206-31c2-08de75250ef8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9604 Received-SPF: permerror client-ip=2a01:111:f403:c005::5; envelope-from=skolothumtho@nvidia.com; helo=CO1PR03CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103466149158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen The updated IOMMUFD VIOMMU_ALLOC uAPI allows userspace to provide a data buffer when creating a vIOMMU (e.g. for Tegra241 CMDQV). Extend iommufd_backend_alloc_viommu() to pass a user pointer and size to the kernel. Update the caller accordingly. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 1 + backends/iommufd.c | 4 ++++ hw/arm/smmuv3-accel.c | 4 ++-- backends/trace-events | 2 +- 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 7062944fe6..e027800c91 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -89,6 +89,7 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint3= 2_t dev_id, Error **errp); bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, + void *data_ptr, uint32_t data_len, uint32_t *out_hwpt, Error **errp); =20 bool iommufd_backend_alloc_vdev(IOMMUFDBackend *be, uint32_t dev_id, diff --git a/backends/iommufd.c b/backends/iommufd.c index 5daefe505e..400946810d 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -460,6 +460,7 @@ bool iommufd_backend_invalidate_cache(IOMMUFDBackend *b= e, uint32_t id, =20 bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id, uint32_t viommu_type, uint32_t hwpt_id, + void *data_ptr, uint32_t data_len, uint32_t *out_viommu_id, Error **errp) { int ret; @@ -468,11 +469,14 @@ bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be,= uint32_t dev_id, .type =3D viommu_type, .dev_id =3D dev_id, .hwpt_id =3D hwpt_id, + .data_len =3D data_len, + .data_uptr =3D (uintptr_t)data_ptr, }; =20 ret =3D ioctl(be->fd, IOMMU_VIOMMU_ALLOC, &alloc_viommu); =20 trace_iommufd_backend_alloc_viommu(be->fd, dev_id, viommu_type, hwpt_i= d, + (uintptr_t)data_ptr, data_len, alloc_viommu.out_viommu_id, ret); if (ret) { error_setg_errno(errp, errno, "IOMMU_VIOMMU_ALLOC failed"); diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 2c4228b7bd..ab1b0a3669 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -533,8 +533,8 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *idev, IOMMUFDViommu *viommu; =20 if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, - IOMMU_VIOMMU_TYPE_ARM_SMMUV3, - s2_hwpt_id, &viommu_id, errp)) { + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwp= t_id, + NULL, 0, &viommu_id, errp)) { return false; } =20 diff --git a/backends/trace-events b/backends/trace-events index b9365113e7..3ba0c3503c 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -21,7 +21,7 @@ iommufd_backend_free_id(int iommufd, uint32_t id, int ret= ) " iommufd=3D%d id=3D%d (% iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int r= et) " iommufd=3D%d hwpt=3D%u enable=3D%d (%d)" iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t i= ova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) " iommufd= =3D%d hwpt=3D%u iova=3D0x%"PRIx64" size=3D0x%"PRIx64" flags=3D0x%"PRIx64" p= age_size=3D0x%"PRIx64" (%d)" iommufd_backend_invalidate_cache(int iommufd, uint32_t id, uint32_t data_t= ype, uint32_t entry_len, uint32_t entry_num, uint32_t done_num, uint64_t da= ta_ptr, int ret) " iommufd=3D%d id=3D%u data_type=3D%u entry_len=3D%u entry= _num=3D%u done_num=3D%u data_ptr=3D0x%"PRIx64" (%d)" -iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint32_t viommu_id, int ret) " iommufd=3D%d type=3D%u dev= _id=3D%u hwpt_id=3D%u viommu_id=3D%u (%d)" +iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id,= int ret) " iommufd=3D%d type=3D%u dev_id=3D%u hwpt_id=3D%u data_ptr=3D0x%"= PRIx64" data_len=3D0x%x viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" =20 --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103170; cv=pass; d=zohomail.com; s=zohoarc; b=Mi9UYy7ZOgORLOclMdobSgTtlJIySdufpELf4c1ONgzJY5abOOGd4feMZiABFCU1J/izYkjk71Vk1YEDs57HlJENmAJAmLXXU9DImTf2n1xlk8AY6Lat4R1HX6RmAf+NZimpRW+poSlUr0n2fVkgMPOUwvUeruGadcPsx7FDJko= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103170; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ACaQSioSOPbokIXX0NRiWo1dG3iORgakhTMOTeD4hnE=; b=S4J3/1mXLCIA5kiCG8lzM4hrwCaLKkKUn9Oensa3CrZoJcgAYGPdIR3DJijYzCUq7tMKVG9Ez0NCOCPKbpUgrUe+hpC79GVzglJxVjBtY1MJGm1Dx5A0RdaEOSM5lScDDbtPz77g4zqL+pmi3Z5l5F/ehK1ogPcAppccqDMVtJY= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103170451959.0519307141711; Thu, 26 Feb 2026 02:52:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYyQ-0003yX-CU; Thu, 26 Feb 2026 05:52:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyO-0003vj-N6; Thu, 26 Feb 2026 05:52:00 -0500 Received: from mail-eastus2azlp170100001.outbound.protection.outlook.com ([2a01:111:f403:c110::1] helo=BN1PR04CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyN-0000g4-5I; Thu, 26 Feb 2026 05:52:00 -0500 Received: from DM6PR07CA0107.namprd07.prod.outlook.com (2603:10b6:5:330::21) by DM4PR12MB8571.namprd12.prod.outlook.com (2603:10b6:8:187::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:51:50 +0000 Received: from DM2PEPF00003FC8.namprd04.prod.outlook.com (2603:10b6:5:330:cafe::c4) by DM6PR07CA0107.outlook.office365.com (2603:10b6:5:330::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:51:44 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC8.mail.protection.outlook.com (10.167.23.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:51:50 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:36 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:33 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=esE4LfSp2i5vr2fcePTzEiLPhIs5/NWnQ9HSnxzLa5j3HXXXlfql45XeXA1o3BYnoGYk9CHvQI6q7ffIWv3Lu/TDRo6IhktkOLHBzAKM+ZNvMJiEfWexatbHGsi2AeCk/s4SL+7s6SxoCErcrZZE4zFIwzUttdLJIO8DtUl0NpL3bG5qKiLIw0R/TqHIkNxKwtobCLve/3zjAnORCb0cWQ1TMe/0syG/Dy2WuzuZ3pGsPoV1nkAaO3iEQhcZmt/Z0DtIjHZNwJ8Wb4IkZgslHQCs98OscgVY5F0/h6D0/KLm2gNP1YSR28GYqfWD1mXTSCcntCbnIS/rX3xyjZjLTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ACaQSioSOPbokIXX0NRiWo1dG3iORgakhTMOTeD4hnE=; b=vPJZSHzvowNxiBdgrzu47X0rFLJljTpNZiaoHe/CcLq1dwkm3sZ/B59A0HrzOHl2Wf+LUz2TYTOHTBLqRUj0DWZZIxf5HGrfoihMuvgAOehyjRhSlhQnzpMzgudrdtOqDyxSSC0rbExwJNIPZziRfYlxLYx+Ck2xMLSLW/TyugWSfqTuBqxS28GAr1PxoQdKFqcVVehmE7NvqqKJ0p4J3qeqPGnBDo8b4t0Fo+WE6g5fDFl2S6gYsgUeNHt8BaCiBcs9CyeCpj0GENki0kg/r3kU3nQaCd+/TECWn+iazS8VO9fTBq5op1UIF7fUQWfXaXr/e8w5tqZqJIIPpV5PBg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ACaQSioSOPbokIXX0NRiWo1dG3iORgakhTMOTeD4hnE=; b=nQikfHgFTaqEXGZyMZ53DAwYWeJTJiCNUhJ21QU4vMLHdzHAHsJD3bgyRAWweqlrwde/vSX199Ld+RvXcJtRD2pDLQbl8R3AL1w5k5tE2h5FrJP7zjZZJGMvh2DTCmYLjMjegVJV/Yge8jywmI1Ybk75VL8FsCe/sKrYRq9T4jOBjAcI3F8aApAx3qX1Wm1JdMZogEg/3deouY59nxwBvOgWcwxxKAfHRoYfmCCF7mb4hTkypHSV7/QW6VOFNsQ7DwpuLarjfu84Ft8ttZ9RRk9OI3mnVVM9P4RqyV0oQ3E4Qxv3ppQagBNIsj07x2AkPAlvpcG041u8jW2Op44WlQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 03/32] backends/iommufd: Introduce iommufd_backend_alloc_hw_queue Date: Thu, 26 Feb 2026 10:50:27 +0000 Message-ID: <20260226105056.897-4-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC8:EE_|DM4PR12MB8571:EE_ X-MS-Office365-Filtering-Correlation-Id: 66e871eb-4d2c-4224-4ece-08de75250bd8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: Bq56ir3lw350zydWC8vqaPdbEe/VASeLxfynzHUPgdoTdfZBTvqogRFAUmemzzpKeuSVmao8eBiLLCxyrmidKeWmERZPLwcfzYaQJvynCEfbHqWTXLTCvkfjPUiGcWXkkeyWa85imHYF3o0KGFgFvDTLhQN0pjncZQa0o2+1VouDNqylaP7dpAEq3CwE9T0hlEeyIBFjx4W1xg0rfDnfWnwwGGMJOKKNoUj7RiCX8hsSAr52Egr81t9Dd2JDA9P+P7JM+2fZ4N/LLxcr8LJTDoJeWpnCmYHIrK/21r3In8fQryZolmIGReJzFtU5LmS+Y0HdN7/RNY2bpwhiPxcY6ssccQFJEHBunP1y1t1H/ykVBJnaqIrZyfgOfbYz/GrWuA34EPJNh57p5bl+ha6wD/RG+9siQ4wkp/217PkItzACBxCG/qW7mpT4Ee9aGUqizpOvdbHeL5qwmqw3N1ZemXvNzde4t6Q8SgYIeVROps2eJVSOFhkPuCpZoohZdTCsTzi23hwKEBbClp1sl5AgKa+hXcEflAWcmaNAvjXspEIxA5JJqGnrlUlV59bIlPAhciHkI0c2uJPgadDsXZidju8qBSJAf+nKtBCSdZ+B8mcG/7Dz6GaD5A04lO6rcpSHy0a6IOSFPpPSkl2c29p9MATZV/CBpNGcpXHw4mJEc6GUXUbK+s4tjkvkhf50DpKy8s0r35kyseamu9LuSw5k1rvme8h03u7dUv7pn2meYFif+tRXvHYs986oc1fqCneRyv9pPRemh4tt8S1qxcAILzyh4SunBDWUjDFWJWrFmDwisIA6Lj1kRO2k7nzMxfMkDLKLZUFXI6k8N/Wy6FpBFQ== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(1800799024)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xp8rU9Wvdk9l4KaFisRuV2VAIzzVQaFVZIpG+R6x7TtRYEgy1Pe8Vy7xH6diVCRREN/o/gd4qeNpPyM0uQdrz5gm43AaTSIOft57kd8dXwTA9DcisUJ5sb6g16EYu4n3U7lhXnUdDNhj+LSiyd0zRmc2CblT1kzJNqzAvR6uzWFbX8ytvRqtY3dDQTQaOfvsymZWrnLYRH5V2v3ZtWQfX4agNiR74TkLN88qXP0OL9jDEzwJVdiHHe8z7SAKLF10odODf3hfz477Se1g5KUF/jVU3u7kp/6PMmWXvdHeF7wiT47F/i7nx/y06vjWQa1kUFFO/Lx5s2AfSoiwLTUROlFyYT5pFL5kIFx1SC6z3e3padnAfQuEk2Y00XkyNcPAnDxPYHqUvdyFMQSGX5vMr1f0qGzdJeKjoQP7+WC8juYm1/mR7UP7wbbsD9b+GyQb X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:51:50.4021 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66e871eb-4d2c-4224-4ece-08de75250bd8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8571 Received-SPF: permerror client-ip=2a01:111:f403:c110::1; envelope-from=skolothumtho@nvidia.com; helo=BN1PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103170800158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a helper to allocate an iommufd backed HW queue for a vIOMMU. While at it, define a struct IOMMUFDHWqueue for use by vendor implementations. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 11 +++++++++++ backends/iommufd.c | 31 +++++++++++++++++++++++++++++++ backends/trace-events | 1 + 3 files changed, 43 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index e027800c91..8009ce3d31 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -65,6 +65,12 @@ typedef struct IOMMUFDVeventq { bool event_start; /* True after first valid event; cleared on overflow= */ } IOMMUFDVeventq; =20 +/* HW queue object for a vIOMMU-specific HW-accelerated queue */ +typedef struct IOMMUFDHWqueue { + IOMMUFDViommu *viommu; + uint32_t hw_queue_id; +} IOMMUFDHWqueue; + bool iommufd_backend_connect(IOMMUFDBackend *be, Error **errp); void iommufd_backend_disconnect(IOMMUFDBackend *be); =20 @@ -101,6 +107,11 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, uint32_t *out_veventq_id, uint32_t *out_veventq_fd, Error **errp); =20 +bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, + uint32_t queue_type, uint32_t index, + uint64_t addr, uint64_t length, + uint32_t *out_hw_queue_id, Error **err= p); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, diff --git a/backends/iommufd.c b/backends/iommufd.c index 400946810d..86f9c9f4cc 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -546,6 +546,37 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be,= uint32_t viommu_id, return true; } =20 +bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be, uint32_t viommu_id, + uint32_t queue_type, uint32_t index, + uint64_t addr, uint64_t length, + uint32_t *out_hw_queue_id, Error **err= p) +{ + int ret; + struct iommu_hw_queue_alloc alloc_hw_queue =3D { + .size =3D sizeof(alloc_hw_queue), + .flags =3D 0, + .viommu_id =3D viommu_id, + .type =3D queue_type, + .index =3D index, + .nesting_parent_iova =3D addr, + .length =3D length, + }; + + ret =3D ioctl(be->fd, IOMMU_HW_QUEUE_ALLOC, &alloc_hw_queue); + + trace_iommufd_backend_alloc_hw_queue(be->fd, viommu_id, queue_type, + index, addr, length, + alloc_hw_queue.out_hw_queue_id, r= et); + if (ret) { + error_setg_errno(errp, errno, "IOMMU_HW_QUEUE_ALLOC failed"); + return false; + } + + g_assert(out_hw_queue_id); + *out_hw_queue_id =3D alloc_hw_queue.out_hw_queue_id; + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index 3ba0c3503c..c5c1d95aad 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -24,6 +24,7 @@ iommufd_backend_invalidate_cache(int iommufd, uint32_t id= , uint32_t data_type, u iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id, uint32_t type, = uint32_t hwpt_id, uint64_t data_ptr, uint32_t data_len, uint32_t viommu_id,= int ret) " iommufd=3D%d type=3D%u dev_id=3D%u hwpt_id=3D%u data_ptr=3D0x%"= PRIx64" data_len=3D0x%x viommu_id=3D%u (%d)" iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" +iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t q= ueue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id,= int ret) " iommufd=3D%d viommu_id=3D%u queue_type=3D%u index=3D%u addr=3D0= x%"PRIx64" size=3D0x%"PRIx64" queue_id=3D%u (%d)" =20 # igvm-cfg.c igvm_reset_enter(int type) "type=3D%u" --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103357; cv=pass; d=zohomail.com; s=zohoarc; b=lls1cAfaTQaWA0d2k+ThrZ0EFLB7yRpo/rLxB71YG59PQrM9Ai616JG7pPFJm0qIueBDhMyHxXAeftK2aROe5uK53lsfth2KrrTTCHR2zsiapJ9vt8MraGRLNrwwf+fT12L6Io8SV3vuWUSbLQ+UEhLnuzkGAnY30GDovVNdkU4= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103357; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=u8Qa0PpBzFZ84WCU9yjH4j6AI0mxwnw4XDBCA1bGV6Y=; b=IcmTzosPA+ZUPUkdwYIawtihgdGown8S+wZ1+5tNefeNQQGYEpgfEk4ZkdksPdcvLv6QAPdrR5bfJsXSQicGZUHUe7kldSTce6zGmx5D8A+SnM/Td7KLXaUInCgLVzG7PSloMI1M/8qyYZHs60FBlJql8J4RjrBtYUXs/u83Mio= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103357968909.5404913566148; Thu, 26 Feb 2026 02:55:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYyb-0004Ec-4g; Thu, 26 Feb 2026 05:52:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyZ-0004Dd-9c; Thu, 26 Feb 2026 05:52:11 -0500 Received: from mail-eastusazlp17011000f.outbound.protection.outlook.com ([2a01:111:f403:c100::f] helo=BL2PR02CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyX-0000hd-RA; Thu, 26 Feb 2026 05:52:11 -0500 Received: from PH7P220CA0124.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:327::27) by CY5PR12MB6154.namprd12.prod.outlook.com (2603:10b6:930:26::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.11; Thu, 26 Feb 2026 10:52:03 +0000 Received: from SN1PEPF000397B1.namprd05.prod.outlook.com (2603:10b6:510:327:cafe::93) by PH7P220CA0124.outlook.office365.com (2603:10b6:510:327::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.23 via Frontend Transport; Thu, 26 Feb 2026 10:52:02 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B1.mail.protection.outlook.com (10.167.248.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:02 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:40 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:36 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LGnOVw/uIP4XtrMsUEOTWainCZuhQ9rbjPmQjFhzkgOlgLKUHQ58iNbVh0b8RZWIGy9qYgKonGyhAgXAAENvss9TWWokeWipUwk0ko5ffG4xx6bhwVjlkfNyc3cfB31/k4KOFQkMhDHfg1SloxK4nB//jarbKzFGKwBgaEenlGhCsc7GG4bOzdixBWZs3vFRhVSgcBBoswZhPfuZqDnKcQ1MuL1tjA6ft+viBGWCht8IBGrE4tC0j4z3eHq8J+qjDM3rah97FbsbKpjdm2LEiW6HIgGkPtQYlS7HCXZVbTzBhqlh0uZFKrKTuwwbm2Vqgc17yKy9DfZY87GtHlJwLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=u8Qa0PpBzFZ84WCU9yjH4j6AI0mxwnw4XDBCA1bGV6Y=; b=m0ZEZyiOW28eZJkgZCDbmhoWatMthr22rFQS2ORNEVQyVEehwofmYdAKnQusP81ONXAKwHfk6sZOHHmorqMNJCiprxldZNXiHqdpYUlILtXxBPh/oleaLz2N4IPTOxkBJPONTBnAAMrdvhyTtMJFeVehEjLk1JH4jGmKcDXd/YW+GCtiBd9jwR38qt6qxuSxA610da6TgVxFGu2E/5CoF84x3ZSbYe1WT5qM9YTUgEPiAUchbZTMM5e2/PC+jQWqvcMxspuLS8aO74mtrzFDowRIr5hOjTlgljLZaS9FlkQ8vNWNzfUJxbtI36ueOEKjAHUp2Ud6ofugCFDz02M+rg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=u8Qa0PpBzFZ84WCU9yjH4j6AI0mxwnw4XDBCA1bGV6Y=; b=rOPankPZtM7OFjs5XO4s9efJ42It3RgSeCMtT+a/Wr2dq2UU6d63FWEj8ci97bsMNht8sFaoiwHUOJY5s6ieZgznN/85q6EDVroEcYnDvTfFoCFB3saJOVA3riOcH2MfcEAOnMaeQ0loNAPShPqX1/KUeJKGGPGjgQokRbbNWh/YZ9mlXr9P3y+FXxsHAZpZ1rxOZ573SovwpszrO8z3DhYm6S4YzaXLeyH5y8CTSr980PNV8v2ZbRjMYHwmQ//w67On3cnS/yHTWtYiE+mkYbUrZDAdhPcJzrEFVZtdNCz4Pd5dFTKd9UHnz0vHSJAiX2j0de/tJaOV9pU2BYROVw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 04/32] backends/iommufd: Introduce iommufd_backend_viommu_mmap Date: Thu, 26 Feb 2026 10:50:28 +0000 Message-ID: <20260226105056.897-5-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|CY5PR12MB6154:EE_ X-MS-Office365-Filtering-Correlation-Id: 6753a481-3942-4abc-9ed8-08de75251317 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|1800799024|82310400026|376014|7416014; X-Microsoft-Antispam-Message-Info: Wk552MIpNnCZWFSVH4jZQ24H/0rEjCUxMobRLU2iLHCVbcCDgOYalfq8OPbiGgTtqJAUzmvUCchsVAygLDx+ahB5drOUiJJRm/YFG5bxV7WUd3PCovyBnv0I9aLYdSWDwLvshCv2jKG/GdeIqEfNMgGhuFUWtVmvDrKfIV/M2O5S8UFSU3N+O8j9K6dNY0O5VyEDiR/0xpzStFsDNO2WqG0FOl0geuJG1BcPMnfZw4jJSlwhSJo9UP3gT4WyhnWCuYFbVza9wRJuDAzO0Xk2q8P21iKRjAFCjPIG3N+znLVV15rBoiBhVivTeoLPgodksfB6UHbTBSezlltXbkRDoK5LH+TCQ2uO2t2BAgcWYJM2AC9VQtOmKQoBUTwDp+4OfSHYZKWljrwIFBVmlsWxhWjn0CUeYsSuEaQgmDEGPloj4AwuRArX9PaBlk/ZaZObfL1aSVy7Al6aYKG9SBezlZZ5uUH9juloPGlFxglMazAGUcgDNk+C7rrrpwGAPyLY9aPArOtMSRuJxKHfhwy/rZa0FOJSwBs8rat5bmWSvfoeU90GpOxSod8otxT/Bfh4LiVKNPrgtDFFOoy0N0rbPl5v4ULBrX8ehvGMVfbTFRT+ihY/wtTPJe+LLhVXao5C283h7RLcO7HGFKcpllhdJaSRkTbe4AD60aXY1OtEERyoGm+5NuNY+65uG7+Cxcfcbntvsu+YQOSJuMP3JLMUdbzJ+1axFlC3lVmVPi91e42seWERq8KTJU373KPgBIfA1mtmj+w+Uvs916XiRNE5nxmd3aj8cK5YNxicDEPdeteGKWkOdmb+AvpTXswBeCVE X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: f/AjbsV90WqgNu1fx3a964MCysNAP4bAjBin8POPhewFsPBVN/mSd0AKHVXWgGJ43A1UCN21iEk6HNl/OAvWEgJqoO+PKMzm6ky2wBiDysKcvxCmf/jcW5WDgOvW2t7uWsWDnRPUKZZYyNgG6/sCcYyPPLmy+IUS3kt/V5Ozgha1sUwfa+jo/E1V10q2C9iVxmKg1kLFONzH4O2egcpB4hanhyye9puQKHrpNz9Nbmu3WPzKro195fgHmvr1+1w9PxtNvO1tX6PpY41EVb4O8azxtPUKYMq6au6GlCtSZ1b/Byo0CTg00hqpppQpDzjIw0HlLkcGLMxpvfmjjSKYnWWeVbvXytQ1R2RgZgF5CilHRg9o3oi+7qdp85OT62TpeE9gZ71OzpM8c4t2ZVuGnX8/6Il/kgRACZcCElSk10YvG/qP0zJSYeJArytdFMuk X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:02.5375 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6753a481-3942-4abc-9ed8-08de75251317 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6154 Received-SPF: permerror client-ip=2a01:111:f403:c100::f; envelope-from=skolothumtho@nvidia.com; helo=BL2PR02CU003.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103359652158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add a backend helper to mmap hardware MMIO regions exposed via iommufd for a vIOMMU instance. This allows user space to access HW-accelerated MMIO pages provided by the vIOMMU. The caller is responsible for unmapping the returned region. Signed-off-by: Nicolin Chen Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/iommufd.h | 4 ++++ backends/iommufd.c | 22 ++++++++++++++++++++++ backends/trace-events | 1 + 3 files changed, 27 insertions(+) diff --git a/include/system/iommufd.h b/include/system/iommufd.h index 8009ce3d31..38cfceca84 100644 --- a/include/system/iommufd.h +++ b/include/system/iommufd.h @@ -112,6 +112,10 @@ bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be= , uint32_t viommu_id, uint64_t addr, uint64_t length, uint32_t *out_hw_queue_id, Error **err= p); =20 +bool iommufd_backend_viommu_mmap(IOMMUFDBackend *be, uint32_t viommu_id, + uint64_t size, off_t offset, void **out_p= tr, + Error **errp); + bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_= id, bool start, Error **errp); bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id, diff --git a/backends/iommufd.c b/backends/iommufd.c index 86f9c9f4cc..6defdf6a52 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -577,6 +577,28 @@ bool iommufd_backend_alloc_hw_queue(IOMMUFDBackend *be= , uint32_t viommu_id, return true; } =20 +/* + * Helper to mmap HW MMIO regions exposed via iommufd for a vIOMMU instanc= e. + * The caller is responsible for unmapping the mapped region. + */ +bool iommufd_backend_viommu_mmap(IOMMUFDBackend *be, uint32_t viommu_id, + uint64_t size, off_t offset, void **out_p= tr, + Error **errp) +{ + g_assert(viommu_id); + g_assert(out_ptr); + + *out_ptr =3D mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, be->= fd, + offset); + trace_iommufd_backend_viommu_mmap(be->fd, viommu_id, size, offset); + if (*out_ptr =3D=3D MAP_FAILED) { + error_setg_errno(errp, errno, "IOMMUFD vIOMMU mmap failed"); + return false; + } + + return true; +} + bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id, Error **errp) { diff --git a/backends/trace-events b/backends/trace-events index c5c1d95aad..b63420b73e 100644 --- a/backends/trace-events +++ b/backends/trace-events @@ -25,6 +25,7 @@ iommufd_backend_alloc_viommu(int iommufd, uint32_t dev_id= , uint32_t type, uint32 iommufd_backend_alloc_vdev(int iommufd, uint32_t dev_id, uint32_t viommu_i= d, uint64_t virt_id, uint32_t vdev_id, int ret) " iommufd=3D%d dev_id=3D%u = viommu_id=3D%u virt_id=3D0x%"PRIx64" vdev_id=3D%u (%d)" iommufd_viommu_alloc_eventq(int iommufd, uint32_t viommu_id, uint32_t type= , uint32_t veventq_id, uint32_t veventq_fd, int ret) " iommufd=3D%d viommu_= id=3D%u type=3D%u veventq_id=3D%u veventq_fd=3D%u (%d)" iommufd_backend_alloc_hw_queue(int iommufd, uint32_t viommu_id, uint32_t q= ueue_type, uint32_t index, uint64_t addr, uint64_t size, uint32_t queue_id,= int ret) " iommufd=3D%d viommu_id=3D%u queue_type=3D%u index=3D%u addr=3D0= x%"PRIx64" size=3D0x%"PRIx64" queue_id=3D%u (%d)" +iommufd_backend_viommu_mmap(int iommufd, uint32_t viommu_id, uint64_t size= , uint64_t offset) " iommufd=3D%d viommu_id=3D%u size=3D0x%"PRIx64" offset= =3D0x%"PRIx64 =20 # igvm-cfg.c igvm_reset_enter(int type) "type=3D%u" --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103155; cv=pass; d=zohomail.com; s=zohoarc; b=EuVOV0T8BTdQs03AGEAbPnuk7xuPYbyWxBadd+ttXt32+lVsxUuYOcCyJd030MJNgBMVZlq2wDAf3S59dVkajUGFWSjeJELmwZGGNrJWK11+4Nbs26iUYI4MEUiP2Mdbp8T+agW4SpZwNvVxFvU3/+3lOu7+V2fIasBtjQkJ3fE= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103155; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7ZhdYXogTw9rlCshhYuAvxL6CLuFxiREWJLLOXLAv/M=; b=EWT3oLxh/NtPTiksJ2FFgOxl95RyKWvLLHiHPjBO/J6Nx/wrBNlDcuI5yRjkCgnosRdkTrd0NLS3B8cFgyeP+I3xxLiYi7vdUDE74P+EolE7xy//ExxXu1brG0iuLlNxXErIVsyqhFWJNr/+SMuHsGxVmOEyhm1wnZ1Tkmrg2pI= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103155418159.2402492394433; Thu, 26 Feb 2026 02:52:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYyb-0004Ee-PG; Thu, 26 Feb 2026 05:52:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYya-0004Dr-H6; Thu, 26 Feb 2026 05:52:12 -0500 Received: from mail-southcentralusazlp170130001.outbound.protection.outlook.com ([2a01:111:f403:c10c::1] helo=SA9PR02CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyZ-0000hs-13; Thu, 26 Feb 2026 05:52:12 -0500 Received: from SA9P223CA0021.NAMP223.PROD.OUTLOOK.COM (2603:10b6:806:26::26) by MN2PR12MB4191.namprd12.prod.outlook.com (2603:10b6:208:1d3::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.11; Thu, 26 Feb 2026 10:52:05 +0000 Received: from SN1PEPF000397B2.namprd05.prod.outlook.com (2603:10b6:806:26:cafe::1c) by SA9P223CA0021.outlook.office365.com (2603:10b6:806:26::26) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:52:04 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B2.mail.protection.outlook.com (10.167.248.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:05 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:44 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:40 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=jopvj/NqNqhG5TKtwhTL8A0blQ6dVdUaAIi4ahykgFPTJcSxzOCdVq5qPMlhEwyLDp/CfYfaflNiQ0jY/5BHWlYtsKeEajmumLs+PeORZ7EsBwe3K8tsBAMoWY01gZwuPQsqG65zoCxG1ou7qUFy5RZA7Jqu5RvffuZeXYpNBANfHWb+XeSoJW90mlp68r/LTfCxramlUBqIpo3BxrDx31kb+EZALDyVuuyZasuliJXW94K2bIOQnXVk91BiH9JPQp2V1CI7MSaFSaXMx9PcXtqCMgM5slH4a6dYOvNufHo5HHxdqud6Y5gsPX4Np/8F6cJPGTsfR/n/qI0c1KWpGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=7ZhdYXogTw9rlCshhYuAvxL6CLuFxiREWJLLOXLAv/M=; b=LC3VWyPW2xCpU0tiiTaMTXnASJtAlIqbcORwfw2xiBmYIvKd2nBzxFrKg0F9cvEdHs226JOjLBchJ6eZYCKtfnr9CDRhu090CuVSEkHnlm0zqbvTUAQPqk0XLiBHRooUNwYlte6+oOMiNgbXlf6H+gEdMLopJ/+bxdcjiyfDfzMEE7F0VioyeKFoVjfdo4vrU9pz/YGrvggmsiebUzS0DhZyXuiqorUj7WSyoeBE/HnkQJCOmSpTTctWcEAUZF3lxzPRfpgyXVdEHowyu2a+NFHUJOT+N6Iwq6GVvyzmEmJmze7vt/ggd7MXF18/Py7NpoAdbpdh6p1tFsC9+GodkQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=7ZhdYXogTw9rlCshhYuAvxL6CLuFxiREWJLLOXLAv/M=; b=tfE+n2rOHxoZrXIhzy+rvbz5CdTszXvN5uILHL3VWt+NTqc+j49QZBEyXSROMDTcrtJUMsdoKVUeLR8v4b0W0yiiVEPIRDgK0oxggLJAVs+59njmpASCc4KnPkPSwRrkfIJo2AQCkfPJygQQJx+7svgokN3f26pVJCDCx0KNBVl2W95P58pU5CYh57PzrDUqtXClplkhvrtI83tKy4FZyvrVFvOnytFC5BsQMOwmzm14eZU7sxvstHn2lXyNh4kVmVJJRNEyaXnnsAyzBTpv9sKGMXVdrTjUDH+tc59BV5YtU622jhAihh2GoHmU0KUneCf5M2AR3FbwHkAQLycGxA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface Date: Thu, 26 Feb 2026 10:50:29 +0000 Message-ID: <20260226105056.897-6-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B2:EE_|MN2PR12MB4191:EE_ X-MS-Office365-Filtering-Correlation-Id: 70cecba7-a9cd-4307-76e6-08de752514af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: g/U0IN4VmZZL0I/dZ0xel3SYBTmZxuqBHR/p8klDzAxqVbECiLlpoD7gZZz/dSuYsLMg7GkCEyKFgekYkVCr412bZDjzHf44oAty1q9Jm1QnXhHkVS53hNn3dh/rED9B6BtKDCy5uFnUOZS/B1NxcKRdIEQpuSbVvGSfk5bcltWLW10DCzSPch71NrMaJ6fqrRTBjFs7w5zZgB09CnjwJQ80KRf5XzTesePmB/UYyQ6Yl6C/IOjEPYsY63HcbA4dzBv2Gq+4MmqSFhPjJPqMmGqZuIpCtwfD28EWVji4eHDxdIVCSI2eUQ0FqA5tUHy4YSZ1PnjcSrFvQyi5bwmERQdD41941dkrvAN7Eweluzl4K8/zXibf9J7t+ZHU+k8XRxxLfKAA+h4ALitw+gS96hOmNzr2UOdw71sYMnUHlRPpu68UzuGbVEOEhMospH8+/YEiNeUpaidZQbMrJFy0GAlC1F1m1BZ4+KoDGs/oK4mIUQvel9jKIjL7yPZD5F7G73Hu2aN2O+VEW2k3dJwbAbnMud1HnIcaGTjmLj8/bhHFIscooVRWJhbi30ZSucklNVxHpxgYbSlT6G/DKE7CuEKcoKRnKIbI9PoCmGz5gvD5DCKFrejbIPBr3rSQN/pNaRBdYoVjipkYxpgHXPz/vgcEs4HTQjgwsC2PCaC7h7gYwE09b5PUQVZQfu4sXN5ORzhw8RC6ZkLlEz8HlRjX3DIzV0I4ISMtvQeOqWk7O9BpNrRo+ZlCQjh1j/FixAYwoPhrVZTxy7nLK8wt+8d6TwvjXniZnEBEeeCUw8bmwLt6v/HftOAngxjOAx4G5SPys3UCrQBtus8Zs1QfUCHseA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MrOGRPqsinZ5Td8ia8sjjMexmoRSIzwl2MWUps7fBt2etvGrjS4qOwdc3zM6qnWrt4U2AtropyrEnZPEXDSTG39jSkrMzu+bOKGet1U47kSPUgnwSzrr4U0D3Y+N6o+hxpp2q0E6Cn7NcDr3SmN0exI5U29fZoeLDx+E+uinQ2TgkhxOwKdr8w3bWB5TYYaQs4mq8RiZ7D20Ww4W/t7pl3k0WOzawDTDjsfxmIDUqo7/FMI8M9yyTHaXEeNeObzgcpnkZXVT21ThYDJC6tcLwe5dRz3dcnL2ltj7fFScJ12O+hEe5Z/iTtzrdeLVAvVhQmFTC9kX+QcpTuuzJFZoZvDvHFPaq5kDA7QMhS1SOGOtqlUgZJTSuca+aaZ1z75tPw9ux1LIZI0Gs1nyaJ9idH0x3G90VL5l9LzwurmO5oK2nKTv9x/uk2u8LCg3Vsgm X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:05.2463 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70cecba7-a9cd-4307-76e6-08de752514af X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4191 Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=skolothumtho@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103156703158500 Content-Type: text/plain; charset="utf-8" Command Queue Virtualization (CMDQV) is a hardware extension available on certain platforms that allows the SMMUv3 command queue to be virtualized and passed through to a VM, improving performance. For example, NVIDIA Tegra241 implements CMDQV to support virtualization of multiple command queues (VCMDQs). The term CMDQV is used here generically to refer to any platform that provides hardware support to virtualize the SMMUv3 command queue. CMDQV support is a specialization of the IOMMUFD-backed accelerated SMMUv3 path. Introduce an ops interface to factor out CMDQV-specific probe, initialization, and vIOMMU allocation logic from the base implementation. The ops pointer and associated state are stored in the accelerated SMMUv3 state. This provides an extensible design to support future vendor-specific CMDQV implementations. No functional change. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 85669d0e00..5bdd01afb5 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -15,6 +15,22 @@ #include #endif =20 +/* + * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to + * support multiple VCMDQs with virtualization capabilities. + * CMDQV specific behavior is factored behind this ops interface. + */ +typedef struct SMMUv3AccelCmdqvOps { + bool (*probe)(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, Error **er= rp); + bool (*init)(SMMUv3State *s, Error **errp); + bool (*alloc_viommu)(SMMUv3State *s, + HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, + Error **errp); + void (*free_viommu)(SMMUv3State *s); + void (*reset)(SMMUv3State *s); +} SMMUv3AccelCmdqvOps; + /* * Represents an accelerated SMMU instance backed by an iommufd vIOMMU obj= ect. * Holds bypass and abort proxy HWPT IDs used for device attachment. @@ -25,6 +41,7 @@ typedef struct SMMUv3AccelState { uint32_t bypass_hwpt_id; uint32_t abort_hwpt_id; QLIST_HEAD(, SMMUv3AccelDevice) device_list; + const SMMUv3AccelCmdqvOps *cmdqv_ops; } SMMUv3AccelState; =20 typedef struct SMMUS1Hwpt { --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103202; cv=pass; d=zohomail.com; s=zohoarc; b=aFqMoe99MCn61dtNNGeE4WdnVaFaT83w9ealZ5dc9BFG7oRcBwSrOCHMRlCx5C+iaUOFsTFvJkghD0we47XUxG26fii9hvs2soYoSufvN/sc7d1eW4yS8nNE+tW4vhU7kpf8NdEPWF6aBA5d816y0bm8vcsDDIZmQg64hYsh6KQ= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103202; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+oMvxWKaDJYbezn/n0ftprtRKbFJ/31jhS3y5u2S6Eo=; b=VlS+//UOTbAQf+iSqPA2T/6GJKBXYzEZBTsyBIHDjzrCdjY0aI0RQmUcr7vJJsM+4Au6ToaisJlezvJmkdeQ/FcCc6fihIPteHYlerB8h/6tZpxFNmNbVphug/Znv5yjUHL4iFHhg+dG3NLFRonUm8IC8tpW01WOhO1tTzNoceo= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177210320286318.025357116405985; Thu, 26 Feb 2026 02:53:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYyi-0004GH-KE; Thu, 26 Feb 2026 05:52:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyg-0004FQ-VJ; Thu, 26 Feb 2026 05:52:18 -0500 Received: from mail-eastus2azlp170100001.outbound.protection.outlook.com ([2a01:111:f403:c110::1] helo=BN1PR04CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyf-0000j0-Ek; Thu, 26 Feb 2026 05:52:18 -0500 Received: from SA9P223CA0008.NAMP223.PROD.OUTLOOK.COM (2603:10b6:806:26::13) by CY1PR12MB9650.namprd12.prod.outlook.com (2603:10b6:930:105::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:52:07 +0000 Received: from SN1PEPF000397B2.namprd05.prod.outlook.com (2603:10b6:806:26:cafe::5f) by SA9P223CA0008.outlook.office365.com (2603:10b6:806:26::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:52:06 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B2.mail.protection.outlook.com (10.167.248.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:07 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:47 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:44 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=L0JIZO/N5AFcISrik9cEZZcbgC3WKGNpQdFXS3KC67nfQJSwHnbP2fGLyhmrScwCJHg0dYdfOrSKpL1Eki6H4W0v6obASWFD6AzSLwD4vSQq2YfPGbqYzE90nUVClHXLl0ePOSPdVCWhXgZ7olm8aLpHC+MsOTJMCEdiXIBb5xTU96s1E6Txl4hUcOWPBiLdryh388Mje5b6Q9DtbxYeyZwGtExyRE169t4yo4mBrhKe5Vo9nMCb+1UQwYqxcpjtTTu6lRb37PGqwhCYZYT5MbEjtQu8LFo5pBasyCTbKY1X0ByZz+zc8IZUpaIScg42CJ/R1RPHpWTBjmTd+IpVbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+oMvxWKaDJYbezn/n0ftprtRKbFJ/31jhS3y5u2S6Eo=; b=ga1OqIOyUc2uzrp0F01DEr1xd5LUFpIuzVEi8CGfmiOwTIZaI07NqDjZPnPpykGour97AZRa+2g9yxkYafsGscn78P/hZS95WGob41WjCXTOJ+R4RAQO0mMFXFYfoUP1BL+tMR33w6joga4ej9K7pDdSF/XbZUFrDYrEHap1xDeqrwTsMMQOlaNFAOxBQy4Sdzft3l+bjp0xKwUQAyLl+MJ1ZrE78TbUTvktkBFq9aIa4miABHvkICLielmGIeQ42UrrjFQwiqc69oyf8goQvuU0kIRIDjs79PwH3UI/vX1fjFAKbVW6h2Xcj+nJdMVWcPTh0VK6a5G5aO0QJyroJw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+oMvxWKaDJYbezn/n0ftprtRKbFJ/31jhS3y5u2S6Eo=; b=IOpl21KhyU4LpAISyoHZ3UGa2xtaZVku21IS1rhIHW00EMNHzgNHB1FO6Lry7ujE3LV9nwyKMRVEI1dCnn/xWuSIL9Coodl9JnukE+lGrFAtfI5pWwqvUXd0v9yh+lH00JhTVqvy397FVcDw2jEgMTe4DW2i75rCAWmsjPQTm3k32doxgFfMHShs2wK6Yj/q+f8Q46UN9ibN3A0tsqCSvqFh58TtkCrALbPCzejjLp7ksQkF6sA1uYVVezC/tPIxw7sPW940iehRaKQMTiId1TcJnI4FfCsW0fiUfoboCSmeOg5xgAIu95UDYZHkAlDMv+l2bAcC513dfvJbUpj9Pw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 06/32] hw/arm/tegra241-cmdqv: Add Tegra241 CMDQV ops backend stub Date: Thu, 26 Feb 2026 10:50:30 +0000 Message-ID: <20260226105056.897-7-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B2:EE_|CY1PR12MB9650:EE_ X-MS-Office365-Filtering-Correlation-Id: ea206261-5be7-459b-0edb-08de752515fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: E16VGAclZOwBfJjUVMg7uxTg+SDvBMrFziJGjdzFi5GB4QBdC+/j7Sag9IFCPEHdHhC4fBAQ5XheH2x2tfDghxhqFg2fiSr71XpNfe6H3KDyoPwdfuKS9WJM0MeH0f5A3TSCHVhC216V5P3f3t8hjdWr4fDWUAddpYXaBnNy0UHcD8kntcSnFi5KxBCb512fEc5fdmiXkUGc+mm9anveYFc41g1IUbOcs7lyl+P5ZicGBSgoMUnnVkH2pg6RMy4aZtxPYaq/CssuGAv2Qep1Opsl++L5Aq21lujONC61ApEe84q/wxq3c4rJPQj9ex5HpVfQ4v2reM3s6V93vWWcDIJTHY7necEbBE+INbUkUv6cJA45GiS3U+EYp55skhfkCAD1WsdWJhe7CQvxwJRPKoVoGx0HglqzyS6e1QaFVqPuMQdbthRPACxruSIj9tQ8B5jh1NdQtMnE8PHGUh7b3n9vhFU13FJgknn75ffSxaoTxCBzu0rKx670Sdbh2DG2PiZ9FMr8rLHv5uNCtW00mVbFX2uvOOYxdwmIFx3O4MQWEKxFIZjfEy7XdkJ8iTLPl1OcZ8yxE+FV7ktD5QOIWWvSssGwQoMAmMjnxnODHlCUY8qxecIPMAyt4MjNXCxMpG8s8gj0XrEh+n36gLUu8N3gfHHB4PCcYPtsRmcB8088+ZDzajWqJwwAnoNEIspzr4H6uRfcd5aDKRtOtyGWQfPNTv72abpXMSWit3QIzqxvWfjWJFBu41E86TuEGINYu6/SIR1cNUezc+QWwH8abxWC8Mr6eSwfzRuTDZsqkU73riXQsZg/xmKJCMQK1FduVyl6wcwaQwC99jOceFR7BQ== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(1800799024)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Bv1INLACBA9kLOOBuUQ4/Uxfw+YQOtuyw/jg5m5tpoR/n9znquJxvR4RR8aGiVUjYuoWecChsJn++tcMOj9Y58JFImNgBzodUEDlT+Y7afbMZibqtv8iycujGhZtC/vZbW91ZLk5yy2e4cw2MihnmuUbrTEhur8A3JgPM8nPgtTG90oH8VF44osaoCyByuMj0L3GPfzuVzJDuDlUPhSRXiWBqm3WHtGL7E8TwQb4t6yO5R13j9s3Ah3PR2PpOkltUPv5RcEf28D6uXXsOh8JNixTxW6UQnLdsFZU6X8Z+qs45H5iynl12y0AF2RayxRpvsjEd16NuyE8Pmln6u5alERjwqrBBHQljfWkGQQ4e4u94AXmMaTV539g5OBz1idl5sQMRpiYVKWwD9gim6hOAsAMS1FqcPAw9+pHhqN2kKqPdtC4bAIwwoG0mrkwgP2T X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:07.4608 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea206261-5be7-459b-0edb-08de752515fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9650 Received-SPF: permerror client-ip=2a01:111:f403:c110::1; envelope-from=skolothumtho@nvidia.com; helo=BN1PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103205093158500 Content-Type: text/plain; charset="utf-8" Introduce a Tegra241 CMDQV backend that plugs into the SMMUv3 accelerated CMDQV ops interface. This patch wires up the Tegra241 CMDQV backend and provides a stub implementation for CMDQV probe, initialization, vIOMMU allocation and reset handling. Functional CMDQV support is added in follow-up patches. Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 15 ++++++++++ hw/arm/tegra241-cmdqv-stubs.c | 18 +++++++++++ hw/arm/tegra241-cmdqv.c | 56 +++++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 5 ++++ hw/arm/meson.build | 2 ++ 5 files changed, 96 insertions(+) create mode 100644 hw/arm/tegra241-cmdqv.h create mode 100644 hw/arm/tegra241-cmdqv-stubs.c create mode 100644 hw/arm/tegra241-cmdqv.c diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h new file mode 100644 index 0000000000..07e10e86ee --- /dev/null +++ b/hw/arm/tegra241-cmdqv.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * NVIDIA Tegra241 CMDQ-Virtualiisation extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_ARM_TEGRA241_CMDQV_H +#define HW_ARM_TEGRA241_CMDQV_H + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); + +#endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv-stubs.c b/hw/arm/tegra241-cmdqv-stubs.c new file mode 100644 index 0000000000..eedc7bfdcd --- /dev/null +++ b/hw/arm/tegra241-cmdqv-stubs.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * + * Stubs for Tegra241 CMDQ-Virtualiisation extension for SMMUv3 + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" +#include "hw/arm/tegra241-cmdqv.h" + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void) +{ + return NULL; +} + diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c new file mode 100644 index 0000000000..ad5a0d4611 --- /dev/null +++ b/hw/arm/tegra241-cmdqv.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights res= erved + * NVIDIA Tegra241 CMDQ-Virtualization extension for SMMUv3 + * + * Written by Nicolin Chen, Shameer Kolothum + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "hw/arm/smmuv3.h" +#include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" + +static void tegra241_cmdqv_free_viommu(SMMUv3State *s) +{ +} + +static bool +tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + uint32_t *out_viommu_id, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static void tegra241_cmdqv_reset(SMMUv3State *s) +{ +} + +static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, + Error **errp) +{ + error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); + return false; +} + +static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D { + .probe =3D tegra241_cmdqv_probe, + .init =3D tegra241_cmdqv_init, + .alloc_viommu =3D tegra241_cmdqv_alloc_viommu, + .free_viommu =3D tegra241_cmdqv_free_viommu, + .reset =3D tegra241_cmdqv_reset, +}; + +const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void) +{ + return &tegra241_cmdqv_ops; +} diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index c66c452737..3305c6e76e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -626,6 +626,10 @@ config FSL_IMX8MP_EVK depends on TCG select FSL_IMX8MP =20 +config TEGRA241_CMDQV + bool + depends on ARM_SMMUV3_ACCEL + config ARM_SMMUV3_ACCEL bool depends on ARM_SMMUV3 @@ -633,6 +637,7 @@ config ARM_SMMUV3_ACCEL config ARM_SMMUV3 bool select ARM_SMMUV3_ACCEL if IOMMUFD + imply TEGRA241_CMDQV =20 config FSL_IMX6UL bool diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 8f834c32b1..fc83b635e7 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -88,6 +88,8 @@ arm_common_ss.add(when: 'CONFIG_FSL_IMX8MP_EVK', if_true:= files('imx8mp-evk.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) arm_common_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-= accel.c')) stub_ss.add(files('smmuv3-accel-stubs.c')) +arm_common_ss.add(when: 'CONFIG_TEGRA241_CMDQV', if_true: files('tegra241-= cmdqv.c')) +stub_ss.add(files('tegra241-cmdqv-stubs.c')) arm_common_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c'= , 'mcimx6ul-evk.c')) arm_common_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_common_ss.add(when: 'CONFIG_XEN', if_true: files( --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103317; cv=pass; d=zohomail.com; s=zohoarc; b=WZAVg4uW3VMkFtDyiq9FH77hYmEkGGKXC4K5OnTThpNO6JG9IGBlrstZ/udtXas73HRah6FfclYG2/3VbWJFGRUMiHfFCBDNjOuGSNySReNHZyzsbIbF/TN3KZciHCcv5dyP5hizyF59CzzLeWOYKTCCBNL5kE4x9UcxBhBNrUI= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103317; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LqitqKl/uFZHk+Hq3v64X4lxeVqr4qkdUK7JGEdxZs4=; b=XwRQUBKBBQR54wkphI781YcPjQPO20CpOV34oQuf+vZWIRm/kkEdNLm8bdHRaevNFacJYsPjDaAqGA0Eaxh9OW/zlVTE77JGWpXgRhdHI2fTnjeyhdhjFIZm/MQT3ku1mE+Q9j9+OTPw9njLerG0pXFyzh8Rj87x/ADJXKzafFA= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103317698267.06018216375264; Thu, 26 Feb 2026 02:55:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYyj-0004GS-6Z; Thu, 26 Feb 2026 05:52:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyh-0004Fc-N1; Thu, 26 Feb 2026 05:52:19 -0500 Received: from mail-southcentralusazlp170130001.outbound.protection.outlook.com ([2a01:111:f403:c10c::1] helo=SA9PR02CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyf-0000j9-Ur; Thu, 26 Feb 2026 05:52:19 -0500 Received: from PH7P220CA0135.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:327::35) by IA4PR12MB9812.namprd12.prod.outlook.com (2603:10b6:208:55b::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:52:11 +0000 Received: from SN1PEPF000397B1.namprd05.prod.outlook.com (2603:10b6:510:327:cafe::1e) by PH7P220CA0135.outlook.office365.com (2603:10b6:510:327::35) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.23 via Frontend Transport; Thu, 26 Feb 2026 10:52:09 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B1.mail.protection.outlook.com (10.167.248.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:11 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:51 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:48 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=AzHXwtYSI5U5WlI3IPh4vVQXrCHaqlWxEBzYRsnbhGy5cIxF6VeD4gHkTRQXSOl7yXo9nJxTKpztdVGACfjao8Xmn1aV74h7Kxm/8XLO8YNpdZGE5VusdY961KfTEJCMZL1PSNFn5CG92NJWAGXjyQ/GYgft6rXCgVZc1+/CHbmUA90rGVLRbM0mjTSX/7njFRsJzrX7e/4XJ2kGlxN9HS8srAu8N9BomesLQ7yBFfEzMkOCYMNVXOqoNUl3/C1SNTFQ5R/mO0TYV8yBEYoKwUd6KiuZGHxsx4e5Nw82dG1Ba0LN+L4wlfTJPAPuqS/1G0kASxZ04bArNYzLg0dyTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=LqitqKl/uFZHk+Hq3v64X4lxeVqr4qkdUK7JGEdxZs4=; b=YzZKRzOnUj3xtBQJOEEi1tEIgNQOVdoLk9KUtHE+eFjLA0ffoeeTVfbbCFbw056D5Vw6I31EHuBuUh+wR4bLItIhIyhobBxsqCJcRn5KNntxt3TGNqhvosqEk8Y+iPXR8lyTylIATcpuiV+uFSfHa2pRj0wI2HVbyxpz6aZIh41XPTAdfw0na+4DZQ5Map2bygCJxMY+aC4Ug3qu22dv29T7pZW6BYsoqnICvNqzRRpwdj9MwT2BjHBwErgq2niIIWL8jkj+4oVsZEW7asjeByzaC3/+cSO7SgBwg7L9Ch7ckusHn9JTiR8stqmyf7bLz6pcVAKHeyYXvyVuXFdjIA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LqitqKl/uFZHk+Hq3v64X4lxeVqr4qkdUK7JGEdxZs4=; b=bs6AyRlXFcZw75YQci82TyYH9Od3dsZNxYAexDtkYkQs9fvXa4ijdXjjhfZaM78N6FD1hJgaIz2WiSSY9aFmSNYIcTWn9dqqPMQFxPrDi33YeowbntSNu+9rbcobklLwhb67DDmlns3nBGDNFpPTfBefhxG1qobrTbgBNTIW/PmzYhvRMd8hYd6AHgIUEfJMt4fzcUJ3zKLpSHTyqzlQX+c7ry5uJv5Hq3o7s6B2fpIulrrakPmO0d8IAGYd59SVGtpRdoYP5d9Lf/B3ICa9PyBvsM32ye9DuSuIoJgm0QdExglv6JF8abISXThBXWMA0uX494i63f5BN1GfbimNSA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 07/32] hw/arm/smmuv3-accel: Wire CMDQV ops into accel lifecycle Date: Thu, 26 Feb 2026 10:50:31 +0000 Message-ID: <20260226105056.897-8-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|IA4PR12MB9812:EE_ X-MS-Office365-Filtering-Correlation-Id: a471b790-9950-475d-590d-08de75251838 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: orG+mhq9sXB0R1hduXWTW3RiPj7hGx2tqhAJBATz2nhl0sTW/snPqY48ziD/x8PhjENHJlps8sloCO6yv512kEi7F4HdX3H5fpC6nkEv4NthBdj+p3ravOPXnmKaB+hfm6VIgkPSqNXzG9VdOsvvzVpc4Lfd3NHVQoEG44EIOsPb69GznEOfcDNTT1nll49c0YHHWIOXKzFACO7B2yyzpoLp+tfm6pEwFgd2LqrZC+0mxolvZoE/+/csg/lFEYo+BDXzkFKa8GBWELnEck4ebIB+kTyRoqJKEYr5GP6apnHxJ8455HzWOwI8q2bNtM2jDPK8gjUM7sbVIvTkwCpr04HPnBWxSOrN4H0rgkagyUXfLzRP3Y4sK8SIuWYEMmdVSaTGJlhouBWlvsqM82iPtAxJZsyc4H3kFiplRPVgLk39Drh+c6DF+Cy/wgbQAUH7DAzLtCIkGxkvFABTmkGV5t51YNC+8GYSZH92zn8H5diK1TmqCRygcIMQvjhBlp0TIeicrWpyTKN2JI/uz3eUu8bhWZsLNcWu86LEsQEFFA82mxP0Obp4BTLi7CD+kh/Ve5Zpkz7ji0f4uxixuTRt0xi0e0qoQig6vk8pZLpeu6OFr8ZU7eBbBwLgG5LjzZ+NvaDeemgH+4o1+BSla30LBPA4wGUDMEXQ6+yi6Oc/CBU4A7yaASynnRGmcTdjNZd8GD8nPp6uQomReafBwv+VyYq0YaXtaNaMx4RCs74R0f0xWzsRwrcsorYK4DuFx5ha9jAhjuGYSqTIH/ifZiTssvHj3/qrugQOUuHIpH33nHgM4VhiETw2HlTPolSwdJF/dfcoOqRwL6RsuublP8wrhw== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(82310400026)(7416014)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LHHaNBmW1PtHgwDDGqI9RANRqdw2NGGJgIJ/WRNXhIa7SpuQVfKW6TMnXmWN3iXQn//bx6g/CenS7ERhsutC9Kh2KR/Huep7upHfBUHyq7GcXZxCi0832hpbuUe1zbq4bYoKr/dRrNq4zrrO65EeGT97kA/ozhbyoI8Ia5YrBMZ16pM7DUd/kH0dYOENtsEwNsDu0KAYwsvxlX04QGNdAe+0nBHhXIo7cvLte3wlKtSkt9XhtXo80fscnYIU8Pt13NyCgDjm+5aJDKrC/V75MBxq+4EVWXwn2/0olV5qZXP/lRSJwSfOiDgSHlrXc3kZde52uQesAMaFnypQSPo1TviY/KJVDvlIj18uFc9UFygbukRgPbA/crrCcEv5T34FxM8QOxb2ATHmyzVkykr6VYsNQfUgf18UFk6OwXsEO5NM9Ytv302ntkEZ4sE7gNzf X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:11.1368 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a471b790-9950-475d-590d-08de75251838 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA4PR12MB9812 Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=skolothumtho@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103319656158501 Content-Type: text/plain; charset="utf-8" Add support for selecting and initializing a CMDQV backend based on the cmdqv OnOffAuto property. If set to OFF, CMDQV is not used and the default IOMMUFD-backed allocation path is taken. If set to AUTO, QEMU attempts to probe a CMDQV backend during device setup. If probing succeeds, the selected ops are stored in the accelerated SMMUv3 state and used. If probing fails, QEMU silently falls back to the default path. If set to ON, QEMU requires CMDQV support. Probing is performed during setup and failure results in an error. When a CMDQV backend is active, its callbacks are used for vIOMMU allocation, free, and reset handling. Otherwise, the base implementation is used. The current implementation wires up the Tegra241 CMDQV backend through the generic ops interface. Functional CMDQV behaviour is added in subsequent patches. No functional change. Signed-off-by: Shameer Kolothum --- include/hw/arm/smmuv3.h | 2 + hw/arm/smmuv3-accel.c | 93 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 88 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 26b2fc42fd..648412cafc 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -73,6 +73,8 @@ struct SMMUv3State { bool ats; uint8_t oas; uint8_t ssidsize; + /* SMMU CMDQV extension */ + OnOffAuto cmdqv; }; =20 typedef enum { diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index ab1b0a3669..4373bbd97b 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -18,6 +18,7 @@ =20 #include "smmuv3-internal.h" #include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" =20 /* * The root region aliases the global system memory, and shared_as_sysmem @@ -522,6 +523,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDevi= ceIOMMUFD *idev, Error **errp) { SMMUv3AccelState *accel =3D s->s_accel; + const SMMUv3AccelCmdqvOps *cmdqv_ops =3D accel->cmdqv_ops; struct iommu_hwpt_arm_smmuv3 bypass_data =3D { .ste =3D { SMMU_STE_CFG_BYPASS | SMMU_STE_VALID, 0x0ULL }, }; @@ -532,10 +534,17 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, uint32_t viommu_id, hwpt_id; IOMMUFDViommu *viommu; =20 - if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, - IOMMU_VIOMMU_TYPE_ARM_SMMUV3, s2_hwp= t_id, - NULL, 0, &viommu_id, errp)) { - return false; + if (cmdqv_ops) { + if (!cmdqv_ops->alloc_viommu(s, idev, &viommu_id, errp)) { + return false; + } + } else { + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3, + s2_hwpt_id, NULL, 0, &viommu_id, + errp)) { + return false; + } } =20 viommu =3D g_new0(IOMMUFDViommu, 1); @@ -581,12 +590,69 @@ free_bypass_hwpt: free_abort_hwpt: iommufd_backend_free_id(idev->iommufd, accel->abort_hwpt_id); free_viommu: - iommufd_backend_free_id(idev->iommufd, viommu->viommu_id); + if (cmdqv_ops && cmdqv_ops->free_viommu) { + cmdqv_ops->free_viommu(s); + } else { + iommufd_backend_free_id(idev->iommufd, viommu->viommu_id); + } g_free(viommu); accel->viommu =3D NULL; return false; } =20 +static const SMMUv3AccelCmdqvOps * +smmuv3_accel_probe_cmdqv(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + const SMMUv3AccelCmdqvOps *ops =3D tegra241_cmdqv_get_ops(); + + if (!ops || !ops->probe) { + error_setg(errp, "No CMDQV ops found"); + return NULL; + } + + if (!ops->probe(s, idev, errp)) { + return NULL; + } + return ops; +} + +static bool +smmuv3_accel_select_cmdqv(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, + Error **errp) +{ + const SMMUv3AccelCmdqvOps *ops =3D NULL; + + if (s->s_accel->cmdqv_ops) { + return true; + } + + switch (s->cmdqv) { + case ON_OFF_AUTO_OFF: + s->s_accel->cmdqv_ops =3D NULL; + return true; + case ON_OFF_AUTO_AUTO: + ops =3D smmuv3_accel_probe_cmdqv(s, idev, NULL); + break; + case ON_OFF_AUTO_ON: + ops =3D smmuv3_accel_probe_cmdqv(s, idev, errp); + if (!ops) { + error_append_hint(errp, "CMDQV requested but not supported"); + return false; + } + s->s_accel->cmdqv_ops =3D ops; + break; + default: + g_assert_not_reached(); + } + + if (ops && ops->init && !ops->init(s, errp)) { + return false; + } + s->s_accel->cmdqv_ops =3D ops; + return true; +} + static bool smmuv3_accel_set_iommu_device(PCIBus *bus, void *opaque, int d= evfn, HostIOMMUDevice *hiod, Error **e= rrp) { @@ -621,6 +687,10 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus,= void *opaque, int devfn, goto done; } =20 + if (!smmuv3_accel_select_cmdqv(s, idev, errp)) { + return false; + } + if (!smmuv3_accel_alloc_viommu(s, idev, errp)) { error_append_hint(errp, "Unable to alloc vIOMMU: idev devid 0x%x: = ", idev->devid); @@ -867,8 +937,17 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Err= or **errp) =20 void smmuv3_accel_reset(SMMUv3State *s) { - /* Attach a HWPT based on GBPA reset value */ - smmuv3_accel_attach_gbpa_hwpt(s, NULL); + SMMUv3AccelState *accel =3D s->s_accel; + + if (!accel) { + return; + } + /* Attach a HWPT based on GBPA reset value */ + smmuv3_accel_attach_gbpa_hwpt(s, NULL); + + if (accel->cmdqv_ops && accel->cmdqv_ops->reset) { + accel->cmdqv_ops->reset(s); + } } =20 static void smmuv3_accel_as_init(SMMUv3State *s) --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103187; cv=pass; d=zohomail.com; s=zohoarc; b=eglwvLq4/0iqzLgmAmNNYixlTA4GZjFHJG1JXqZI+SM0WBMlS8MhENPJaqaB4jHGOpHpQfbw0qHQBEhPumy5vwygsCh2B46HNvthK6tcL+Y5JHngT8pbVWs1ADTTI3mUzNgdaUpIXVICAHmy4j4ePiAOF72at0Tplf7OXC9D18k= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103187; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hj8Q14XcCmzWE31d+zXAJH4H2Osd0l8DlJG3ja3Zmng=; b=i/6e9ldeBlSePmEMWpOGLSYztvEIPA3P9KK9TxnGAie4hY99J5k2QSA1tQFYRQd1mGYG4iTl+4VduPC/YGdJ2jQFZQZVhaSrYLW56lvkndHTRzWaB8edOoDy1+1eg7EYdt5weho8z8jCgH3vNhBxQkkahTCZreMTINUX+xY4oF8= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17721031872361003.0520592736518; Thu, 26 Feb 2026 02:53:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYym-0004IA-NQ; Thu, 26 Feb 2026 05:52:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyl-0004HO-3j; Thu, 26 Feb 2026 05:52:23 -0500 Received: from mail-northcentralusazlp170130007.outbound.protection.outlook.com ([2a01:111:f403:c105::7] helo=CH4PR04CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyj-0000js-LG; Thu, 26 Feb 2026 05:52:22 -0500 Received: from DS7PR03CA0045.namprd03.prod.outlook.com (2603:10b6:5:3b5::20) by SN7PR12MB7348.namprd12.prod.outlook.com (2603:10b6:806:29b::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.19; Thu, 26 Feb 2026 10:52:10 +0000 Received: from DM2PEPF00003FC3.namprd04.prod.outlook.com (2603:10b6:5:3b5:cafe::33) by DS7PR03CA0045.outlook.office365.com (2603:10b6:5:3b5::20) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.22 via Frontend Transport; Thu, 26 Feb 2026 10:51:41 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC3.mail.protection.outlook.com (10.167.23.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:10 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:55 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:52 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=KXMGGF4qMutcjExqB/yxhi9scMD2P4KzhKV/xjlwZhOME5TfNGk5fOkdg0sbANZXbTZC1cdW/2Cn0FvmCWwzrcBY1mFs6hF9oWi8PEZjAGMNDNs8UWy9oS0WYXrZ9D+gGfxGw0QW3ady7IpmSuSWtS9ffxM+khvWDtHehyf6626dDzYIzIXfRBJ281zQxJSnnFTMlm/WMorc3iwWu+ZGux+aeeD/ZWE26wLZxb6nRcbk2CzJDtfzzff33Me01jVXE+JDcOcq6xFPpVLRowmOJbEC9m+xNHEAkZ5IxL6Pm9d5vRGeUOuPaB47OPxP4kpQbH4V7M0uf1u6Yj/Jdgi+5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hj8Q14XcCmzWE31d+zXAJH4H2Osd0l8DlJG3ja3Zmng=; b=ST+uf87oGMqdCVUdU0wJIatYtsuSYTmqB69F1jB3pwcpAfg6+S04Ydniqb6yv8fyk9XPdmukTd1dvQL8EEYm0/wc63VRG/+nAWU+p1s2PzKNYO6QYfZCQx3b39eY5UC9D1rf9JgFJg8kQtAYZT1qPvFlHRVZmj3ybMvzftTqCIiqFJvKDNACzCxKMKrmeDItSCJPsP+G22m2nhIpe3gGsi9kBHANKm36/NQ75kvPhItYsBru0G0kiEHftZjowqZH8LZAcsoeN30r8vW9/wBqv9+wdvhj82BYQBSxF2Mul1aem7/iW14jD/tSIAK2U7Vqt+NepEUzJdpU/F43FrVqfQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hj8Q14XcCmzWE31d+zXAJH4H2Osd0l8DlJG3ja3Zmng=; b=Y2fmkUkzVoURDohG2hutFjsRvlI9Q8Lw5P+YJ7UA5AnkXj8iWDr+BhvlBbi3r730ZcHpxp5fWGNQo6zcHIyRqDolR78jtHITPG1+ojPfQd4XQYUtxZMyiV8ke3f1YVeQa1nRgMTehs2KnztluzzLetLqDKtqpvqhCbVfeF91j55/bsrshBHrMqTLJ6UY8tDeDcPcB9Y38s6pjRv2oUm85PI0rNegEi5jg/k19Fu/vFEtaW3tAqgMSFYrdh6rRceUEErkQzDII50SmHhBJ3vlzWYOZp6MPfGWMZel2WZTDdiVaJ+gD3zQMQYBXW3aoUegcOdDOoPl5AthRe6AVBXe3g== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 08/32] hw/arm/virt: Store SMMUv3 device objects in VirtMachineState. Date: Thu, 26 Feb 2026 10:50:32 +0000 Message-ID: <20260226105056.897-9-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC3:EE_|SN7PR12MB7348:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e667f59-f3d1-427a-980f-08de752517e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: JjyrxOFGGPqrrWKwrq0lMWGHe2QVTKEVH9HinPLRA/WrKWkK/23ntKzL27IPTh9HOv/Z1y+yC8FW99j1uNxaM+P3mwv7kBx1V1s9HrcTwz6w5Bx8ArP6qV82FVhGl1pzWXM12ia7x4CUUUd1efsS2OkO94mhr/3jgwxKdrYTl+NrfY3qxwuVeKvXeL0mGc6r5Wq4sDYwDeKOiWHPP5kNoaVlrI0Qcw+7jFijPJYsDRv/OFGgUiqs0L0iMjjKF8iPhj8xFEE4x4qHvF7w+WNkCkqbrTb6FW/mN/DPHq/b2delD/kd2hmV93OalaTvtlZLxwluWOoEOZ1QA50yjlJuN2h7jKse1vnjzK4lssKpKOJMpd9ubtD7pr/sbZW3rYIyMRxiNoX7pN4aP/v845yxKd5EWV5bD/gp/hfNylTBx98j4oG5pU5wjgCeScpZ050D62eO5Q3UeWy1Dle2JH4aeSC/oVKuqc0az1wFeG+ROYrF/R7nrE2bja1/xoyUdWnESENL3/eutPy1K0ABF4nrtOFZ6YBYO8iGp3VODJlu3E8A5S02pckySWJubmdVDaMne5AjY57zpG62yT/U7p0JrGy1uWtuVrFgJ6YTuTR1ecMd+fbp/eMfRtMXm/saoHKjUsJy3xkVObMyqF7uOtofiyraJ195Isaqq3SvCWs7halRkli3wXVt7LNx0TsA7ZenhFdP8edEZTlD9Q+Fdrgn561R2lwaMd2SBDE4nt+jJiroTXsP6e6eLK0tX8/SQV6QxdNkNvvJ8Jjd9BN7cyLmTYYR91z42+VgxOdLBRorvPrCtxe2v2n+rh5YmYpjfGEVGIsGc4TybLkIhdKjJpg7ew== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ApAzrbHBV/O9TZAYYmQxonpSuYJmsBfapurhcgCmGfRmEsgogC5CiLZb9ljfUvU5IdEGWjaCz3zrVccLial35wSQgtQnM29/rdrv45GQHY2lzP8GsKjz4a1VlbrnMoSbSstzupiiCta6mVZP7n1h24/g53lP6oxt7uvUVltapHeDz4+YCaRe2koymrVXkYEPR0kQ/swhu4qr1iZYCG9n0yaCUMCs/83H/HhlU5eKzUAk+QhOSjE9b9fPFaukdrZ53aDGpTLGUnh0yUhKIJKBhwZw8HHZnVTT0dYmdLU4sZrBM/zgaGYH79LIMRcjN/jGIMu5OyiP1igr4XH594Xooyt+5AstxfQ+xeoi0aGj10ZKXtZTHUIcjdBap+6pzFgtMRHdtBKAkzrraaS5wupjqOAckLSeIRwHpb15YtGwfvqTL3kcOpScWjsi9Epzrgoc X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:10.5759 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e667f59-f3d1-427a-980f-08de752517e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7348 Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=skolothumtho@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103188810158500 Content-Type: text/plain; charset="utf-8" Introduce a GPtrArray in VirtMachineState to keep track of all SMMUv3 devices created on the virt machine. This will avoid relying on object_child_foreach_recursive() walks of the object tree when accessing SMMUv3 instances. Subsequent patches will use this list during ACPI IORT table generation and for CMDQV-related handling. No functional change. Signed-off-by: Shameer Kolothum --- include/hw/arm/virt.h | 1 + hw/arm/virt.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 8069422769..f9437e6410 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -186,6 +186,7 @@ struct VirtMachineState { MemoryRegion *sysmem; MemoryRegion *secure_sysmem; bool pci_preserve_config; + GPtrArray *smmuv3_devices; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 50865e8115..292e523664 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3232,6 +3232,7 @@ static void virt_machine_device_plug_cb(HotplugHandle= r *hotplug_dev, } =20 create_smmuv3_dev_dtb(vms, dev, bus, errp); + g_ptr_array_add(vms->smmuv3_devices, dev); } } =20 @@ -3659,6 +3660,8 @@ static void virt_instance_init(Object *obj) vms->oem_id =3D g_strndup(ACPI_BUILD_APPNAME6, 6); vms->oem_table_id =3D g_strndup(ACPI_BUILD_APPNAME8, 8); cxl_machine_init(obj, &vms->cxl_devices_state); + + vms->smmuv3_devices =3D g_ptr_array_new_with_free_func(NULL); } =20 static const TypeInfo virt_machine_info =3D { --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103182; cv=pass; d=zohomail.com; s=zohoarc; b=mTVzkH+ANDeHMa46QcaLlJdRdDrD8UESyNRs6Qpc6f9P1mB1ODxa3/wxWJ+trSZ4I7ltFD/14Qm+FYW6i7JYyinnNKAgWg8JrNXAVaVMl4bjUrRmzzqEd+vfmQLpRPrEBZQIgDgKIXcTbkLqnM8610uWm8AyEgUEtr9CDWTYj/A= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103182; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JMfvPe8+EXJP/qfD/3eMNEOfmzgMjT4VxgjP4q9/Fjc=; b=ACsITXlo1h7mdXm/0xVOw6SWhXhLCfP89xdqDP014zpgciWDgfo7ZazuGXmK485EwJRGausjASBET9pdVAr+LAkoEWOFHITPpnY+ep2dsATs4naYgtjzS8vObeyDUAmW8vXk3565xTyEa4NnxOCl4SRUDhBL4V7kBLvBLrbJucU= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103182860794.8401911878698; Thu, 26 Feb 2026 02:53:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYyp-0004KU-7h; Thu, 26 Feb 2026 05:52:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyo-0004Jo-3D; Thu, 26 Feb 2026 05:52:26 -0500 Received: from mail-westusazlp170100001.outbound.protection.outlook.com ([2a01:111:f403:c000::1] helo=BYAPR05CU005.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYym-0000kD-Gg; Thu, 26 Feb 2026 05:52:25 -0500 Received: from DS7PR03CA0058.namprd03.prod.outlook.com (2603:10b6:5:3b5::33) by CH3PR12MB8902.namprd12.prod.outlook.com (2603:10b6:610:17d::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:52:14 +0000 Received: from DM2PEPF00003FC3.namprd04.prod.outlook.com (2603:10b6:5:3b5:cafe::fe) by DS7PR03CA0058.outlook.office365.com (2603:10b6:5:3b5::33) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.21 via Frontend Transport; Thu, 26 Feb 2026 10:52:04 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC3.mail.protection.outlook.com (10.167.23.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:13 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:59 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:51:56 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Cf8saBvMnf5k3QqMTu28fMQOIcpyTT4czSfPBXAkc14oXLOBBZqJZ7McjJMmiJMV9K4UKblxQWVrkMTCL5JAM71Fs9qYifdj0HKtuIFgb6BdcaWJSl/82E8nHMOZsSw5mWdrcaYBuYLhd0In+Xwof/++g4Ev4RgF6onkBSD3Dy1HwSlAsuj/A4A/I5q+v7/+TZ+gyvIhuGOOMNaJkYR3orjysAULOUoaQxKcC4A7GbbThzdZIN1auZCBWQ+k9atUzNwk2wbDNLtx8WmmVnRSBxMcqYUAWxZZcNo9SVdR4KxdAneq/rez3A+b7Xk9xHnyhdmziEKA6EkbZf7F3D9Aqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=JMfvPe8+EXJP/qfD/3eMNEOfmzgMjT4VxgjP4q9/Fjc=; b=ofhGOQ7zzQISERns/ce3HawQNmSG+5nWlk1C4Mqmal4ga4eRaMVHdDNyS00muzMWRc5IDlEA9+04DDiQ/0ClF2nyrjje4+I0MYaSN0wwd7gsmB+kybiV0mE84ioiOY+QkavKtZnxlIvs/0mO8f2hOluQvW1NzmE6i0OoLPr8QuaHiHNb6mVQe8J3vq/NFdW3xN1AC68bZqtIFs9+jI7PDUI6IEFRFlSqIlL+SZH4QKLM/q0CJEHKpxns8PiA98MPmtYlSEVhgiioQLCxjjpGSY/ofkXlPg5THG1Q9B++OrgYkUGIi09YwNwkzgS9xrEKVkD8FXE3vXDzY1Kx1fuiXg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=JMfvPe8+EXJP/qfD/3eMNEOfmzgMjT4VxgjP4q9/Fjc=; b=c105DCGfgJhgc23OZmVgOIBtQo9+rYwGPgq691uq7/UwoRGhO9JNbF1bxtSa2lLfOiEYKY3RZMtSAJ/s2Ly+FpaQYhjEcEqcx/+DfDKDHtvEY+TwYx5KyJROKTi61X6t/jLQzkF813ZWwnQiDrnKuRC4cbmIU3TmPdj1qdR0cPqtF1BENELJYNmukHr8zCw0Gix2O2UlxfMnm6ZYB2Rmbx1UgFop+8L+BxbBcd+NDbGI/Px4vQNMSPPLoD85S3qapwgRz+5Jb9hA+iHfFPLDbev1AJDAxHRMG6UEfTgC3ANseeVinnd7iNJGCk47a1YlPfNaz+kP2ueG2E5Nvh1weA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 09/32] hw/arm/virt-acpi-build: Use stored SMMUv3 devices for IORT build Date: Thu, 26 Feb 2026 10:50:33 +0000 Message-ID: <20260226105056.897-10-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC3:EE_|CH3PR12MB8902:EE_ X-MS-Office365-Filtering-Correlation-Id: 11b10a4f-857e-4635-7eb3-08de752519df X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: AOdL6mEPn76iQ7D6ug8uB5F5KP2rg96NPlhmt5dYiyqALsTU6dTfRSU98yX2b+bVT1pRyvB+6s/cdbzNaTJA6l/GVinOzu6L7MAEXePqGOmPUpeKi9XSEYYuMHwnA0ub2PA6MWh8J4iBg1+WiKmhHpiPyXvTd5rHE4My4VFR1uyqAh8gImavGZxnO1/00DabXB/MM+tXUeMVQCIl1yMfPDf6YhQld636f8OgAwtm5Vli7Ye8jHSVl5BOS17gNYGG8DRGCG+rqvEFWqzSTqWdZrDegnpiqblbFvwSgerge+TpZu3vy86IQgh4hO/vqsLIzaQ/JOU5sT7gp+YXP9n83jIKmnR1cqUiMWvySSdidmudeceEIPsrT4i2tsdntJS6o1zH311M2lzf+hCsAz55CD/wAQ4kEtMP3fsRfvi8YSPe13y18VbSUaWHo32KpaVpLyRWKGeWFlDHOiwkc4VNygsywYVy/9CHplbCoUEKMP+KCcNBxiD7sAzzCGCap1YLh+NOjEQNyuuaMVha2g4zNz3n9hkWnQA2yUVY3tbdi/kSIlB761/OujOicOni3MxPsywsRgwMSe2JKsDbhhIL+f1C0+ntO1NXAFOOJBFZHsuT4IiqfiZE9N3RNaY6snWW4x7pa3p79VdsmzBAz+fwP7a38zWXyL2xyU4xx16Qmo0YcODxXqFs44B0kSCckK1eEctkcMHEMR7KE/fk/lQbot2KrvBs6iPUMhgxkd9jbgd3JhBEuSF4vCfvRLkypKEHF9lywNDpo5jnsOYZAqabWUchkE3v1psWQJu2Zd3s2iKQ2QO1F4AI5sYcrXhb8b+BY9RewKMWHPslm0wTnifp1A== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: R7Vu62Rha+rW6dqkHMd47qx/6NNgfChppmUhvGB/ddJ/gzDQAvA36sBUVgc3wsVxK2EmS5NFT7Az/bNncJGJ/l92Sga6s1L7llSaFn+BMfdRCU+Rb+idcxk03iHw25Zl2OZwvV0M0E+zeCBKmVm4OJAxC4g5k0YB5szLEVPsDATSpnDv53vRVfTST3rDz/BAzzYynmUXzQgNL28qEv26H12Ilt5L0bMgdXUyv7zjr4QCowr4oMty4Q7Ce6XZBtZmUw2C0F+zP0QD9Hadv0CHcKdSQCni9N8dTGgenUeOjTJ4/N9LDLBLXzurnsYnw7tHryScijQpn2qV5AxOAgIl4Ncc5z6P8A7EssnrDNaVMCZU8cE9GxKy/yZQlV0YlhYNJTGZpQNu4tjjsCdJdZkFIw+9iCW5IOr+kKA57VvvHZNnccWOC1fQ05iHoCqPkZbG X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:13.8661 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 11b10a4f-857e-4635-7eb3-08de752519df X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8902 Received-SPF: permerror client-ip=2a01:111:f403:c000::1; envelope-from=skolothumtho@nvidia.com; helo=BYAPR05CU005.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103184837158500 Content-Type: text/plain; charset="utf-8" Stop walking the object tree to discover SMMUv3 devices when building the IORT table. Use the SMMUv3 device array maintained by the virt machine instead, avoiding recursive object traversal. No functional change intended. Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 70 ++++++++++++++++++---------------------- 1 file changed, 31 insertions(+), 39 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 544004615d..ae78e9b9e0 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -385,49 +385,41 @@ static int smmuv3_dev_idmap_compare(gconstpointer a, = gconstpointer b) return map_a->input_base - map_b->input_base; } =20 -static int iort_smmuv3_devices(Object *obj, void *opaque) -{ - VirtMachineState *vms =3D VIRT_MACHINE(qdev_get_machine()); - AcpiIortSMMUv3Dev sdev =3D {0}; - GArray *sdev_blob =3D opaque; - AcpiIortIdMapping idmap; - PlatformBusDevice *pbus; - int min_bus, max_bus; - SysBusDevice *sbdev; - PCIBus *bus; - - if (!object_dynamic_cast(obj, TYPE_ARM_SMMUV3)) { - return 0; - } - - bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); - sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); - sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); - pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); - sbdev =3D SYS_BUS_DEVICE(obj); - sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); - sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; - sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, 0); - sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; - sdev.irq +=3D ARM_SPI_BASE; - - pci_bus_range(bus, &min_bus, &max_bus); - sdev.rc_smmu_idmaps =3D g_array_new(false, true, sizeof(AcpiIortIdMapp= ing)); - idmap.input_base =3D min_bus << 8, - idmap.id_count =3D (max_bus - min_bus + 1) << 8, - g_array_append_val(sdev.rc_smmu_idmaps, idmap); - g_array_append_val(sdev_blob, sdev); - return 0; -} - /* * Populate the struct AcpiIortSMMUv3Dev for all SMMUv3 devices and * return the total number of idmaps. */ -static int populate_smmuv3_dev(GArray *sdev_blob) +static int populate_smmuv3_dev(GArray *sdev_blob, VirtMachineState *vms) { - object_child_foreach_recursive(object_get_root(), - iort_smmuv3_devices, sdev_blob); + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + Object *obj =3D OBJECT(g_ptr_array_index(vms->smmuv3_devices, i)); + AcpiIortSMMUv3Dev sdev =3D {0}; + AcpiIortIdMapping idmap; + PlatformBusDevice *pbus; + int min_bus, max_bus; + SysBusDevice *sbdev; + PCIBus *bus; + + bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", + &error_abort)); + sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort= ); + sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); + sdev.base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + sdev.irq =3D platform_bus_get_irqn(pbus, sbdev, 0); + sdev.irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + sdev.irq +=3D ARM_SPI_BASE; + + pci_bus_range(bus, &min_bus, &max_bus); + sdev.rc_smmu_idmaps =3D g_array_new(false, true, + sizeof(AcpiIortIdMapping)); + idmap.input_base =3D min_bus << 8; + idmap.id_count =3D (max_bus - min_bus + 1) << 8; + g_array_append_val(sdev.rc_smmu_idmaps, idmap); + g_array_append_val(sdev_blob, sdev); + } /* Sort the smmuv3 devices(if any) by smmu idmap input_base */ g_array_sort(sdev_blob, smmuv3_dev_idmap_compare); /* @@ -561,7 +553,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) if (vms->legacy_smmuv3_present) { rc_smmu_idmaps_len =3D populate_smmuv3_legacy_dev(smmuv3_devs); } else { - rc_smmu_idmaps_len =3D populate_smmuv3_dev(smmuv3_devs); + rc_smmu_idmaps_len =3D populate_smmuv3_dev(smmuv3_devs, vms); } =20 num_smmus =3D smmuv3_devs->len; --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103375; cv=pass; d=zohomail.com; s=zohoarc; b=Q5H4k8DO1lcW1HWcY1fHupvTtbsMNpAL9ATC7lVRm/v6SCCS8u/4IvXCJEUNSh5WtsBTLxxU+IfqjvsvPiiYyCKp8NHDEe49vYTI3QVdlgN+fsUUq8vzx1YfrOEYcH5OujYhzoZ0T1U47OUry3bHhvBp4XzYURxoxDmokXrt9hM= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103375; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=3Nhpj8HDxl0SQlqEKRkF71GPgaU8fFmL1l2Bj5a7IwM=; b=oDPb2xC7pqraBrX4msF9r2csKLcydChnF5acaRd/jFwIeNqXTBzB6g44kdJqoAcA9hPWA7hE9quXfwyQQ+Fkyrl9wSWFcxGdDToplb3fPiLTYwHfoUBPOlveuI8w9juWZSNVdFBlB2haRfuAbS51pauuA4S7yVOAGMa6ObubOP8= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103375181312.5833359776984; Thu, 26 Feb 2026 02:56:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYyx-0004Xa-ON; Thu, 26 Feb 2026 05:52:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyv-0004TO-Np; Thu, 26 Feb 2026 05:52:33 -0500 Received: from mail-northcentralusazlp170120005.outbound.protection.outlook.com ([2a01:111:f403:c105::5] helo=CH5PR02CU005.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyu-0000lg-BZ; Thu, 26 Feb 2026 05:52:33 -0500 Received: from SA1P222CA0103.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c5::7) by SJ2PR12MB9139.namprd12.prod.outlook.com (2603:10b6:a03:564::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.22; Thu, 26 Feb 2026 10:52:24 +0000 Received: from SN1PEPF000397AF.namprd05.prod.outlook.com (2603:10b6:806:3c5:cafe::5d) by SA1P222CA0103.outlook.office365.com (2603:10b6:806:3c5::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:52:23 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397AF.mail.protection.outlook.com (10.167.248.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:23 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:03 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:00 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=KhqxeZz1PSxg8q78YS5I+oz5km355qIQWoj0/MSrl316GSpvSMZmYfb2pPaM769i9XlMrrO7vfMCKd02u8nEaLJS7lTKKQbeKcMYsoIzom5dtjQajZhdJy9pKPNO7qWF1M0lnZmmnlfE9mismLhpXlb6XuZZL/yNkAIOxQ8f3HdptUrKQS//7bfkX3ir7kJ75gpfB8WVl4GUo89K1XmMKHS1cyXCQNgPdTvlidQ9M9WmOt0eLBeYZ0JobXilyoFC1iYvAGJypndh/HZcMPkkSE1XJrsrYXF53c1DxCSYRE8efzRUY0puoWFTqzRJdVUEEaFwcb5NGfCFYdiDoOFaYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3Nhpj8HDxl0SQlqEKRkF71GPgaU8fFmL1l2Bj5a7IwM=; b=nb0f6FiGwsghANy3BvgUjbgFa0MREN5tneDA4IZh9KT5o8NSYwbERqX1l4/vcpJtV0jcDTOwUGhbJDWX2CFvnLeGZWVu2zNcMSHO7DHK/b3rOdmBaTa0rF/O90u52IM3au1Vo6T2MBrX3tvUxVoHMud5CKpj1gdLY9mPOlRRKOhDpnyzArcUq6YtN4iyHCylCp3mh3cmSCIkDx3TAnMdPKWCrXT4Z6hX9rxTCQJ451oMQPv8cBvMBVzSPAUtPkm5H4mzEbJN9Dn0hMBSKW8bvakzKbiEOm9kxWkzGumQcyKQnXCFVw0JsyOxcb2k3j/WUD5aP5fhl1Nud3YmwjHJBw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3Nhpj8HDxl0SQlqEKRkF71GPgaU8fFmL1l2Bj5a7IwM=; b=CMrtZd3ZSlgLjvHekhdOrhOszIkRcXHj4mYYCV/rXdR9CbtwU7Lowe0hex5a1XUn0LzL6wFzT8Dw1YC24WFL6c27omtzWHK6E62xyKnhHF+xYUXIXfasmYqDsAG/WuGRSenBIFuag8/D2OwgoC8zrYQzwTkZZ0JCanOW314UBwIYpE3gOtODd6uCzkH47LEL+RgjxXX5NqW68a7CfYSTvySdJxdAlF7TDBersngzrNbBlYiSAfI4U3cUy9w7P8JIdFplKCE59WfX1cPmPJpw6tg9vPkkK3FhtkZKdRkVrWpAeCspBZvnHqf19FlLUx43MHLRtsFWvoWSita959JTSg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 10/32] hw/arm/tegra241-cmdqv: Probe host Tegra241 CMDQV support Date: Thu, 26 Feb 2026 10:50:34 +0000 Message-ID: <20260226105056.897-11-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|SJ2PR12MB9139:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fa59e04-2e9c-48ba-af2b-08de75251f55 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: jMkwLw/2egt03tLKmnMytsVjfnssOsO2HalCAzi2ItspQKZCEVjvYCZt8yrA+XmWISVg9tokj9xTX8WpcYPl5Sy4Ytoi/fhLAcR9J8SK39jLmbts9arOf+jl6BMlFz5zKgbQzwVENxF7Wa+V5wkbb86sTQDbofnm1gceYSSAupftVUygs1DTcYFesyzjRzMofH5lXY4kxauHz6YC8f1pyx2jjv6QQSu9Y4i732ceb0KKwLiwyJINTgF+6y6UQfeLe5/6KAsSOO5YnN/nlBCt6MG1tqXoCrbO2A2KY8n8qCIgLPcvQpuZhl3M6u/4Tmct/5Mqks6pMmO2+40SMhu/qShrzT9waQI7pvmJ4gIP90AbWE0Eh5a7azml3Zsjc+vdjwDvj6DUXs5ssED5ZBjOZqb2N7suZUESHRpXdXVHcyY9pvCR8fxMTXLJiuYBnj9+BI3Ax0BUAgFlANfoh7MoE8ft3KBVk0w2U5F3JMJ7SaOhG2RrazcjGduP4ZEEgJPGWH2IKRE52RSYF379WlG4JCseFu3zzoBPNUfwau2pXmQSilNaN0E1BVltI7Xw7cSpKl3e/Nnyr2nmCjOra6AA5UevLheG1JfA/Ev80FzfyZp6y5WTWtGKKtDveTe5TS8cbSeQq4i3sa/osKCQfY5y9MdZUdwc8IefzmKLfq0kqemTYD8CDYYrE5ZwPsht55lZNTcQkQqRJzHAG+Nr5ke3P5nYJY3LSQWZnrGQOhSRuGIalQA/CJ9bGALYYS5qE/5ow5aBeeaXbKhGRlLzlNqmsxOw5pIOeV134CadBsvBzqDDsTdNBhr+6ffF9bOylsVWwysAh0+0754Yg3PciVCRPg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: DQcgROlUIz+zU85Ujl00olsaR34WQyILtFru6sOgrPd53iSect6mGBbyLk254ran6wdEnpgWUJJLkwXH4BpQAI2yI0eKdpPGhfkvcYrU2TTMhAX2xhvxpQvn4aWrZyVqZwLcPLjnhvBpcmL9W6gYHvi/AwB4s4k+pA+yR0AixJeT7vK3OKUm/IEmEre78tez9E6hmeEI3OxENskmKFrE1qv1HyddrVlfGLCWjket1qFxLIL/OVrhQ6+xgzdTCjSTSOqogXnOSA34t3d+JGmmZ1Xa55dc9OqvhKyQPpF85RZUa1DOHDt/zp4z1gW9s67mBaAP7OUVoh0/GaR55EygqqxBBQAW/0J+Fvpx1CmXiB48ZkneLzCfdoDLDB5WWVa7yp2iBrhuW0BOsdyondzreQw49kcNwU/WSTzBQ1a3aA2rKt3DykzzEMkv1e/rmZjT X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:23.0313 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fa59e04-2e9c-48ba-af2b-08de75251f55 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9139 Received-SPF: permerror client-ip=2a01:111:f403:c105::5; envelope-from=skolothumtho@nvidia.com; helo=CH5PR02CU005.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103375722158500 Content-Type: text/plain; charset="utf-8" Use IOMMU_GET_HW_INFO to check whether the host supports Tegra241 CMDQV. Validate the returned data type, version, number of vCMDQs and SIDs per VM. Fail the probe if the host does not meet the expected requirements. Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 5 +++++ hw/arm/tegra241-cmdqv.c | 32 ++++++++++++++++++++++++++++++-- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 07e10e86ee..312064a081 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -10,6 +10,11 @@ #ifndef HW_ARM_TEGRA241_CMDQV_H #define HW_ARM_TEGRA241_CMDQV_H =20 +#define TEGRA241_CMDQV_VERSION 1 +#define TEGRA241_CMDQV_NUM_CMDQ_LOG2 1 +#define TEGRA241_CMDQV_MAX_CMDQ (1U << TEGRA241_CMDQV_NUM_CMDQ_= LOG2) +#define TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2 4 + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index ad5a0d4611..a270fa7ce4 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -38,8 +38,36 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error **= errp) static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + uint32_t data_type =3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV; + struct iommu_hw_info_tegra241_cmdqv cmdqv_info; + uint64_t caps; + + if (!iommufd_backend_get_device_info(idev->iommufd, idev->devid, &data= _type, + &cmdqv_info, sizeof(cmdqv_info), = &caps, + NULL, errp)) { + return false; + } + if (data_type !=3D IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV) { + error_setg(errp, "Host CMDQV: unexpected data type %u (expected %u= )", + data_type, IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV); + return false; + } + if (cmdqv_info.version !=3D TEGRA241_CMDQV_VERSION) { + error_setg(errp, "Host CMDQV: unsupported version %u (expected %u)= ", + cmdqv_info.version, TEGRA241_CMDQV_VERSION); + return false; + } + if (cmdqv_info.log2vcmdqs < TEGRA241_CMDQV_NUM_CMDQ_LOG2) { + error_setg(errp, "Host CMDQV: insufficient vCMDQs log2=3D%u (need = >=3D %u)", + cmdqv_info.log2vcmdqs, TEGRA241_CMDQV_NUM_CMDQ_LOG2); + return false; + } + if (cmdqv_info.log2vsids < TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2) { + error_setg(errp, "Host CMDQV: insufficient SIDs log2=3D%u (need >= =3D %u)", + cmdqv_info.log2vsids, TEGRA241_CMDQV_NUM_SID_PER_VM_LOG= 2); + return false; + } + return true; } =20 static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D { --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103333; cv=pass; d=zohomail.com; s=zohoarc; b=cvJSEWwH0mco+D643ol7RTZ0RfiigvOd3EbDs888sKoKxPKc0LYLrYU8efza1P9zbROHb6zIw4hiZ0UB+CNjkvtM/xsqTDiJcs2mHBhMQSD7QYehZL4lVdW6NqON5LWZokSITWTWF6ACM78Nx+DCw05HdYcIBo+8MK2fE1M0pIs= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103333; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MVEa3osZWa1dJAq0UCK1z7aAjEv4m8Xc2nH1snTADKs=; b=LCtKZdENvD+1ruxkG3TkvanFZldk7WB8ZAxEutW8/0V4ABwEB7YyFESwRSIFZoLYXJW7CMnxz012bkp1mm0PfbqDZUwFoKuXkLUDlVskhFGOWicUAAPX540GZK/ivMlZZfz5dt5E7pUBQQql493dl8hwv1tN0Wd/h4QBIffn4tM= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103333827624.7211741044259; Thu, 26 Feb 2026 02:55:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYyw-0004Te-3s; Thu, 26 Feb 2026 05:52:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYyu-0004RQ-70; Thu, 26 Feb 2026 05:52:32 -0500 Received: from mail-westus3azlp170120001.outbound.protection.outlook.com ([2a01:111:f403:c107::1] helo=PH8PR06CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYys-0000l9-G5; Thu, 26 Feb 2026 05:52:31 -0500 Received: from DS7PR05CA0038.namprd05.prod.outlook.com (2603:10b6:8:2f::23) by DM4PR12MB7549.namprd12.prod.outlook.com (2603:10b6:8:10f::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:52:23 +0000 Received: from DM2PEPF00003FC2.namprd04.prod.outlook.com (2603:10b6:8:2f:cafe::9e) by DS7PR05CA0038.outlook.office365.com (2603:10b6:8:2f::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.22 via Frontend Transport; Thu, 26 Feb 2026 10:52:23 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC2.mail.protection.outlook.com (10.167.23.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:23 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:07 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:04 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=szxhX11a5Oe00FJl2/7wSo1s3qt8t0NViSSih4AU9nVwTax0AuuYLk5ocWqAK12mrOnbf9aqTVTp2h2R5bwHZCN6OCw+3t+Bp46+sHFPo45cGuRsgQj+pD8cEKfC4HBILueIKT1vuBYdRyorrtnKg9oHD5Qp3YIbOCRWsiXGvExRa1p6KGQJTAus1aoNC5fIjPMzSRis38dE/3eVrn8jNGQbfn9mtUuMWsvPQ97W+9moSNncEHrdajhpqGTLKuoe/IPLQFhtlk9Z9JEmAZO0GV4PO7OzMnESi/KKpsqyK5nnjci6aRtleEIdqE5cnXiM0xX8W5CnQdSRfkhrXguz1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MVEa3osZWa1dJAq0UCK1z7aAjEv4m8Xc2nH1snTADKs=; b=FXw3tfSGVNIX9KDNjUOOrlb3xEt+hK+J1K7MxEWuA+/kZlEXbWWkubJPyri3aBNsPF63ri+//EwH9gOykfSlWt+OwUT1Oyqfz6qiAaDUzVNEnESGJbwrvyjLxyUNN7Ni74ldCY2NdMvOxzBz2aJnrObbFaBTNNaVy4ar1lezPChSo7V0zbk0+qJ6GQcam6mwT+hKS97y/ChJ2sfEyxu+TI8BXmJA+cc+h8/FYGL5uH2SAfm8DZPFN4J0+6TvW3FsBcjcF8vSwLyqDZJn31tCuFmEGqecNGEJFADObPZP4xbgBfnDtbILC2VUMeE27bdcYLPmkZmXfg2tEqhglTk9AQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MVEa3osZWa1dJAq0UCK1z7aAjEv4m8Xc2nH1snTADKs=; b=badpoZFN1E0baojzenV+pNbdnxqWC4VhfFa/IDm6iklWSUsHM/G9kleJSHeJu8Q2kwkVr20rP5q8Y5GUJkOeK8rrL8adS88MR0lfjlvs2wKhycG6u9QnCFqBpDohIh8pPdP8qAwcIHWEK0rRp7OpV8c6sEu38yHq//prVxw1QjiMjgtsYqJkzpz+HPgBZd7H/sdF3+epLiqRKndY0jDmwOWjh4jfQJ2H6gJ3BN6Qhl6KFAuV6OuQ/PrWv0uagJRYw7+k1KbGebfHnsLOQYOzxBS7V8X3gJSKZmh0heT1OaRkMWPrV0D0ktY2g7UKys6yjoW2R4ct/0iVh8xmIcjUhw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 11/32] hw/arm/tegra241-cmdqv: Implement CMDQV init Date: Thu, 26 Feb 2026 10:50:35 +0000 Message-ID: <20260226105056.897-12-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC2:EE_|DM4PR12MB7549:EE_ X-MS-Office365-Filtering-Correlation-Id: a1eb7206-0811-4f58-9e21-08de75251f6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: 76JA5euw8YJs0irStKYRK5mKrvfNYoUu1bfj93z8D5sN1+uPO0tJqshkial8d3AuSKm0nhp4SiO/N70uWw5q7HkEXK+tnJUxbGqM3iJTXqdrSiR046MGf81AgoFIrfU/0q1VofMWUOKkk1rLzkwqTBoH5ppOCG5qHy/ASJjcozDgkCpH4UhT7aQ5MlHsbL3fjsvo27nihIYsZIF5ALEd1Mi1TqBlUVWJSzEUnQaQ5GMD+C3vVpyizazO3ifOdQsMx6bx4p3IYCAxesAkjrMjSkhjdiuKLGKTR2HjkEnNJtc+xq9P3h/OyAST6R8sfhCSRxyK8TFzX8L8OQGSYUo4QYF46bmKsDSoA65lPu/UEFps4nRg4aEu1XFQgNyUpUxs66Kn2pbWkuhIlQ6tdz3TwYbCpHyVdjLbK3H6wIR2ZwNEzbdVA9nCJUmwWxsXeimViXQuwMhNkpRNS3b1uUWOO3Jcs2T/Zk8cK5Q/ogGTmt+V/llQfCvj4uQzaW7+wI0SBvUgLRRHV65yM9Kh/64ba0Q8fBZ5LGCh6BRDiB44tFWbTNU60uqP6JpSaS/uiPem+i9uWtLilNwsLOi/WNAryivo+s4qWimBMneb70LchSFBNd0RGyQiV2PBCfeBWVPwQVXUySY4cfHRyP46P2vBzzo5j2XQDdWlzmM+X9o53a6mgPpXqnSHwIf5xQDfh4Em8e02lYLA2yd3QuTmCVNBTdIznpCd6trrF5S58CkVHBvIfA+h4FRaahLEP7pl3RlrWKb38VnFw/Usm9aBuWUZO/mAL/OwiM2kV3V2JCFQdsKBQRIOlCEKK8XgIVvy9O/bnvA4OtgdaU2qNNvk5pge6w== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: +g/EUu8zN7lKzA+8cBsGo6uipSi8s1vJWr9Ilk3yJkyuv+pH8iw/Qtu0aIlYfjnntGe6lEVQZEwtPrAxw4cTEw2JLlIzWUUhkNBtfQJsiIFdxJOtLfCnyT0jM6qh5FnAxHvBklSiEXoYi2CC6egdBAzvLu49958M7MccYLkUIgkX9o3R+SgBIk4iFodED3JGL309vwfWYLZ3i/Cf7196Aa7H+5BwJ+4+duMUf5bknlSIyFoq6J2bPett3yl2YATgX1miYHD6cWoOIIUpapHOzvqQ6uy5m7PsryIimmnWb6nRJL967zupB7Z2gaeDuTs8NWTkXbNHOT1xDUjDNnPncNKumETL8qjCxyYWva0O+JIMPXWWFYBAo/s4D3h2TlQQjIV3edk32qJbC8ZAwqD2pd9CyoNzFNyFUI5/lKWNeqzg2vvRYbuTSXGgUCAHJg3v X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:23.1884 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1eb7206-0811-4f58-9e21-08de75251f6f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7549 Received-SPF: permerror client-ip=2a01:111:f403:c107::1; envelope-from=skolothumtho@nvidia.com; helo=PH8PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103335560158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Tegra241 CMDQV extends SMMUv3 with support for virtual command queues (VCMDQs) exposed via a CMDQV MMIO region. The CMDQV MMIO space is split into 64KB pages: 0x00000: Global CMDQV registers 0x10000: Global VCMDQ registers, Page0 0x20000: Global VCMDQ registers, Page1 0x30000: VINTF0 logical VCMDQ registers, Page0 0x40000: VINTF0 logical VCMDQ registers, Page1 This patch wires up the Tegra241 CMDQV init callback and allocates vendor-specific CMDQV state. The state pointer is stored in SMMUv3AccelState for use by subsequent CMDQV operations. The CMDQV MMIO region and a dedicated IRQ line are registered with the SMMUv3 device. The MMIO read/write handlers are currently stubs and will be implemented in later patches. The CMDQV interrupt is edge-triggered and indicates VCMDQ or VINTF error conditions. This patch only registers the IRQ line. Interrupt generation and propagation to the guest will be added in a subsequent patch. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 1 + hw/arm/tegra241-cmdqv.h | 18 ++++++++++++++++++ hw/arm/tegra241-cmdqv.c | 30 ++++++++++++++++++++++++++++-- 3 files changed, 47 insertions(+), 2 deletions(-) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 5bdd01afb5..7d6e4c6b76 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -42,6 +42,7 @@ typedef struct SMMUv3AccelState { uint32_t abort_hwpt_id; QLIST_HEAD(, SMMUv3AccelDevice) device_list; const SMMUv3AccelCmdqvOps *cmdqv_ops; + void *cmdqv; /* vendor specific CMDQV state */ } SMMUv3AccelState; =20 typedef struct SMMUS1Hwpt { diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 312064a081..46aa9e8a9f 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -15,6 +15,24 @@ #define TEGRA241_CMDQV_MAX_CMDQ (1U << TEGRA241_CMDQV_NUM_CMDQ_= LOG2) #define TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2 4 =20 +/* + * Tegra241 CMDQV MMIO layout (64KB pages) + * + * 0x00000 TEGRA241_CMDQV_CFG (Global CMDQV configuration) + * 0x10000 TEGRA241_VCMDQ_PAGE0 (Virtual CMDQ page 0) + * 0x20000 TEGRA241_VCMDQ_PAGE1 (Virtual CMDQ page 1) + * 0x30000 TEGRA241_VINTF0_PAGE0 (Virtual interface 0, page 0) + * 0x40000 TEGRA241_VINTF0_PAGE1 (Virtual interface 0, page 1) + */ +#define TEGRA241_CMDQV_IO_LEN 0x50000 + +typedef struct Tegra241CMDQV { + struct iommu_viommu_tegra241_cmdqv cmdqv_data; + SMMUv3AccelState *s_accel; + MemoryRegion mmio_cmdqv; + qemu_irq irq; +} Tegra241CMDQV; + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index a270fa7ce4..6959766129 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -13,6 +13,16 @@ #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 +static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned = size) +{ + return 0; +} + +static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t val= ue, + unsigned size) +{ +} + static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { } @@ -29,10 +39,26 @@ static void tegra241_cmdqv_reset(SMMUv3State *s) { } =20 +static const MemoryRegionOps mmio_cmdqv_ops =3D { + .read =3D tegra241_cmdqv_read, + .write =3D tegra241_cmdqv_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + static bool tegra241_cmdqv_init(SMMUv3State *s, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + SysBusDevice *sbd =3D SYS_BUS_DEVICE(OBJECT(s)); + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv; + + cmdqv =3D g_new0(Tegra241CMDQV, 1); + memory_region_init_io(&cmdqv->mmio_cmdqv, OBJECT(s), &mmio_cmdqv_ops, = cmdqv, + "tegra241-cmdqv", TEGRA241_CMDQV_IO_LEN); + sysbus_init_mmio(sbd, &cmdqv->mmio_cmdqv); + sysbus_init_irq(sbd, &cmdqv->irq); + cmdqv->s_accel =3D accel; + accel->cmdqv =3D cmdqv; + return true; } =20 static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103442; cv=pass; d=zohomail.com; s=zohoarc; b=Aq8v4Xxmy2XAEBNJcrBWdK6ZrdSH1o3GXFmRPoNQnr4qR9lPbfNvEB4QgKYnXIgaCCdI/9ltc/bhPoIT5opevt7Eo5u5wY8nQaMtIWg//Y76ZoiX6kMXGnZddKz3m4uzYo/ySYhcxGAhbYj/gGFS1Z6ka8Ccs0M7Q0uPeiiv1L4= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103442; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qH1RaeibYDkJ5ZRNRJpc87DXVbALmF1hyEOhxcJ9AOI=; b=FERTef8LvLaTjOZvgANacKQ7ABtMuejffj5yrzpC8DkTqe4i0PDwBZyuOWgL6aJF5NQxp8dXGGza0V/OIWdwxk2QpVPLrGihLQbgngxP7sMgfC7aaUdgQH24XFHD4gN+Hga3uAjLr6HYubnBz9iK5UV71esFTbeXxK47LbAl0t0= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103442872815.5543539692794; Thu, 26 Feb 2026 02:57:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYz5-0004gg-72; Thu, 26 Feb 2026 05:52:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYz1-0004cJ-DU; Thu, 26 Feb 2026 05:52:39 -0500 Received: from mail-westcentralusazlp170100005.outbound.protection.outlook.com ([2a01:111:f403:c112::5] helo=CY7PR03CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYz0-0000mU-3n; Thu, 26 Feb 2026 05:52:39 -0500 Received: from SA1P222CA0125.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c5::19) by LV8PR12MB9641.namprd12.prod.outlook.com (2603:10b6:408:295::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.13; Thu, 26 Feb 2026 10:52:30 +0000 Received: from SN1PEPF000397AF.namprd05.prod.outlook.com (2603:10b6:806:3c5:cafe::75) by SA1P222CA0125.outlook.office365.com (2603:10b6:806:3c5::19) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:52:30 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397AF.mail.protection.outlook.com (10.167.248.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:29 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:11 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:08 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=PTvPLC/4rhRMb8fuvQnpp9tpTdfBcDfyjMorIZXAOGiehfGwc4ndqraxCnjxdVoAKl814QxFW9YvicASYYx8WsuETOqrKSNYAjv2xvcgpd5stLT9c55uC3mX0ZMGFm58twSTVSTcdRinsHYHVFIKgv9y3RhwcnvIpFKFpeQlHK2aaNxK5TNM9bXs7OgCSvJ9J5f+OtB3ra+MPMehXLTtPcP5fIQF8jFsuz6vgyJ9u6gPr7ezqrmBfV+DzmjizjUm2PkvbEhcuOdxhNhRrSqq6eWfFZm91RnzJgBSFwJOBar/waTr0vF+tCKshm1wm3Ehe0RUU6+6gHYAewN0RhQuNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qH1RaeibYDkJ5ZRNRJpc87DXVbALmF1hyEOhxcJ9AOI=; b=R/5otNqgqaRiZe2wQYRnOngGxZxF4Lok84UeVcCRER27pM9S73ly5t9plwc309gYDHcCeBe2+UOHllMU4UEZgB5HbfSwqiI/2t8Cpr7F1pPPIE3Jeh7BS1f63pLeEjmCEIZG4VEnIbsVuTHs6968pht2VgDfaJo1fO6Iso/iesYmOmFEphzjFigiqNspVpBErh3XG8CnQZYIMzr38dmBocUhcLn1m41cr7H3K4/Nyn8J6KGMu4KaLlqP/T0gmiV1RXDGAG8oAS9Xby3/8m9LWPRnkNMhH69TWU6QCfnj8i5NENvJR0ZczhJ4jFHgZ48jKZ9K192d5pq3Qijr06BAHQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qH1RaeibYDkJ5ZRNRJpc87DXVbALmF1hyEOhxcJ9AOI=; b=bHnxZWroswFFplWjmwf384kq9LgEoZcj3OiwpZZDeQXDyaeBEtFAaSCaz23Wb/LmUfJtidEIvKgQugohaFbeNn2sE8WTB/XjFkTsc0IyaL53qLrrtreIfQoFuuT2ummfoxr6aJKI/KM/VFDZYl2AXnzENZL/GIioMO6dGjCV9olVDgqGcvArBKfA5cenxMjoDC72iTdFm+6gTjkhl+jQjegAB+1tVFesukDcNJlBGgdcPgLlpx+0gX6m+H7Yw0rprPqgdDOqTcbXKhxAdARQcGceOwtJasTV4TXN5cqkMHnqwpBiItaMoyszsvXIRyd+iz+HMdDfQUgQVEhM4uaujQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 12/32] hw/arm/virt: Link SMMUv3 CMDQV resources to platform bus Date: Thu, 26 Feb 2026 10:50:36 +0000 Message-ID: <20260226105056.897-13-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|LV8PR12MB9641:EE_ X-MS-Office365-Filtering-Correlation-Id: 911d4a6d-3e1b-4f69-b197-08de75252338 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: 0REvlEKX4QgNpC/Utg+7ZWUKzk+6o2Dy6V3T+/XzhoLuuMT5Hr21xRXn8R+WjPfkoCZ0VIAT89m5sYzAwho+V/8GGcMvvuCQtUE/g/vsfH05F46tyxkDsu5/MWD1mz2L7p3uTM30vzCVSbdRyr1VmhEj2L19g8xdk3HHHkoKTSFxRj/bwm18Ozz/zm9Y68k0dhnaccFQhplwKVLVnvxZm2IjIDjedWCM7+fRkau8e/omgkb2sMrO0RL3qSK/ncEPty0GuHkBg7GxBPWZXkByO8GZ+MAsbbB+TETIAbaBPCOzsJ2dUykmDfVp0zWgv7sIU80gqFX5SWZbWTZSBpsqjz2hEdjQdT7jc2TKlwdd7I8fCQvdAwjcuocTt5gbw9u6mgH3/AcRJS7Vaiav8Vv7MJg8bMTo9U+TwysKh0HWI7kABq25mBeIJoKmeYuhDZs/MZqxjFu1PoZ1ps4+RBUMSRUDlQgQtgeYsZSqeATzknNjnEw2IXlh5d3tS5y+2XAV4y2Fa9xfXmufoCJXjkMNEgUhWDHsoaHyX9fq4Cgk91fjvfKXc9oj1bQHMM1HxHzXO3ab7lVIPZYfd7NQNK8OvFAhCBK3dZVlY1KY+9JBSApOekv29rowQa04pUyu4jevq2UJEnapGUd1TpGMxq9mtvqRmr5+pAxCu0Vn0o2diLNaPj9So8UTbPZEsZnDZF0Ptt9kP1JAn93TWmuDXVvCwJJVxLMcvQ9u+ZorviR1uEwCUteSB09tJuJutlSsVe4Hapuv1MI9hPeMgTe5/gyB9CPDDxdwenmTgcwj74V28z5Ne/LIWFipiolcXaNkZJ5yeuyMlj0iWJPvgyjpBp/vsg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hptKTS08k6UndM+tLXwOUtj59jJq7reCS6PYWYT3I76+aavWyjm9/Zej81Hr0PrAUICewLBu1dtRoUoup0+atvHLndyw3AXmHEfuw++N53Mv6ZcgsnxYsR/s/Cbt012iTFt9DvGEotnYI945MiRVBumYDKa+Km2YU7SRFKKr1BzFpQukFAYIt54G8hy2A4nH2v5rqAVmXN1pgCS99qGhTy5J2IaaOHHAiVzeNs1aGaz26/w8ygN1Pr70u462LrJLj2geJGwImELTDgCbtVrokQh8s+6oKkmz1ytzGv7HkWajKyQsP7i7QndQTd5DguoPGdm+VdbANtKaoGxB/X5f1rjTmIKHN/zoQyyy1Mtip8t64L1YTK6TEvgrefem6cXn+/brE96/oT51eocVab5OXcMFIPruH3jmNh9newFBhfGnIV2RWaOGks8RFz/TNZ0a X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:29.5818 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 911d4a6d-3e1b-4f69-b197-08de75252338 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9641 Received-SPF: permerror client-ip=2a01:111:f403:c112::5; envelope-from=skolothumtho@nvidia.com; helo=CY7PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103444151158500 Content-Type: text/plain; charset="utf-8" SMMUv3 devices with acceleration may enable CMDQV extensions after device realize. In that case, additional MMIO regions and IRQ lines may be registered but not yet mapped to the platform bus. Ensure SMMUv3 device resources are linked to the platform bus during machine_done(). This is safe to do unconditionally since the platform bus helpers skip resources that are already mapped. Signed-off-by: Shameer Kolothum --- hw/arm/virt.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 292e523664..c75a8d6e9e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1833,6 +1833,24 @@ static void virt_build_smbios(VirtMachineState *vms) } } =20 +/* + * SMMUv3 devices with acceleration may enable CMDQV extensions + * after device realize. In that case, additional MMIO regions and + * IRQ lines may be registered but not yet mapped to the platform bus. + * + * Ensure all resources are linked to the platform bus before final + * machine setup. + */ + +static void virt_smmuv3_dev_link_cmdqv(VirtMachineState *vms) +{ + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + DeviceState *dev =3D g_ptr_array_index(vms->smmuv3_devices, i); + platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev= ), + SYS_BUS_DEVICE(dev)); + } +} + static void virt_machine_done(Notifier *notifier, void *data) { @@ -1849,6 +1867,9 @@ void virt_machine_done(Notifier *notifier, void *data) if (vms->cxl_devices_state.is_enabled) { cxl_fmws_link_targets(&error_fatal); } + + virt_smmuv3_dev_link_cmdqv(vms); + /* * If the user provided a dtb, we assume the dynamic sysbus nodes * already are integrated there. This corresponds to a use case where --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103212; cv=pass; d=zohomail.com; s=zohoarc; b=MUyf66djF6UXzq67r5XQTBYVNNV4prWZ37ZmwKsKW6kO9A1Hm9ZgjHQ29MpCcV7MO04YqXQN5i1T/14UEftagFYnZeXdZPShC7rw7Xh5sLE7fW0CeXdgRlBuryfr4dIeHSKHpA5v6eGHcgeinXnfpixX9IUFnpqHLRpYi/lNpt8= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103212; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=twt2FCstt9zRAElw66KM2A9VTF6lMrPed16vyZoTctY=; b=KgoOG9Zm20N+mwX90CI30jXYOTQhdE9OI6cRNOezVI3I3xfm7ATgdcWfQB2p5/ZvPNWqb5x1LZt13Fgk+rxlJ2buHsC4x6ZSJpUvVtS03iUo0KrXeXW9ZfB3wdgsziwUxUOLVMXtrDG7DeiBmRAb/oVfv1YLoPctcdH1VnoVgJ0= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103212135103.57094914280015; Thu, 26 Feb 2026 02:53:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzB-0004l1-6Q; Thu, 26 Feb 2026 05:52:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYz5-0004gm-DE; Thu, 26 Feb 2026 05:52:43 -0500 Received: from mail-westus2azlp170120002.outbound.protection.outlook.com ([2a01:111:f403:c007::2] helo=MW6PR02CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYz4-0000n2-2b; Thu, 26 Feb 2026 05:52:43 -0500 Received: from CH5PR02CA0004.namprd02.prod.outlook.com (2603:10b6:610:1ed::21) by MN0PR12MB6319.namprd12.prod.outlook.com (2603:10b6:208:3c0::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:52:35 +0000 Received: from DM2PEPF00003FC5.namprd04.prod.outlook.com (2603:10b6:610:1ed:cafe::a3) by CH5PR02CA0004.outlook.office365.com (2603:10b6:610:1ed::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:52:34 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC5.mail.protection.outlook.com (10.167.23.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:34 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:15 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:12 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OZiOPZwmNzkngIWHc6+0VuQ6cfsYOAA1NQAwKebcT+72BqSlbCc2wA1stUsNNDkKfvLQjW8UDir3e/he2kR8PCkAsdO83zQ2hIFcsWXhaquzs3Ngm0ICaNAhUgvxkp0vncURvRvM2ruAHIGPw0dbGjDR3wZjL1rLDrfxxxERTSntzGeNLBteYqPbDRrK8fMGt5PC4tJV2dK7/buTazS0Kzc3OCAxi+rE+DHf8i7TmdXa6HfaQ4hmEkMefGJ2Vh1sh71dLCt3jJMDOyYnpq1jyONrxagZcKxnvY7oqI67gKub3VgRB07M+C6GOoxC+LGWq3rIxWuPTeRnf2/NTJ/sng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=twt2FCstt9zRAElw66KM2A9VTF6lMrPed16vyZoTctY=; b=ft4cgyTmBydU0LHNTRCNRZL6BodxB3LX5c9j5stoaDYEpB5I1ukk7FMf/TIRwEFHN5uZs85goA22XpsUzN1tWzoSOZUJN0QKAoW7GvVHnwdhnDzZyKdjxokR1FWM8xwBnVfVGiNk1m9duXV87jRmdFSAeVbbNG+mXrOQkfuSXHxaQDh8lGHpniz94PpVY+z5pl4b7rphprVYsoR4w3bSSzi7fLKHNlPD6KYqZbcTpZpfH/eRG4qiXs1mTnVaJhstRaRXdmU018ftVUeXgIxw1Gk6GaLxX5wGV/Q8ZlPqAPR5sdJpvc+YO1+eUbXrrpRYfdFDHyJG0TMK4xwo0SvaUg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=twt2FCstt9zRAElw66KM2A9VTF6lMrPed16vyZoTctY=; b=nGoolFR1WWvlHStUTf5vSL5iyirEfSt7Bcmu8gyqiWStroAV/futCaKFXrdQZSPWKIukYsdzk9whTFUWeN9Q63gL79HCu0KZ48rxml6/cjg4KmOtTkpxaa0k1k+7d5Cr0kSz8/MCbdfvcOvvNoU8q8d/3Jg9hlaUjA0rQ1JzlnYEFBEEmBi6Ax257eO8/b3HffatCkoboM5ktCOALO+DmRirrMiwd1CjL4pFbuTaX7DHilExGsy0nGwfnm5NgH1Fpid+JdkMzicyZZPl3H/RqXdhqflq1O0yjzqfH3oizSxvkbVG99c1QN0RxF6ZK1VxpNMLBcLBUIQT6Ogu95it4Q== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 13/32] hw/arm/tegra241-cmdqv: Implement CMDQV vIOMMU alloc/free Date: Thu, 26 Feb 2026 10:50:37 +0000 Message-ID: <20260226105056.897-14-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC5:EE_|MN0PR12MB6319:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e44c23e-d06e-4f97-ca38-08de75252630 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: teRPgF7LVDhs2COU1902HNoOaImQyRyAyVHN+3QaBOsAKBNeFD0SjqvA5Bk6E99It8y2wcnAjlBK1BrtO9MnZ+U8dZPfDXK6xX+UNkI8EW1cYM3+V8lfmM0UDn7WOP0D5NZTVctsQWuoLDUGmgn/foZz5cYhY26ZtfO2/OUnHlXN/v3pIYpEroO8EWTYhLZOCxaujZtozy2T9W4g3vZgjAZvnVKmrJYkXrPi1YLt04koHTiEM299h2Ww6CWK0qLjlugwx6ph/rfl+st86gHziqWd0xTB10uZ/rJCL9JoAZxAmOseaDfaWTaAeOUdFBXhqeslWVkCc+Dngh/t+ot3sqgoXfBRRDDKO2qqyIQ6E49ld1LTuzSWSjZXw+UdzHi55tc+IDsnXh9ZYDbhIK3jdUVZtRgPKYy3jbu8MZZgYShEc0QD27lii/+vGbnPJ/XVykzUivIHANd9TShgSb9mHF5WydfpkotFHiFQ6Tr91Kc8MejDimkbmfmLVE0lqL/dbDm7MEtu+SNZ+KDMiOIy0IEDDaqmXytADVHGIgcUSGS//Pk2l4qbVXpe1A3iQD/EGb8P5eHFnzjWfFj0az4tBG2msp3TMC/ijkxAZnUShOSH1AgXwpOk0lkB6IacUU6+2NzlJuiFpAkl0cPalP/7qR1aCB+/yukNnjsGkDJ1oMPaBxTwlaUH3Eu0R62cvVce/dZVHREn6maDygmcOqeAi/PnGpg3QkVRIBqweOv3Tdr4LICv9GnCQtKiYLnMMDKs33MUobIlt4kJJNcn4jnssVeWFq8l8mRbuDGOjTNGjY9JBxch0MQZt9sth1J6qeSDpoZIDDq8HDwwgduSCpZ/pQ== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 85gI15D70bDJzsoBBF0JOTn5r7FP2fSypbVLRwv9t8Tr43gdpIfjuu/7VisAK5iOdOAHMpZPuIth8iwdB+6oN591A04dcnVpAGhSIcOQvbQbLrD0iqKtObtToFwAXlm1lTd1jIoE3HP7Ubop91AYcN7M3yWjiiqAtte9IxTDPdY/k+JHA4/Jg79nEE0S4cOhEgtm8jCf61X3FyazH9Qv3XPystKzPkzFx+cKkrS8xGAPHW3pVxjopZvfpqVXbtGfNQZAqZo1+s0QIn3HtrYiNac6WrlLUnYrdIDWuIPe/oBgeTxjHI8MLpzAS3YJCgeuF5ZQKmIwL9jg5cIYWIzCjjvmnL/7o6jlUhVGvv+K14rPB3eOcIgr2i93tJ9ZUKjpeFyQEmOPatkWsBP6NYpVGLGS2SyDUJTZy5rpQ/r4PlG8EY5N8u7vwZoB9hKeSEu7 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:34.4811 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e44c23e-d06e-4f97-ca38-08de75252630 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6319 Received-SPF: permerror client-ip=2a01:111:f403:c007::2; envelope-from=skolothumtho@nvidia.com; helo=MW6PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103212912158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Replace the stub implementation with real vIOMMU allocation for Tegra241 CMDQV. Free the vIOMMU ID on teardown. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 6959766129..d487612ba2 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -25,14 +25,29 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + IOMMUFDViommu *viommu =3D accel->viommu; + + if (!viommu) { + return; + } + iommufd_backend_free_id(viommu->iommufd, viommu->viommu_id); } =20 static bool tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, uint32_t *out_viommu_id, Error **errp) { - error_setg(errp, "NVIDIA Tegra241 CMDQV is unsupported"); - return false; + Tegra241CMDQV *cmdqv =3D s->s_accel->cmdqv; + + if (!iommufd_backend_alloc_viommu(idev->iommufd, idev->devid, + IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV, + idev->hwpt_id, &cmdqv->cmdqv_data, + sizeof(cmdqv->cmdqv_data), out_viomm= u_id, + errp)) { + return false; + } + return true; } =20 static void tegra241_cmdqv_reset(SMMUv3State *s) --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103224; cv=pass; d=zohomail.com; s=zohoarc; b=Mh12OqyMfS15W3qNiea44+Dni65dx35UuDHxrJx9Z0aK+bN7gyKLAfcue2yk5TYBERGRQ1pEplC5pJAvj5U59uprEgnA/rfpU0OOaYrdHbR8Do4SKARuNCbWg1wbRBDtVdMR8XanJgBm2JnEPtf3mpOOMnjwmazzQtUEImJNH/Q= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103224; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=H7MJr8hE+NiZ1YM2RJVGGjq93xk7eb2xNmJkBASVDMg=; b=KiYc0yLNHCz4lZkCfMpBifhUTKcGwScDIb8RtzIacCSyA9prDRKWDFjUQ118m8e0QoCS/eraJP6Qw35h5AX93YYu3+47FhBOvyjrZU8+D23ixJNnZ051VpkP9pNj0c4Q/297TL44dpFQGC01KR4V6X25Ol9eKfJYtwgeEu42Q3I= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103224744464.3022856122532; Thu, 26 Feb 2026 02:53:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzF-0004uh-UM; Thu, 26 Feb 2026 05:52:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzA-0004l2-Ft; Thu, 26 Feb 2026 05:52:49 -0500 Received: from mail-southcentralusazlp170130001.outbound.protection.outlook.com ([2a01:111:f403:c10c::1] helo=SA9PR02CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYz8-0000ox-JX; Thu, 26 Feb 2026 05:52:48 -0500 Received: from SA1P222CA0122.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c5::17) by MW3PR12MB4427.namprd12.prod.outlook.com (2603:10b6:303:52::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.15; Thu, 26 Feb 2026 10:52:40 +0000 Received: from SN1PEPF000397AF.namprd05.prod.outlook.com (2603:10b6:806:3c5:cafe::ab) by SA1P222CA0122.outlook.office365.com (2603:10b6:806:3c5::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:52:42 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397AF.mail.protection.outlook.com (10.167.248.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:40 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:20 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:17 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=mot8ob2jXidJuiEmN4d0itZ57EDxePkUmZBOZXcGXrI/MYLit/SpV+iYs4R+tWZKLYWgmWIm+459vdX+/E5otPxpsFOMTExT96Ehi/fNZ9qxpGOXDSQqfRW4U35MZcZi/EgUfdIUS+6CFYNl5so/GA8ZiqCLLduTca9/QzTKvYqznuy4YE1nj63xhEeY6CyS/tKLX1jaoSSHArwMWwD1WAgJy+tY1PYXlmLmjXjsBHcqbRcHAOLJZkNjWulennXgCJsNpxwZmdvB2MkEMaS1X2+x6+izzJm6RpNavSyimaeBpPSGjLuVkgsuvLJurOlVG664+VbksRc+M9zCJebKvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=H7MJr8hE+NiZ1YM2RJVGGjq93xk7eb2xNmJkBASVDMg=; b=aUPnHadPCdaj3gGZS0kGLYjVZrKoj12UsO5xEEku6Z/ZjHIk6IsKQ00WODJ9NHaLopHjXejq9cwZ3QgW+D9euch9gzcKL/RBXChj6v3MxKsCxTeO6gwkT+yMPKYM/Q+Ca6Wp4mnWu4nMij/HoUQC+Ed41YGPxsRTLYOT0/+upSXss8BJxcOIP3hpibK6f29oZKrKIOS9NcjqH4hYF3UW9ezFZLpFq3WYfSDpdqUj8mFCpKkdr++/g7CXiZ6HwUbs9aeO1m+D003agYumRij7hRo8JJHN42ASz+Bq+CKpJlZ01LdfgFrPN62pkVQf3MEMegEhuQPOrOWV0DEBYvZJFw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H7MJr8hE+NiZ1YM2RJVGGjq93xk7eb2xNmJkBASVDMg=; b=hUsDXi+EL8lvPCJYrI6YWozHDK++3OncfmrQRXxkgqBzIBf5nE/UHfpnsum99Xg639EqyWYWlt62n3RPdi3y7yfjdKLOr9fYmYNp2ecw0sMek6Ikp86OMX9IV6U4UhkJ+Am4YQRDnOyxpwhQuH0H6rJ/EdgFdEKum7KF9yTzb8KWaUXv0T2j48c2v+VlzTbVzlPbncXZyxp4Zim86ed7CeG9RZm8eNrf8YDN6B3NLvLtxCo8AH2Qrw7snVKrjkOnEuCX9nS1nEYaQoJIsCAWSw9d0/Sl4TyCD5zHPhcDK0lTfXG1ewoY920cY00O2gOFquhTZvA6f8InNmWE4jKdrg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 14/32] hw/arm/tegra241-cmdqv: Emulate global CMDQV registers Date: Thu, 26 Feb 2026 10:50:38 +0000 Message-ID: <20260226105056.897-15-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|MW3PR12MB4427:EE_ X-MS-Office365-Filtering-Correlation-Id: 3cb61219-192f-4a4b-2429-08de75252971 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: CJct3TnnhU74eUlXd716CcZzGxSOW/Z82dasQGkL51u5Vs/p2x80eZxVfkroaUhQMjjEVfBVLqPaT6OP9c46ftU500NsukvWq1dr898sOyQkcbui2q5URhOIJQsKSKaU+w1GftKlgEInWNxaNhrP0WeGVcgMF22Eq0/toH3OUlMyQX1mg9odWV0pnIP0jQc8r9tsblKcIM0bBte6O9P9OYZkHQaDLdICxDfkwjreDPx8nCZCnG+GTCQZsr4PYoje9NGWPSuEmZxYNmpkOH8MW7UVEkVV1vl1KaV1F5izbNElCYWIp5aFmZECLTOYsiUwEOYmDN32SJDK4WyhAOfOMzs/2JoR+d0iC5p9+/PjEI5voXAQ0Mgjg1opPbo2PZ9q2+1uAQHpsFq7/65fQER8IjZnEXeGX0x7K4eJY3Z3U2Ax4GWdrFRBTcGZ7g2p8ET/dIcAsgUYHjU6kokx3kmKZGoLpMdtefkFJ85wvpX3sWqMjIqTmk5Q9NWcWamwyUTpA8S8Cju19zhYe9l/IImfsAkguFm73ILSM//npG/64NIw/sn0Shekc2KNigq20b78UI/lewUQwUqBHugRqeUxu40HylASDQuQB66TLo39GN6lGnnuz2p4tLYnwMIRPauW74oA/Hay11RL8QuHJEA1IgPu+JW1dcutnG96K/X31WoCojDpOd1PhS4XhV0ga2NEk9MTTn0ogu4IYfZFlBGcaT5wHCObrVvegFa6Kxt+DSSTB33TCNP4UcVU51oGVoOpXQXk/4raERpeowmDeOzzPP1xnfxdOIHIsrW/e2Lv4HuLEGhVM6y6ruEAgm4NpimwlRmRljKg1ApBdZjQVFHYbg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6nxkOFbpjr/G9bqz/c2esctLI0Z5Ph+NOjW9LxHr5HHeO7lpo1CtnWciHxJKT786jeLj0lpSSRM6IRu5HdAAiLU8VULrXU39zEFR+vGUBim3VGMHkZF1TupzQFHNHVg5HE0znpXtoLGSZqkI9h4E5jeb27A/3G6BhqacT1Gt9Mado5Ai6VolHSVs4ZEr2jFKmM9TkWw7H2z7PlhCl/OD0akKvWD83a8RSjzyP78XzhU2r2NqAR4YaDFqO03/56qnflszI/yHF1XpyxL7/y1ZUdKOl8OVjf1sgykXyYsWZdzwHhKBvBWm0N4uiws9G1pJ8P/RRtqnwm0p8vAzn++5p2Q70JtDpJWhwR2YiGsqn7vKU1bQpvyJtvAjWu1dTAyeLp3UOUmBAiJbbsT00MFKIOgkFOfbshNk7G0V/j1AyAk6NBxpMvKpymZj32fk4M0b X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:40.0562 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3cb61219-192f-4a4b-2429-08de75252971 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4427 Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=skolothumtho@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103225002158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Tegra241 CMDQV defines a set of global control and status registers used to configure virtual command queue allocation and interrupt behavior. Add read/write emulation for the global CMDQV register page (offset 0x00000), backed by a simple register cache. This includes CONFIG, PARAM, STATUS, VI error and interrupt maps, CMDQ allocation map and the VINTF0 related registers defined in the global CMDQV register space. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 108 +++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.c | 121 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 228 insertions(+), 1 deletion(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 46aa9e8a9f..50bcecee9d 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -10,6 +10,9 @@ #ifndef HW_ARM_TEGRA241_CMDQV_H #define HW_ARM_TEGRA241_CMDQV_H =20 +#include "hw/core/registerfields.h" +#include "smmuv3-accel.h" + #define TEGRA241_CMDQV_VERSION 1 #define TEGRA241_CMDQV_NUM_CMDQ_LOG2 1 #define TEGRA241_CMDQV_MAX_CMDQ (1U << TEGRA241_CMDQV_NUM_CMDQ_= LOG2) @@ -31,8 +34,113 @@ typedef struct Tegra241CMDQV { SMMUv3AccelState *s_accel; MemoryRegion mmio_cmdqv; qemu_irq irq; + + /* Register Cache */ + uint32_t config; + uint32_t param; + uint32_t status; + uint32_t vi_err_map[2]; + uint32_t vi_int_mask[2]; + uint32_t cmdq_err_map[4]; + uint32_t cmdq_alloc_map[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vintf_config; + uint32_t vintf_status; + uint32_t vintf_sid_match[16]; + uint32_t vintf_sid_replace[16]; + uint32_t vintf_cmdq_err_map[4]; } Tegra241CMDQV; =20 +/* Global CMDQV MMIO registers (offset 0x00000) */ +REG32(CONFIG, 0x0) +FIELD(CONFIG, CMDQV_EN, 0, 1) +FIELD(CONFIG, CMDQV_PER_CMD_OFFSET, 1, 3) +FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) +FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) +FIELD(CONFIG, CONS_DRAM_EN, 20, 1) + +REG32(PARAM, 0x4) +FIELD(PARAM, CMDQV_VER, 0, 4) +FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) +FIELD(PARAM, CMDQV_NUM_VM_LOG2, 8, 4) +FIELD(PARAM, CMDQV_NUM_SID_PER_VM_LOG2, 12, 4) + +REG32(STATUS, 0x8) +FIELD(STATUS, CMDQV_ENABLED, 0, 1) + +#define A_VI_ERR_MAP 0x14 +#define A_VI_ERR_MAP_1 0x18 +#define V_VI_ERR_MAP_NO_ERROR (0) +#define V_VI_ERR_MAP_ERROR (1) + +#define A_VI_INT_MASK 0x1c +#define A_VI_INT_MASK_1 0x20 +#define V_VI_INT_MASK_NOT_MASKED (0) +#define V_VI_INT_MASK_MASKED (1) + +#define A_CMDQ_ERR_MAP 0x24 +#define A_CMDQ_ERR_MAP_1 0x28 +#define A_CMDQ_ERR_MAP_2 0x2c +#define A_CMDQ_ERR_MAP_3 0x30 + +/* i =3D [0, 1] */ +#define A_CMDQ_ALLOC_MAP_(i) \ + REG32(CMDQ_ALLOC_MAP_##i, 0x200 + i * 4) \ + FIELD(CMDQ_ALLOC_MAP_##i, ALLOC, 0, 1) \ + FIELD(CMDQ_ALLOC_MAP_##i, LVCMDQ, 1, 7) \ + FIELD(CMDQ_ALLOC_MAP_##i, VIRT_INTF_INDX, 15, 6) + +A_CMDQ_ALLOC_MAP_(0) +A_CMDQ_ALLOC_MAP_(1) + + +/* i =3D [0, 0] */ +#define A_VINTFi_CONFIG(i) \ + REG32(VINTF##i##_CONFIG, 0x1000 + i * 0x100) \ + FIELD(VINTF##i##_CONFIG, ENABLE, 0, 1) \ + FIELD(VINTF##i##_CONFIG, VMID, 1, 16) \ + FIELD(VINTF##i##_CONFIG, HYP_OWN, 17, 1) + +A_VINTFi_CONFIG(0) + +#define A_VINTFi_STATUS(i) \ + REG32(VINTF##i##_STATUS, 0x1004 + i * 0x100) \ + FIELD(VINTF##i##_STATUS, ENABLE_OK, 0, 1) \ + FIELD(VINTF##i##_STATUS, STATUS, 1, 3) \ + FIELD(VINTF##i##_STATUS, VI_NUM_LVCMDQ, 16, 8) + +A_VINTFi_STATUS(0) + +#define V_VINTF_STATUS_NO_ERROR (0 << 1) +#define V_VINTF_STATUS_VCMDQ_EROR (1 << 1) + +/* i =3D [0, 0], j =3D [0, 15] */ +#define A_VINTFi_SID_MATCH_(i, j) \ + REG32(VINTF##i##_SID_MATCH_##j, 0x1040 + j * 4 + i * 0x100) \ + FIELD(VINTF##i##_SID_MATCH_##j, ENABLE, 0, 1) \ + FIELD(VINTF##i##_SID_MATCH_##j, VIRT_SID, 1, 20) + +A_VINTFi_SID_MATCH_(0, 0) +/* Omitting [0][1~14] as not being directly called */ +A_VINTFi_SID_MATCH_(0, 15) + +/* i =3D [0, 0], j =3D [0, 15] */ +#define A_VINTFi_SID_REPLACE_(i, j) \ + REG32(VINTF##i##_SID_REPLACE_##j, 0x1080 + j * 4 + i * 0x100) \ + FIELD(VINTF##i##_SID_REPLACE_##j, PHYS_SID, 0, 19) + +A_VINTFi_SID_REPLACE_(0, 0) +/* Omitting [0][1~14] as not being directly called */ +A_VINTFi_SID_REPLACE_(0, 15) + +/* i =3D [0, 0], j =3D [0, 3] */ +#define A_VINTFi_LVCMDQ_ERR_MAP_(i, j) \ + REG32(VINTF##i##_LVCMDQ_ERR_MAP_##j, 0x10c0 + j * 4 + i * 0x100) \ + FIELD(VINTF##i##_LVCMDQ_ERR_MAP_##j, LVCMDQ_ERR_MAP, 0, 32) + +A_VINTFi_LVCMDQ_ERR_MAP_(0, 0) +/* Omitting [0][1~2] as not being directly called */ +A_VINTFi_LVCMDQ_ERR_MAP_(0, 3) + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index d487612ba2..a3830a02d6 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -8,19 +8,138 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" =20 #include "hw/arm/smmuv3.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 +static uint64_t tegra241_cmdqv_read_vintf(Tegra241CMDQV *cmdqv, hwaddr off= set) +{ + int i; + + switch (offset) { + case A_VINTF0_CONFIG: + return cmdqv->vintf_config; + case A_VINTF0_STATUS: + return cmdqv->vintf_status; + case A_VINTF0_SID_MATCH_0 ... A_VINTF0_SID_MATCH_15: + i =3D (offset - A_VINTF0_SID_MATCH_0) / 4; + return cmdqv->vintf_sid_match[i]; + case A_VINTF0_SID_REPLACE_0 ... A_VINTF0_SID_REPLACE_15: + i =3D (offset - A_VINTF0_SID_REPLACE_0) / 4; + return cmdqv->vintf_sid_replace[i]; + case A_VINTF0_LVCMDQ_ERR_MAP_0 ... A_VINTF0_LVCMDQ_ERR_MAP_3: + i =3D (offset - A_VINTF0_LVCMDQ_ERR_MAP_0) / 4; + return cmdqv->vintf_cmdq_err_map[i]; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", + __func__, offset); + return 0; + } +} + static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned = size) { - return 0; + Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + + if (offset >=3D TEGRA241_CMDQV_IO_LEN) { + qemu_log_mask(LOG_UNIMP, + "%s offset 0x%" PRIx64 " off limit (0x50000)\n", __f= unc__, + offset); + return 0; + } + + switch (offset) { + case A_CONFIG: + return cmdqv->config; + case A_PARAM: + return cmdqv->param; + case A_STATUS: + return cmdqv->status; + case A_VI_ERR_MAP ... A_VI_ERR_MAP_1: + return cmdqv->vi_err_map[(offset - A_VI_ERR_MAP) / 4]; + case A_VI_INT_MASK ... A_VI_INT_MASK_1: + return cmdqv->vi_int_mask[(offset - A_VI_INT_MASK) / 4]; + case A_CMDQ_ERR_MAP ... A_CMDQ_ERR_MAP_3: + return cmdqv->cmdq_err_map[(offset - A_CMDQ_ERR_MAP) / 4]; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: + return cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4]; + case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: + return tegra241_cmdqv_read_vintf(cmdqv, offset); + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", + __func__, offset); + return 0; + } +} + +static void tegra241_cmdqv_write_vintf(Tegra241CMDQV *cmdqv, hwaddr offset, + uint64_t value) +{ + int i; + + switch (offset) { + case A_VINTF0_CONFIG: + /* Strip off HYP_OWN setting from guest kernel */ + value &=3D ~R_VINTF0_CONFIG_HYP_OWN_MASK; + + cmdqv->vintf_config =3D value; + if (value & R_VINTF0_CONFIG_ENABLE_MASK) { + cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; + } else { + cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; + } + break; + case A_VINTF0_SID_MATCH_0 ... A_VINTF0_SID_MATCH_15: + i =3D (offset - A_VINTF0_SID_MATCH_0) / 4; + cmdqv->vintf_sid_match[i] =3D value; + break; + case A_VINTF0_SID_REPLACE_0 ... A_VINTF0_SID_REPLACE_15: + i =3D (offset - A_VINTF0_SID_REPLACE_0) / 4; + cmdqv->vintf_sid_replace[i] =3D value; + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", + __func__, offset); + return; + } } =20 static void tegra241_cmdqv_write(void *opaque, hwaddr offset, uint64_t val= ue, unsigned size) { + Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + + if (offset >=3D TEGRA241_CMDQV_IO_LEN) { + qemu_log_mask(LOG_UNIMP, + "%s offset 0x%" PRIx64 " off limit (0x50000)\n", __f= unc__, + offset); + return; + } + + switch (offset) { + case A_CONFIG: + cmdqv->config =3D value; + if (value & R_CONFIG_CMDQV_EN_MASK) { + cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; + } else { + cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; + } + break; + case A_VI_INT_MASK ... A_VI_INT_MASK_1: + cmdqv->vi_int_mask[(offset - A_VI_INT_MASK) / 4] =3D value; + break; + case A_CMDQ_ALLOC_MAP_0 ... A_CMDQ_ALLOC_MAP_1: + cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] =3D value; + break; + case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: + tegra241_cmdqv_write_vintf(cmdqv, offset, value); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", + __func__, offset); + } } =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103270; cv=pass; d=zohomail.com; s=zohoarc; b=aq2ZRPd0pkb7fm36tK2yraBge6tMeLmGmOV8OWJ+ffaLYW9QgivpyJdYURVloSO9nba481cJTq1AdEHPo3Ca9viafWftjdoDLXioxTNMFDG8aCh7vho/r/s7UDQZ/3fyI0nR2Uc03mqE8R+2ierjVloPGC1FWkrqFn9YvkdXYqc= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103270; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=H1gkGW25ViwhMHjCKlGTG7gy/2Tzm+MNKheML2midkk=; b=j6xNthxcgrml4AzHsr9w9VIaK5Va41V/lb6NKLfqQrERc5+5nDel2uKLh0/FyGExiszLObziWfWgCaqnetLKKY09Div9JPbg0D+LfyJkxy+KJ1CRihCzdQKfj4AqYiVW8gHHFpTFRkHXfgqZNRaFNiQ+Ff82kWhNIM7WOtvQmDg= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103270761375.6110337960248; Thu, 26 Feb 2026 02:54:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzI-0004ya-Jm; Thu, 26 Feb 2026 05:52:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzH-0004w5-6m; Thu, 26 Feb 2026 05:52:55 -0500 Received: from mail-westcentralusazlp170130007.outbound.protection.outlook.com ([2a01:111:f403:c112::7] helo=CY3PR05CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzF-0000s8-7e; Thu, 26 Feb 2026 05:52:54 -0500 Received: from PH8P220CA0018.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:345::28) by DS7PR12MB6214.namprd12.prod.outlook.com (2603:10b6:8:96::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.23; Thu, 26 Feb 2026 10:52:44 +0000 Received: from SN1PEPF000397AF.namprd05.prod.outlook.com (2603:10b6:510:345:cafe::c6) by PH8P220CA0018.outlook.office365.com (2603:10b6:510:345::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:52:44 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397AF.mail.protection.outlook.com (10.167.248.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:44 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:24 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:21 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=o7sJlUZKCs1dOa71EgG7l+ylehZ9N9GJZDvfpz43MCYCyauJ4+35At/MoDkYS2eqQp+0KB1KrPHjRCdo1xtKOvwGPPh1Pmf/L+TaFgrw8+okGc8KZhWCyJclyCGs2MfYTQlKG+H6vwaQkQW4Q6vpzodYdDN+8KVLZoEwLnG+4R4rycOO8ZIB4sRLdo53XoM9SYlpcYIbG4AmxBnSMsqWbcgsvsd1TigLPy8TivZjkz+gYb1nJke6DzfKTUMjsfscLjS/CqF/b2zwX/rFbsWkmmjr+Ker6XjSPLG99R6lhQCsSs9hwaC9GuN0JYBOp2jJrTQ435hLMdmce6N4q6s/rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=H1gkGW25ViwhMHjCKlGTG7gy/2Tzm+MNKheML2midkk=; b=rSdWKsaoC7068jSHkZg2xRbQ6DG0N1CKRpwduQ3c+5gMd+UQT/kXwU7FcBeYWc/SuUofTgdxygx6cC5OshZp9JQUZ4OFNYvHeXJwR5qsJMaNEpq3kLt5O1oXSNxYgzvLhh+/dujjOVsRitGb1f3bHLqoe5KtBWD9h9zg8MTavbbi0+SKfJDf5Y1d/UofZStwkVk3P0MXLkW3hpplkOjydaQb+gYUMXZWzTgaf/JN/4mzSc4tJ4a0VHMs5CPxU1X4MG3mkld8cV5c5Fgg1rFngsVEyUhkKORnqh21YLRyhknL15b+e4fW1q1pnPs0Wt9CcuHNQxXOwelR8MguANMOiw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H1gkGW25ViwhMHjCKlGTG7gy/2Tzm+MNKheML2midkk=; b=jtIs/7WnHy6dk0uazULHbjUw5R1MHmCDXWOXusK3APbHZ8OYNHnfO+/b/parQ2zXHZwlIB4YmgrGSEsap4oyaO7k96FtbBpe/UWOhKnWCQ0jnDVe8wBa+uWCUqbdg+qO86fO2XZSyiAqeNX9+uCsTU7gBE2wdv82GtXf+dATckdv/+ALTRL0SBLr0pVlqT0P460gJ2rZXUYYmLu1rr0gc6UeZTmFmY8cxCHT643RTzKw9PqU3haDwX6JTQhfRiXZOv72g62zt3FXhS/TYMBxSC/V34FH0mFGyu7arGTBP3gwkojVfObWvZ3HTydpH76DNELRUrNd8+pP99W0pchY1g== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 15/32] hw/arm/tegra241-cmdqv: Emulate global and VINTF VCMDQ register reads Date: Thu, 26 Feb 2026 10:50:39 +0000 Message-ID: <20260226105056.897-16-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|DS7PR12MB6214:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f4de30b-96c7-481e-5814-08de75252bea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|7416014|36860700013|376014; X-Microsoft-Antispam-Message-Info: C2iUmwckLcqCMVQSDFFLAXZcAj9R49nYAOdXSNzEjn06nadGp7qwMLhywywWIol/T/qoPE1a8MIQow9MQqztrDtPCboUkagXlB8MLTMpwwS8fsHo+zRF9RoHYZwOlNtYji4Hi7wFoRaRAvSkvFW0q4Tzcc3LO7Am5mWm2roZ89XWloCifKZ2syAP+x1zjghm2vdkKJUB/eZ6IRbI6UXxDTVQjTgg1eBTcr7Q/PUvYQa20Kx/99+qclZ6XqQJY9HOKxiIZ/UtR/lZ6jE9HdrNlHxQuGdtyO20+7NdBuiU4iMVSsH/Cfc4Dqy7o+cnhbZAtCREWSprEJv7ZSoiNVA7F1Z7CuDS1Jmus2qkZfZFqY+9+/aGGoanmKkmahrSBopvymWOdtkSaJVQ6Msy5VDDb6eVL22rR9ybS8Q6rx7bhhIYGUIx6tR9FTsmpMGGhmqb2FBVKT4I00iW78roakSI6TMFBzbGAetN84WJI2C3q1BoW3Kjbr7pMCG1aVv4t8daQuc0fq/j9qeUTEZhio20rVUIz09ST3txPy95o7Vw9gcQv2dkS+zCY7FpbtYOPcQIAClIOYeRxTfeuDUHnU25lI/XkJR4Fycdzb9g05axTbWVK/cB6InEQe16UzVVlAaBA51soNB3Z1vlE3DPgw+VnyOP7cTaAjlbKxFxn6tvKrdGTL7kFC2PRbQIhbOfKYlN+8eDvTd29smlfyom6KK/kYix7/ldjlJmt0cwqP1oNB9SA8fTZ2xnpSe3ikJfFtPDwXShMInC6LTXeEJWI63vnsbsPfZXsSTIwumLIGMkwvGnABhWzhi/WmpI1OnyaLj4uaj/b2vdBuPhMtuz4UtX/A== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(7416014)(36860700013)(376014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: e02HHXIGRRbq7YfUW3p3IAUcvQpyM1oljEUXxLFWA1hD8ZBudahTqhTVeeLVI0+q0CtJSCG5KG8BSZmpW2FHOO3AenXTMtsHACIyfU5hMvchPw7/tGCpwLM7EkTS4YmLpUjRk81t/sjtXwKUYk5d4Pm9AdcFXQQtOsybpDXJ2ZHO3A0tily5ykXJJOtl2aMJJRot6FtnfRySap1JqEBpbBmiTQSWePhIK7DDWDxHj8t+ZReVTlF2DgtRk7K1zpqKqTzlYkGWXpHp8nfyoxH9zE9E71S6hKSfs24noE6hLeBq1ABq7pHRzCCoRyG8Kt2MOLREHrdFg9z88roW9XnRz5Ixzk5TRFGEnn1kV8ceRvT1PjW7/0vVGw1uDD2R6Bf+4oyZSA9ji/t/Jss7/hlJKpoD+NFkFM0AwYio68qC1mVd5R4OEy/BDYdWIWBh1q5m X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:44.1421 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f4de30b-96c7-481e-5814-08de75252bea X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6214 Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=skolothumtho@nvidia.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103271169158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Tegra241 CMDQV exposes per-VCMDQ register windows through two MMIO views: -Global VCMDQ registers at 0x10000/0x20000 -VINTF VCMDQ (VI_VCMDQ) registers at 0x30000/0x40000 The VI_VCMDQ register ranges are an alias of the global VCMDQ registers and are only meaningful when a VCMDQ is mapped to a VINTF via ioctl IOMMU_HW_QUEUE_ALLOC. Add read side emulation for both global VCMDQ and VI_VCMDQ register ranges. MMIO accesses are decoded to extract the VCMDQ instance index and normalized to a VCMDQ0_* register offset, allowing a single helper to service all VCMDQ instances. VI_VCMDQ accesses are translated to their equivalent global VCMDQ offsets and reuse the same decoding path. All VCMDQ reads are currently served from cached register state. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 178 ++++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.c | 77 +++++++++++++++++ 2 files changed, 255 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 50bcecee9d..d379b8860c 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -48,6 +48,14 @@ typedef struct Tegra241CMDQV { uint32_t vintf_sid_match[16]; uint32_t vintf_sid_replace[16]; uint32_t vintf_cmdq_err_map[4]; + uint32_t vcmdq_cons_indx[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_prod_indx[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_config[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_status[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_gerror[TEGRA241_CMDQV_MAX_CMDQ]; + uint32_t vcmdq_gerrorn[TEGRA241_CMDQV_MAX_CMDQ]; + uint64_t vcmdq_base[TEGRA241_CMDQV_MAX_CMDQ]; + uint64_t vcmdq_cons_indx_base[TEGRA241_CMDQV_MAX_CMDQ]; } Tegra241CMDQV; =20 /* Global CMDQV MMIO registers (offset 0x00000) */ @@ -141,6 +149,176 @@ A_VINTFi_LVCMDQ_ERR_MAP_(0, 0) /* Omitting [0][1~2] as not being directly called */ A_VINTFi_LVCMDQ_ERR_MAP_(0, 3) =20 +/* + * VCMDQ register windows. + * + * Page 0 @ 0x10000: VCMDQ control and status registers + * Page 1 @ 0x20000: VCMDQ base and DRAM address registers + */ +#define A_VCMDQi_CONS_INDX(i) \ + REG32(VCMDQ##i##_CONS_INDX, 0x10000 + i * 0x80) \ + FIELD(VCMDQ##i##_CONS_INDX, RD, 0, 20) \ + FIELD(VCMDQ##i##_CONS_INDX, ERR, 24, 7) + +A_VCMDQi_CONS_INDX(0) +A_VCMDQi_CONS_INDX(1) + +#define V_VCMDQ_CONS_INDX_ERR_CERROR_NONE 0 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_OPCODE 1 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ABT 2 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ATC_INV_SYNC 3 +#define V_VCMDQ_CONS_INDX_ERR_CERROR_ILL_ACCESS 4 + +#define A_VCMDQi_PROD_INDX(i) \ + REG32(VCMDQ##i##_PROD_INDX, 0x10000 + 0x4 + i * 0x80) \ + FIELD(VCMDQ##i##_PROD_INDX, WR, 0, 20) + +A_VCMDQi_PROD_INDX(0) +A_VCMDQi_PROD_INDX(1) + +#define A_VCMDQi_CONFIG(i) \ + REG32(VCMDQ##i##_CONFIG, 0x10000 + 0x8 + i * 0x80) \ + FIELD(VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) + +A_VCMDQi_CONFIG(0) +A_VCMDQi_CONFIG(1) + +#define A_VCMDQi_STATUS(i) \ + REG32(VCMDQ##i##_STATUS, 0x10000 + 0xc + i * 0x80) \ + FIELD(VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) + +A_VCMDQi_STATUS(0) +A_VCMDQi_STATUS(1) + +#define A_VCMDQi_GERROR(i) \ + REG32(VCMDQ##i##_GERROR, 0x10000 + 0x10 + i * 0x80) \ + FIELD(VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ + FIELD(VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) + +A_VCMDQi_GERROR(0) +A_VCMDQi_GERROR(1) + +#define A_VCMDQi_GERRORN(i) \ + REG32(VCMDQ##i##_GERRORN, 0x10000 + 0x14 + i * 0x80) \ + FIELD(VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ + FIELD(VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) + +A_VCMDQi_GERRORN(0) +A_VCMDQi_GERRORN(1) + +#define A_VCMDQi_BASE_L(i) \ + REG32(VCMDQ##i##_BASE_L, 0x20000 + i * 0x80) \ + FIELD(VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \ + FIELD(VCMDQ##i##_BASE_L, ADDR, 5, 27) + +A_VCMDQi_BASE_L(0) +A_VCMDQi_BASE_L(1) + +#define A_VCMDQi_BASE_H(i) \ + REG32(VCMDQ##i##_BASE_H, 0x20000 + 0x4 + i * 0x80) \ + FIELD(VCMDQ##i##_BASE_H, ADDR, 0, 16) + +A_VCMDQi_BASE_H(0) +A_VCMDQi_BASE_H(1) + +#define A_VCMDQi_CONS_INDX_BASE_DRAM_L(i) \ + REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, 0x20000 + 0x8 + i * 0x80) \ + FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) + +A_VCMDQi_CONS_INDX_BASE_DRAM_L(0) +A_VCMDQi_CONS_INDX_BASE_DRAM_L(1) + +#define A_VCMDQi_CONS_INDX_BASE_DRAM_H(i) \ + REG32(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, 0x20000 + 0xc + i * 0x80) \ + FIELD(VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) + +A_VCMDQi_CONS_INDX_BASE_DRAM_H(0) +A_VCMDQi_CONS_INDX_BASE_DRAM_H(1) + +/* + * VI_VCMDQ register windows (VCMDQs mapped via VINTF). + * + * Page 0 @ 0x30000: VI_VCMDQ control and status registers + * Page 1 @ 0x40000: VI_VCMDQ base and DRAM address registers + */ +#define A_VI_VCMDQi_CONS_INDX(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX, 0x30000 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONS_INDX, RD, 0, 20) \ + FIELD(VI_VCMDQ##i##_CONS_INDX, ERR, 24, 7) + +A_VI_VCMDQi_CONS_INDX(0) +A_VI_VCMDQi_CONS_INDX(1) + +#define A_VI_VCMDQi_PROD_INDX(i) \ + REG32(VI_VCMDQ##i##_PROD_INDX, 0x30000 + 0x4 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_PROD_INDX, WR, 0, 20) + +A_VI_VCMDQi_PROD_INDX(0) +A_VI_VCMDQi_PROD_INDX(1) + +#define A_VI_VCMDQi_CONFIG(i) \ + REG32(VI_VCMDQ##i##_CONFIG, 0x30000 + 0x8 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONFIG, CMDQ_EN, 0, 1) + +A_VI_VCMDQi_CONFIG(0) +A_VI_VCMDQi_CONFIG(1) + +#define A_VI_VCMDQi_STATUS(i) \ + REG32(VI_VCMDQ##i##_STATUS, 0x30000 + 0xc + i * 0x80) \ + FIELD(VI_VCMDQ##i##_STATUS, CMDQ_EN_OK, 0, 1) + +A_VI_VCMDQi_STATUS(0) +A_VI_VCMDQi_STATUS(1) + +#define A_VI_VCMDQi_GERROR(i) \ + REG32(VI_VCMDQ##i##_GERROR, 0x30000 + 0x10 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_GERROR, CMDQ_ERR, 0, 1) \ + FIELD(VI_VCMDQ##i##_GERROR, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VI_VCMDQ##i##_GERROR, CMDQ_INIT_ERR, 2, 1) + +A_VI_VCMDQi_GERROR(0) +A_VI_VCMDQi_GERROR(1) + +#define A_VI_VCMDQi_GERRORN(i) \ + REG32(VI_VCMDQ##i##_GERRORN, 0x30000 + 0x14 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_ERR, 0, 1) \ + FIELD(VI_VCMDQ##i##_GERRORN, CONS_DRAM_WR_ABT_ERR, 1, 1) \ + FIELD(VI_VCMDQ##i##_GERRORN, CMDQ_INIT_ERR, 2, 1) + +A_VI_VCMDQi_GERRORN(0) +A_VI_VCMDQi_GERRORN(1) + +#define A_VI_VCMDQi_BASE_L(i) \ + REG32(VI_VCMDQ##i##_BASE_L, 0x40000 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_BASE_L, LOG2SIZE, 0, 5) \ + FIELD(VI_VCMDQ##i##_BASE_L, ADDR, 5, 27) + +A_VI_VCMDQi_BASE_L(0) +A_VI_VCMDQi_BASE_L(1) + +#define A_VI_VCMDQi_BASE_H(i) \ + REG32(VI_VCMDQ##i##_BASE_H, 0x40000 + 0x4 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_BASE_H, ADDR, 0, 16) + +A_VI_VCMDQi_BASE_H(0) +A_VI_VCMDQi_BASE_H(1) + +#define A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, 0x40000 + 0x8 + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_L, ADDR, 0, 32) + +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(0) +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(1) + +#define A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(i) \ + REG32(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, 0x40000 + 0xc + i * 0x80) \ + FIELD(VI_VCMDQ##i##_CONS_INDX_BASE_DRAM_H, ADDR, 0, 16) + +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(0) +A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(1) + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index a3830a02d6..d2e6938e44 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -14,6 +14,46 @@ #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 +/* + * Read a VCMDQ register using VCMDQ0_* offsets. + * + * The caller normalizes the MMIO offset such that @offset0 always refers + * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + * + * All VCMDQ accesses return cached registers. + */ +static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr off= set0, + int index) +{ + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + return cmdqv->vcmdq_cons_indx[index]; + case A_VCMDQ0_PROD_INDX: + return cmdqv->vcmdq_prod_indx[index]; + case A_VCMDQ0_CONFIG: + return cmdqv->vcmdq_config[index]; + case A_VCMDQ0_STATUS: + return cmdqv->vcmdq_status[index]; + case A_VCMDQ0_GERROR: + return cmdqv->vcmdq_gerror[index]; + case A_VCMDQ0_GERRORN: + return cmdqv->vcmdq_gerrorn[index]; + case A_VCMDQ0_BASE_L: + return cmdqv->vcmdq_base[index]; + case A_VCMDQ0_BASE_H: + return cmdqv->vcmdq_base[index] >> 32; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + return cmdqv->vcmdq_cons_indx_base[index]; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_H: + return cmdqv->vcmdq_cons_indx_base[index] >> 32; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled read access at 0x%" PRIx64 "\n", + __func__, offset0); + return 0; + } +} + static uint64_t tegra241_cmdqv_read_vintf(Tegra241CMDQV *cmdqv, hwaddr off= set) { int i; @@ -42,6 +82,7 @@ static uint64_t tegra241_cmdqv_read_vintf(Tegra241CMDQV *= cmdqv, hwaddr offset) static uint64_t tegra241_cmdqv_read(void *opaque, hwaddr offset, unsigned = size) { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + int index; =20 if (offset >=3D TEGRA241_CMDQV_IO_LEN) { qemu_log_mask(LOG_UNIMP, @@ -67,6 +108,42 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwadd= r offset, unsigned size) return cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4]; case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: return tegra241_cmdqv_read_vintf(cmdqv, offset); + case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: + /* + * VI_VCMDQ registers (VINTF logical view) have the same per-VCMDQ + * layout as the global VCMDQ registers, but are based at 0x30000 + * instead of 0x10000. + * + * Subtract 0x20000 to translate a VI_VCMDQ offset into the equiva= lent + * global VCMDQ offset, then fall through to reuse the common VCMDQ + * decoding logic below. + */ + offset -=3D 0x20000; + QEMU_FALLTHROUGH; + case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN: + /* + * Decode a per-VCMDQ register access. + * + * The hardware supports up to 128 identical VCMDQ instances; we + * currently expose TEGRA241_CMDQV_MAX_CMDQ (=3D 2). Each VCMDQ + * occupies a 0x80-byte window starting at 0x10000. + * + * The MMIO offset is decoded to extract the VCMDQ index and norma= lized + * to the corresponding VCMDQ0_* register by subtracting index * 0= x80. + * + * A single helper then services all VCMDQs, with @index selecting= the + * instance. + */ + index =3D (offset - 0x10000) / 0x80; + return tegra241_cmdqv_read_vcmdq(cmdqv, offset - index * 0x80, ind= ex); + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* Same decode logic as A_VI_VCMDQx_CONS_INDX case above */ + offset -=3D 0x20000; + QEMU_FALLTHROUGH; + case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* Same decode logic as A_VCMDQx_CONS_INDX case above */ + index =3D (offset - 0x20000) / 0x80; + return tegra241_cmdqv_read_vcmdq(cmdqv, offset - index * 0x80, ind= ex); default: qemu_log_mask(LOG_UNIMP, "%s unhandled read access at 0x%" PRIx64 = "\n", __func__, offset); --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103235; cv=pass; d=zohomail.com; s=zohoarc; b=WcZHcnlXQf7ku+Uz63nERdtTW9fI/WKbF6IVza+RkeD1HTM9DBdJ7ciFCNgAXXLribfMkVzuq3GRTkJTqUSo5ai52FSOdAsaBN2Yy2k5ugkD6jJd4PH0+G4rkwxHSL1G83ArtKHpjTtBCaHPwr9kMbqKH/L56BgB+5ld3moH6ag= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103235; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YtdlVXQ+Ar62xpkD5o9kVA6sZGzHZiJzZI/a6YWBCkU=; b=UHvIkQedu3X9jAk3A8MsM1L2sjqmC2a0rspOWjipkIOfQ7nSeAhH7lfPMaXt8+H+aPKRhqc8dnBtIBCzZlHqPPbNYaYA+x5zK/3ur2WoWqF+cmQ/3sjd/WrGrOf00kRzQE5gzt6U9cPpkHcm5HYN7Hf+YwNxAoCgVytndk/RmfA= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103235492529.1246168893366; Thu, 26 Feb 2026 02:53:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzc-0006FY-Sh; Thu, 26 Feb 2026 05:53:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYza-00065Q-T2; Thu, 26 Feb 2026 05:53:14 -0500 Received: from mail-eastusazlp17011000f.outbound.protection.outlook.com ([2a01:111:f403:c100::f] helo=BL2PR02CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzZ-0000wl-8V; Thu, 26 Feb 2026 05:53:14 -0500 Received: from PH8P220CA0018.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:345::28) by DS7PR12MB6214.namprd12.prod.outlook.com (2603:10b6:8:96::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.23; Thu, 26 Feb 2026 10:52:47 +0000 Received: from SN1PEPF000397AF.namprd05.prod.outlook.com (2603:10b6:510:345:cafe::f4) by PH8P220CA0018.outlook.office365.com (2603:10b6:510:345::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:52:47 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397AF.mail.protection.outlook.com (10.167.248.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:47 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:28 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:25 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=kIg7bXMVcNCF7x0Pa0EkQWivlqmXZMAakFMIp2yDYVuDeoi4H3m99xNVut4DcoTM3AOBcRToq5T1wZccK5DFrtLVxPkXtFMZ1xfN/hZMelYbyHOSOGxi7/0iLLtZvS0FmcGfOLWgz4S4kMKnc3yciCbe0oa2Y6fXg8UltfVUcW+3PUMgmv966gUSbJPYdvZbYesXIeuaELW5ArXmEg7yPOMxmak+hltlkVIwMsWQvzPKnM4k9DpbUOscdCZjvvTv2M/SLH/Sev1YgEPn19zcuYcb3yTnXjNZiIR80quNfY2pu2srOGcOxLL1xdNz6qSMTR2Zwrz9NGLl1tPSk2nHHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YtdlVXQ+Ar62xpkD5o9kVA6sZGzHZiJzZI/a6YWBCkU=; b=b4pi5/brJHOqADyFuRCttRLjhBBhJvokdWFVnroxh4gXWxQ/xIb4DA9aJaLqr0nWXpl45FJqHguAS0RVkL/xB27NSvyGJgE4FaC+pfvgkkwRnoLcpaGf9/MVsAJ9Bx/R9XhZHJxidBeDoFksmsUIAaUXBNzbv6/tBJh9dVxcSZ2EUZvZPXku0XCW6jtcyxKiUtM0INBfFLXNrjQ0d5HI1MyZ0onpM+x6c0gXPdvHibzFbXKH2aEQC8MKHk/4jTReJ+4QUPkY+tavQy7PMMW8YpYG5xe74kCtAFVxXaCSo0QnOFyGHtrmHud1bguMTQRlIGp2/TeTbYJ+Ok+zsddyDg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YtdlVXQ+Ar62xpkD5o9kVA6sZGzHZiJzZI/a6YWBCkU=; b=OxbyFv1qGzqC20w5H5boal2an/W9+0OL25keRpdTUxidcTuDkXjSXfo8ZNd5VXI8cMkeMCmaedicGegqE4vv2ecZi2TT+5g78sydab6exDszMn8dYCSZ+11FXXVjmUOfzKXtU1/E1Sk41RcDwlnGt36s/tzkqk6FvyjE/aFzfueNPnBRX/+jWqe6lM9agsBdo/2F9OwhHG43R8688MmVAV1ePQ3umSCiCrJeP49VMfkojhUTOBoXlXSvVGZz8+Zefvn3BY98RPd/imtyQISepKBn8z39SYqhCwoLdSijnESRi9GrMWTvbloo6ZaRinbQjITJc67vS8hWZoCkw0J8Ng== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 16/32] hw/arm/tegra241-cmdqv: Emulate global and VINTF VCMDQ register writes Date: Thu, 26 Feb 2026 10:50:40 +0000 Message-ID: <20260226105056.897-17-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|DS7PR12MB6214:EE_ X-MS-Office365-Filtering-Correlation-Id: 81746200-4b4c-4435-3204-08de75252dcf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|7416014|36860700013|376014; X-Microsoft-Antispam-Message-Info: hZO5gsWpyGAIqZWWL1nKF8L7ynMSZpO7X5BaTvldjtxFC/Ni/dLrm16JmRhLJugOKF79KWZ6DZIoNxS0baRM9oklmE55cxrJZhVV37abZQSG8jBzR9iWGrrunskozkep60n9iVFOtWS0ePLuJZ3Rr+MXTaU69FrFs40wXui0a+qAT4mOqBOk7Vm7t2JvGgxTH9sUPU43j7tRX0VbqCWdw/0z6I7jZAIMbjaj/MONj64KiER9W1rcJmog3JKrnUCpXKVxd7yC6PjvLd1z913aguE54+oTkjAveSXVOy1nUMgq8xU9lIJR1/q8dLlwp7l1uWyQb0khh4/v05g/FTf6W+xX7WR5ZTr+v6z1AB+7fW6BqRC5Majejq9co+WZoTyhG+Xwh28FMb7GDaQmc1DN0EWahE1qjrPD5wU4sj1RF56ybKgz0Ody081CGmExDhFGV3DlWbWYExh6cvp8+LqouSW1ZUp6XWaSuBy4B51UiSgppXU1VRSDTLdvkMddRg+lw2dG2naiMFZMIfm5SQo3m0C+jo/LtOYR7aRIRJALDnOfA2pW94lIsqsZVxOjlqaV5zpDsZFsq/vXuR0HgY7Go31swSKddnotxG1EDI6XDoTI/v27bOsc+sG74o04SvWK+MpCz7tDQMwbNidrm3sZ/r5stoE3ZvU4+DeEFI1kYovbJcV8aWSEJQhBKuyt0gpmVq+g+InZJDCNu+rmhC2SQTe5a7CW8/zTqDw4nSU6fqPNrmHOaeZlPrnm7JLlWvtaAEvmMmp16yVsCrD/V8PQxvgm7IoHo20ZnErIMp4gFGXm1L4qdlkAgpc2g8qPhFcJ34RvtLukWHfxtgJvgCxzaA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(7416014)(36860700013)(376014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UFs2WNcrVhXyGNl2h/IYdGWrNUGJBtzaVE/D2ppYRd1o5sO/jbvVsMPjbjo+VKQdBJOLYaSOQwb+l6zb2WvlwjmwuRcYIPSk1Aco14iBW2yHWmFY9zAmOZczDOKl41pgphph3uFnFMT2hAQ7CrtxDvo6SDboufxkYWf9oC9LF6AcqQM4hv2vDapC0jOQUgdGV1J5s+0jt6uCfT4n8mmWeWF7MNpp0CycZ672/QIaB2WTi+3i73aDkBbYQ2zKLPfsYRvLzfpAlCObnhA9tjD2DypwIrKsixrNh/vrEFEiPaYPv1UuNIRNXw80WF+H0yHVG/K0CAzab46yxGDrIZQ7ZNtcsLs4ZmxOvMfyaTrBuyUg2x/w/Or7eWgXG/eoXQ0UZMTpWRWMogiLnTH/IePR2DCfD/3CWGT9Q6gsnz8qWQwwbXiVB+qqLdZ9G1dhVH3v X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:47.1897 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81746200-4b4c-4435-3204-08de75252dcf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6214 Received-SPF: permerror client-ip=2a01:111:f403:c100::f; envelope-from=skolothumtho@nvidia.com; helo=BL2PR02CU003.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103237092158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen This is the write side counterpart of the VCMDQ read emulation. Add write handling for global VCMDQ and VI_VCMDQ register windows. Per-VCMDQ accesses are decoded into a VCMDQ index and normalized to VCMDQ0_* offsets, reusing the same layout assumptions as the read path. VI_VCMDQ registers are treated as a logical alias of the global VCMDQ registers and share the same decoding logic. Writes are backed by cached register state only; no hardware queue mapping is performed yet. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 83 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index d2e6938e44..e1f1562c44 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -151,6 +151,70 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwad= dr offset, unsigned size) } } =20 +/* + * Write a VCMDQ register using VCMDQ0_* offsets. + * + * The caller normalizes the MMIO offset such that @offset0 always refers + * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + */ +static void +tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, + uint64_t value, unsigned size) +{ + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + cmdqv->vcmdq_cons_indx[index] =3D value; + return; + case A_VCMDQ0_PROD_INDX: + cmdqv->vcmdq_prod_indx[index] =3D (uint32_t)value; + return; + case A_VCMDQ0_CONFIG: + if (value & R_VCMDQ0_CONFIG_CMDQ_EN_MASK) { + cmdqv->vcmdq_status[index] |=3D R_VCMDQ0_STATUS_CMDQ_EN_OK_MAS= K; + } else { + cmdqv->vcmdq_status[index] &=3D ~R_VCMDQ0_STATUS_CMDQ_EN_OK_MA= SK; + } + cmdqv->vcmdq_config[index] =3D (uint32_t)value; + return; + case A_VCMDQ0_GERRORN: + cmdqv->vcmdq_gerrorn[index] =3D (uint32_t)value; + return; + case A_VCMDQ0_BASE_L: + if (size =3D=3D 8) { + cmdqv->vcmdq_base[index] =3D value; + } else if (size =3D=3D 4) { + cmdqv->vcmdq_base[index] =3D + (cmdqv->vcmdq_base[index] & 0xffffffff00000000ULL) | + (value & 0xffffffffULL); + } + return; + case A_VCMDQ0_BASE_H: + cmdqv->vcmdq_base[index] =3D + (cmdqv->vcmdq_base[index] & 0xffffffffULL) | + ((uint64_t)value << 32); + return; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: + if (size =3D=3D 8) { + cmdqv->vcmdq_cons_indx_base[index] =3D value; + } else if (size =3D=3D 4) { + cmdqv->vcmdq_cons_indx_base[index] =3D + (cmdqv->vcmdq_cons_indx_base[index] & 0xffffffff00000000UL= L) | + (value & 0xffffffffULL); + } + return; + case A_VCMDQ0_CONS_INDX_BASE_DRAM_H: + cmdqv->vcmdq_cons_indx_base[index] =3D + (cmdqv->vcmdq_cons_indx_base[index] & 0xffffffffULL) | + ((uint64_t)value << 32); + return; + default: + qemu_log_mask(LOG_UNIMP, + "%s unhandled write access at 0x%" PRIx64 "\n", + __func__, offset0); + return; + } +} + static void tegra241_cmdqv_write_vintf(Tegra241CMDQV *cmdqv, hwaddr offset, uint64_t value) { @@ -187,6 +251,7 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, unsigned size) { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + int index; =20 if (offset >=3D TEGRA241_CMDQV_IO_LEN) { qemu_log_mask(LOG_UNIMP, @@ -213,6 +278,24 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr = offset, uint64_t value, case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: tegra241_cmdqv_write_vintf(cmdqv, offset, value); break; + case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: + /* Same decoding as read() case: See comments above */ + offset -=3D 0x20000; + QEMU_FALLTHROUGH; + case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN: + index =3D (offset - 0x10000) / 0x80; + tegra241_cmdqv_write_vcmdq(cmdqv, offset - 0x80 * index, index, va= lue, + size); + break; + case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: + /* Same decoding as read() case: See comments above */ + offset -=3D 0x20000; + QEMU_FALLTHROUGH; + case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: + index =3D (offset - 0x20000) / 0x80; + tegra241_cmdqv_write_vcmdq(cmdqv, offset - 0x80 * index, index, va= lue, + size); + break; default: qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", __func__, offset); --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103439; cv=pass; d=zohomail.com; s=zohoarc; b=epxO74G5uqsUPAYENVEG6qXnbaP3pt0LHCXjHuxkUq0yBe3LamuXcO/cEMUrpVnjsHDbIETzjEAeOxu8QQbebAowjufxj75bDZyVMO26KLSrlQqhMuIRgE3b5Ihr7dPHD6PgVP30vvRNz+Dx0WfxQcyHYvuueGg7dhTYv8WRmBc= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103439; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=P0eBYB9DjCuAcJN1rBCIML8TGP8xxIFS6LFbGu+oTI8=; b=b3JzLsbqsrEbj4nVekqL7/5DZwtTNS1pimt+LuGllx3Rn+n4N5YZ7XcF/dwn/4GCp0JEssgeYXyuOFc2am/XULzSHWfPWYfnxRk0lk753243IPviz+xJF18t+LdKGNO/GDGtv0N4tElgOLMcrAG8+UKLwLGfVLjEMTC3gkKF1x8= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103439275750.4101706687163; Thu, 26 Feb 2026 02:57:19 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzO-0005Yt-0c; Thu, 26 Feb 2026 05:53:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzL-0005Fa-Rt; Thu, 26 Feb 2026 05:52:59 -0500 Received: from mail-northcentralusazlp170130007.outbound.protection.outlook.com ([2a01:111:f403:c105::7] helo=CH4PR04CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzJ-0000uu-UG; Thu, 26 Feb 2026 05:52:59 -0500 Received: from SA9P223CA0005.NAMP223.PROD.OUTLOOK.COM (2603:10b6:806:26::10) by CY3PR12MB9677.namprd12.prod.outlook.com (2603:10b6:930:101::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:52:53 +0000 Received: from SN1PEPF000397B2.namprd05.prod.outlook.com (2603:10b6:806:26:cafe::56) by SA9P223CA0005.outlook.office365.com (2603:10b6:806:26::10) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:52:45 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B2.mail.protection.outlook.com (10.167.248.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:53 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:32 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:29 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ggJrU0qVJpQM+6Ie/HBuXFe5gQzJtMy6UMzWfaBK72QIOo1COJF9fUwqzZkxGkjnKnbO7tpW9rHMT4I/LsWWbVQtsSFxCA4DXAeWmTuoUCFRTaMlno7aY+YHvzcR6Sh/5tbO8rNslU5mo9hz7DhwA5pZoRrjE9LXapeSSrIA5CdZ2kGlu6jDbiS5804xYuK3VUI3zR7LIuGFJcLXmJAQJy+Dx6c9B6zcDpJ+23O4JY8YE0m29Z4eBUKzLhQzyUsKp1KDQt5D9XymbbRsjaGnTKu/lJ9UJFx0lCq6RqjpXEUk7QLGeJuNMWkB5qENs6TiPHQ9Jo7Bak1JC2PQGOc/Og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=P0eBYB9DjCuAcJN1rBCIML8TGP8xxIFS6LFbGu+oTI8=; b=yljO1+LIuF+IJu/bUHtMYY0dmm+umFu6dGk168guJqUSo5anXmQv/vjRJ5+TMWX7LAtwsrD1t82cl6/SjO9VX+Dha4K0jrmncC1s1NsGRkr6AySGXHBdegFkpyZikB88GZduJJgc26x0zbtCkm9/pL/4Mnhts3HGlsxROFv4RGfD0VozAk5nevhhn2LJOByYCOHdsclgWRSratwCqSqUB2kovG9mfshfzJtNUvh8gS6wACFh0zzdwX7EuHrPhCAoQWQtMSbHubTp+mNqX7uq0hWygeI6tFavVandXoo+kOuR9Zg9drfRmhKkgbxdohYOtIwtFu+f1fZWtvU8FXnY6w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=P0eBYB9DjCuAcJN1rBCIML8TGP8xxIFS6LFbGu+oTI8=; b=DsJrmLkG8Un35VAl1Vl0AbvARG6KKdU07CzGDKAjjJvrqM/4OQWhytTSsondQr0RhiVtaRLVIBaJBn+KOWBYGf2UQ0ICfl0PySjJFkRym9K04UP4psc2v2ThsMVGYqohJ0k8e6qh5roHO+G1BfJdb8Jfxb8eQI1nxfKE1HrQaVGuYimz8qjjTLC7OM9Wl2Xu8Wj2rw4LqEN8HzRmcmmjVZyxlHDAdH585GyrgO3lIoUBLf8UqK1Wayq/W9JeOsYXZjo/P4PoNuqbuXbO3jnnSkGpivDzGlZayLD3KaF2UvxFM9P9q1VqpDVv+FwK4WuE/4lfe45WtCHv21FBzmHq8w== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 17/32] hw/arm/tegra241-cmdqv: mmap VINTF Page0 for CMDQV Date: Thu, 26 Feb 2026 10:50:41 +0000 Message-ID: <20260226105056.897-18-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B2:EE_|CY3PR12MB9677:EE_ X-MS-Office365-Filtering-Correlation-Id: be140546-1e86-4ec3-8d58-08de7525317d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: qBSnYCzhMtoiXyCKszezUuZgDxNY9NimfIYbMgi5L+yU7OFKMxI1L4BVG1pDKM9BHpvisGId66eAyvQpHUbCg+t4T4wLYJitBkuCyGxMN7T72sk/padHPWZHLFmBi3ASs8AwWqBjJ9w/jgcYQzhGffJI2QFbkdEVBmHHMkeKrdT40m8gkboJvASTJWFeinuU3ZhMWWZYgZxvspiPtUNVGlFYuSljW5s77GlcW/+TJVyaVmJCgFS2g0cJYKdhi+Nk6zxzw7qtf2d5DWTDBUJVmlxAh/T56deFE9t5tQUH8wF6hksF+mXB/La5pubQQKOQroBwfSYbVVwPwuMPZ4LIxhbf+wdOZCwr8aKCHTmGhhBQhgfHii9UTDMOQ5ZxOokIBjNV8h0V9M34a08TKuebdYGn4tAEheG562eydxj1wIDwa/ghLAz3g7sOO0G74tOWnVI3vNPe3hOm5aXUJKpDlqr+vGv/nTn5dtZuanncDmpqSMHJUxperdZyvjaIWp761i2LGerJfGmi47gVzt8xoVA6o9Ud7Q14EPOi55Tfq1T7osBbGkoYM+kPI4vNzeBtYp6L0B6G6D7QEgwlz9nkDQMcpP6wAxVGZDFdILLXPMNuak5Ptaq2+XYNcTFkaa3GllnEAo4xbfDp2i4QtmhHRZ2hHRh2uiIUhOFcqbz8NSRUEJUxF+P05rmrmvtugGhurMFX+MEnaHE7nraekKDOWTEtnojluMA0oAW2ycryI0Alpf1CIdinvLgv7Bk/KEYQ6Whdqdm1W1bJgeFm7iNcpVZKzNPikUyqqUMh1nTgL0Hnr7qpJyG9mKYKjTk+VOHby+q5fu1Sd4NbbstOco+zkw== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(82310400026)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 35ZVvKgvkw3OF4UqddqD5zODJaGv5T+yedVcz/yMvklppJeHVWw5ZfrHOCkOkLwKRYdoWwSkW5+tusSHeF6reizKBGJ8hOt14dGCqyVH3+SjNCDpNMSyjP8Q/rMKL3PNDxi6gKxyJmtTcLau+lqldhRapU7CcP8H39mHo4vDU7FUGHcyLqtmkTtyK9SJyz8iqDlcKr0kuaGam4Z/mA8c16tQtw5mPDCdqoU7u/lWXjUN1qGLHFYja9TViQlxUMKkqMu/hQNoT/Q/l3qNc3cLW0GSL0efArQ53djA7TnUUnAHHQkFNLssk9h0JYQvx7xTsnzZCFhM6G+e22PIekpSZ8yClZOxdqz5No1MOy+kIBCeYj/ub8VoX9WzpdVt5tkL5Nhdn+Mf7inVDZD6IY3egZuGDgMNaNUvttNTUy8Pd4vF34ge4ZxJcSEvJlSTrZW6 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:53.3649 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be140546-1e86-4ec3-8d58-08de7525317d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9677 Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=skolothumtho@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103456127158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Global VCMDQ pages provide a VM wide view of all VCMDQs, while the VINTF pages expose a logical view local to a given VINTF. Although real hardware may support multiple VINTFs, the kernel currently exposes a single VINTF per VM. The kernel provides an mmap offset for the VINTF Page0 region during vIOMMU allocation. However, the logical-to-physical association between VCMDQs and a VINTF is only established after HW_QUEUE allocation. Prior to that, the mapped Page0 does not back any real VCMDQ state. When VINTF is enabled, mmap the kernel provided Page0 region and unmap it when VINTF is disabled. This prepares the VINTF mapping in advance of subsequent patches that add VCMDQ allocation support. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 3 +++ hw/arm/tegra241-cmdqv.c | 44 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 45 insertions(+), 2 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index d379b8860c..3ce9f539ae 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -18,6 +18,8 @@ #define TEGRA241_CMDQV_MAX_CMDQ (1U << TEGRA241_CMDQV_NUM_CMDQ_= LOG2) #define TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2 4 =20 +#define VINTF_PAGE_SIZE 0x10000 + /* * Tegra241 CMDQV MMIO layout (64KB pages) * @@ -34,6 +36,7 @@ typedef struct Tegra241CMDQV { SMMUv3AccelState *s_accel; MemoryRegion mmio_cmdqv; qemu_irq irq; + void *vintf_page0; =20 /* Register Cache */ uint32_t config; diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index e1f1562c44..a3767a85a3 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -151,6 +151,39 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwad= dr offset, unsigned size) } } =20 +static bool +tegra241_cmdqv_munmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **errp) +{ + if (!cmdqv->vintf_page0) { + return true; + } + + if (munmap(cmdqv->vintf_page0, VINTF_PAGE_SIZE) < 0) { + error_setg_errno(errp, errno, "Failed to unmap VINTF page0"); + return false; + } + cmdqv->vintf_page0 =3D NULL; + return true; +} + +static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **= errp) +{ + IOMMUFDViommu *viommu =3D cmdqv->s_accel->viommu; + + if (cmdqv->vintf_page0) { + return true; + } + + if (!iommufd_backend_viommu_mmap(viommu->iommufd, viommu->viommu_id, + VINTF_PAGE_SIZE, + cmdqv->cmdqv_data.out_vintf_mmap_offs= et, + &cmdqv->vintf_page0, errp)) { + return false; + } + + return true; +} + /* * Write a VCMDQ register using VCMDQ0_* offsets. * @@ -216,7 +249,7 @@ tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr= offset0, int index, } =20 static void tegra241_cmdqv_write_vintf(Tegra241CMDQV *cmdqv, hwaddr offset, - uint64_t value) + uint64_t value, Error **errp) { int i; =20 @@ -227,8 +260,10 @@ static void tegra241_cmdqv_write_vintf(Tegra241CMDQV *= cmdqv, hwaddr offset, =20 cmdqv->vintf_config =3D value; if (value & R_VINTF0_CONFIG_ENABLE_MASK) { + tegra241_cmdqv_mmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; } else { + tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; } break; @@ -251,6 +286,7 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, unsigned size) { Tegra241CMDQV *cmdqv =3D (Tegra241CMDQV *)opaque; + Error *local_err =3D NULL; int index; =20 if (offset >=3D TEGRA241_CMDQV_IO_LEN) { @@ -276,7 +312,7 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, cmdqv->cmdq_alloc_map[(offset - A_CMDQ_ALLOC_MAP_0) / 4] =3D value; break; case A_VINTF0_CONFIG ... A_VINTF0_LVCMDQ_ERR_MAP_3: - tegra241_cmdqv_write_vintf(cmdqv, offset, value); + tegra241_cmdqv_write_vintf(cmdqv, offset, value, &local_err); break; case A_VI_VCMDQ0_CONS_INDX ... A_VI_VCMDQ1_GERRORN: /* Same decoding as read() case: See comments above */ @@ -300,6 +336,10 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr = offset, uint64_t value, qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", __func__, offset); } + + if (local_err) { + error_report_err(local_err); + } } =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103408; cv=pass; d=zohomail.com; s=zohoarc; b=WX/q7tjICDoYujKvW8s5AnHVPmRnhLV7id4B4Fj9btGiCLNZXs6poQuONMfBxrVoueuHvegobGR1eoZmN56EgQeE23w1Cw/89qmqF5xBnwY3fP0CJqShi03MysJbNfx1BaJPTCRoxHp3wtzk7G9Vajrss/GaqUd3eAR9l0l2kkg= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103408; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mOmUzNaaovJ/p7xg++2LU7soe49qzwpSpOfxpx8O6EU=; b=HTv4GOpO7dpt/CPuGpdmLs7SZekUX/wJg4CfsQmcnyYqy8HycONLsyXtY/TE3Nwyn54onVgtFpHDCblCeUc1fPvWN+kEdXwsVKg6OhfXwuHJIauGvFC7gsDfQ0r7B0dTREKrCnOqMDijKho+nBynw8k2AwJ0iuZgIKyAZKEosKg= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103407856262.9737231221603; Thu, 26 Feb 2026 02:56:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzR-0005eB-Ds; Thu, 26 Feb 2026 05:53:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzP-0005cV-8S; Thu, 26 Feb 2026 05:53:03 -0500 Received: from mail-eastusazlp170120007.outbound.protection.outlook.com ([2a01:111:f403:c101::7] helo=BL0PR03CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzN-0000vQ-Ok; Thu, 26 Feb 2026 05:53:03 -0500 Received: from CH5PR02CA0016.namprd02.prod.outlook.com (2603:10b6:610:1ed::13) by LV2PR12MB5918.namprd12.prod.outlook.com (2603:10b6:408:174::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.13; Thu, 26 Feb 2026 10:52:56 +0000 Received: from DM2PEPF00003FC5.namprd04.prod.outlook.com (2603:10b6:610:1ed:cafe::3d) by CH5PR02CA0016.outlook.office365.com (2603:10b6:610:1ed::13) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:52:55 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC5.mail.protection.outlook.com (10.167.23.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:55 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:36 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:33 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=J8g49JLb/hZsSFfcx9ty8I8jlSqKfFwudUNOroRsNipujAmEV28eL5JcCuWs8NOtGHzcYR2TMcxfaTgkM6W0VHAPMyb0JzQ2T4QPCZvt8HEDcEcV0s5xCC2ba0RpL/kFdMmXPnIgX0ni5gxcIuI21qbm1rPJS8bMKuD6hEIaoVTzd/BN1za8cFD3p9fHSGF74943Arp6hdGwPJulDGsPygUMoNcznhM7KWSFn/jmtRn7boXPFqGGbDrIlsFsb/chSJgS+xPdiDnB+yhYiODs90A02d//0G6rPQwTC7dz86jFWJAUPUFuWfPGmdSy97JXguIjHf8qZbdrLY++M8JnMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mOmUzNaaovJ/p7xg++2LU7soe49qzwpSpOfxpx8O6EU=; b=Vws1xuR305NUc/f9+ygDVPAfFL/AWrq3oRDYhdeE/3njd4Dc/zVsdZ8BHa0B7QpugtaYew0qt8l4ruMsT6jGku3+QTZvKwMdEbiJ6127j81W1kyavnIS5S6FdnuGZL+I8nt0Y3xK4z5cv3tYA2IWiqMLR5l8dtrcka0kcWeJzeOU7RLs4SvNA1WG1Lt+qQFDIenDPPJgy8b1FaKdDAVpqOfYpHVInm0VDVOktuOf07UQUW/Q+RzetAC5IEjiJysczovvVxZMP4Vrx17CtwXBkejy8wx961suRvnCK4dmJPpR65VE5StF20+hnRYhPzFPf+9gq1C5BArQa+sVIDEsCw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mOmUzNaaovJ/p7xg++2LU7soe49qzwpSpOfxpx8O6EU=; b=k0BBcxF4ZNz1epqvpBP4MYkOHcSlDGAYHXWoQfwsTjGK8KK98veLifPOv/dTPHhQGXu+W197aCg9JgiSptWUGoYlFJDR4xM/1GOqCdJLmy4gxORHT4gyr/ntxjl9JNXwLnAxuTyErQAj+53be3UdFPqSC31B1BdlqAXIPwCk0WWygXMcMeU/s/9ZnM6JHJp+b8+jk9xjRBw57pRxb+hkE7MX5fz+yXb1x3GWjYcu5qKNsKqdq1r+Jo8xeSwggVkkC999t7d6XM7QwzlieQZMuJbfdLiUiK88EOwBhesvzdXkoFM1N5goqFIFkD+DeSnJVUjtKgzmIdMcdqsiWT/Ihw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 18/32] system/physmem: Add address_space_is_ram() helper Date: Thu, 26 Feb 2026 10:50:42 +0000 Message-ID: <20260226105056.897-19-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC5:EE_|LV2PR12MB5918:EE_ X-MS-Office365-Filtering-Correlation-Id: bd44900c-e60a-4429-5856-08de752532c4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|36860700013|82310400026|7416014; X-Microsoft-Antispam-Message-Info: xfAvxhZMc9xdJ1WegBOZREkeUjlETB4VWylF9yMmnJOpy9d9KceKF+3nYlbcWHP2UxiAjbyaZ2HDm5IFzlOM9Z4H/9l8D+obF4tanYL58PjEh+plkuuQ68IEtaXwf/R3yZKypsMIGjZaogQmKE1352mZbMkEIbS7YpmSt6sq/HgTKbOoNtwdAexiusY7JjsqZf13rrla94a/d53J9l+ZjNPxPifBtX2tydVPHAV3xqM0liQOvMlPyiEuGxD+lat7pMpwRppyMsgjXapYoc59ebvzCv0VmaUIIvWqZtw20IoUrgGOSd9Q3rOjVphM92MSP3JpWiGPUUQhOSx51ryJXWnMd53rfq7MZ/vHNeeaNpKEG5RwSQwPiiy0g5vsYwtnb39Cmqeoz7HwnVRaGtkKZAX8ICCGZiRk6sd5buv3+lqGjdVUusGh/2quR73kMTPnJksvR2l9SedCBigIBsjZ1F9TsCTJKKy2HmBAyQnmRq2/kdWQBLMhOfmS0LFxtONOSrI3TtHgSyRmIffu1U/Ku6p9jym3wJxLz4/jH5zgSjzLUQ/tqtcokf7o5LK60OquGPWB2LszqyjE8GBm+fcgFdAQhB8WqYJoss65fCNXRP2EfvfB8eyzJ88z7gP4KTMlMcruI2bJFoIFR5KqkWbVDoaWGALPcmDXjDzXUB2CxzWn6XAMlyHZqOLgo9XmdH3BrdKlac2ljn2Xq/aPLr/p9oEy6DAnb2YVUbu3QPdwQb6y4vJPrPH3GQx+WFIT9GAJJV+FpprQUqtesOeKW9YgRFrXfIlZi2dtTSesakhHpezbm8vFJyUJMcbac+2Nr32oEn+mgSXfk+LnwTkBLNAZNQ== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026)(7416014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: cS3mres96w+ula2So7h73seRNlLACuAEoYD6sHhey7aN6/3C3ZZdLPp+NMQXfDfbeR5B+u/x/96xuIxKkJAHl3ajCU7D3gZYAtVkjJ00ZnoodgS7JyITwceSDOdv5l3TlCWAGd+0mj8Iay4o1WOZwN/eL/CP1pdK9qvhQ++DUVDXPkNAPNEIIoRCGhe65mpIlmFgpXiqJMQjsC9ETA0CMEc09dmv2GBWvDOv1WA7qUxdRy1jRxh5mmIrxPzAmA5Y2005uBOHSdCrjMJq6ucFWSSuQcJy7YOf+mqosINaOUL7kvHfszjsSzxc05Jpb0LVGCvL0TezUVWY/y3uPETPsYzfDt340prwAAp01YMiE6H/aeNpNQ8XK1ihyZUArGDe7tP2VZMPd9V5j5GQa1L3gA16L+jQh/eCIPS24RlszueVhs+1KbdYkHICyFrwIz2Q X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:55.6269 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd44900c-e60a-4429-5856-08de752532c4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5918 Received-SPF: permerror client-ip=2a01:111:f403:c101::7; envelope-from=skolothumtho@nvidia.com; helo=BL0PR03CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103409838158500 Content-Type: text/plain; charset="utf-8" Introduce address_space_is_ram(), a helper to determine whether a guest physical address resolves to a RAM-backed MemoryRegion within an AddressSpace. Reviewed-by: Eric Auger Signed-off-by: Shameer Kolothum --- include/system/memory.h | 10 ++++++++++ system/physmem.c | 11 +++++++++++ 2 files changed, 21 insertions(+) diff --git a/include/system/memory.h b/include/system/memory.h index 0562af3136..02b2e83fd7 100644 --- a/include/system/memory.h +++ b/include/system/memory.h @@ -2900,6 +2900,16 @@ bool address_space_access_valid(AddressSpace *as, hw= addr addr, hwaddr len, */ bool address_space_is_io(AddressSpace *as, hwaddr addr); =20 +/** + * address_space_is_ram: check whether a guest physical address whithin + * an address space is RAM. + * + * @as: #AddressSpace to be accessed + * @addr: address within that address space + */ + +bool address_space_is_ram(AddressSpace *as, hwaddr addr); + /* address_space_map: map a physical memory region into a host virtual add= ress * * May map a subset of the requested range, given by and returned in @plen. diff --git a/system/physmem.c b/system/physmem.c index 2fb0c25c93..ddcf921311 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3646,6 +3646,17 @@ bool address_space_is_io(AddressSpace *as, hwaddr ad= dr) return !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); } =20 +bool address_space_is_ram(AddressSpace *as, hwaddr addr) +{ + MemoryRegion *mr; + + RCU_READ_LOCK_GUARD(); + mr =3D address_space_translate(as, addr, &addr, NULL, false, + MEMTXATTRS_UNSPECIFIED); + + return memory_region_is_ram(mr); +} + static hwaddr flatview_extend_translation(FlatView *fv, hwaddr addr, hwaddr target_len, --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103380; cv=pass; d=zohomail.com; s=zohoarc; b=UI6t3xOaBNFgjFo7hzq+T/fPhJ2Ez9x95qcChRCMZIU5p5WucXRpbqf3YgJGsp0+AR+g8Bmv4uQcbqqq0vCcpjblK2krx0fXopMIqdnHSLzoBk3zYi2v19iJnQJpc2lsTeRE0huqmnFtKw1EOphJy3Pwf/XT4wYq/3qX4UxCJJs= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103380; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=H/x6Z53vYtwzADwrqfdwqpRtrFNsOWyKn1F8ehpLf3w=; b=ZPuduvH4TWrRHhiKgFWTBLjYcM69ayitJZHC4ySsFsOLfJ3QvYOJdPg00w3fexdhIsKNXBZmFbcJDZMJ0dbhpxOLHC8zMahwH15he2vjJC0KwtxoDjGY8W0Uo5mry6UaddzmwbHPA0J+jBbaSjqFTSg6gLLAHDD1aUsj3WQxP2o= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103380080848.4698298794129; Thu, 26 Feb 2026 02:56:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzn-0006qN-Hb; Thu, 26 Feb 2026 05:53:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzm-0006pb-0m; Thu, 26 Feb 2026 05:53:26 -0500 Received: from mail-eastusazlp17011000f.outbound.protection.outlook.com ([2a01:111:f403:c100::f] helo=BL2PR02CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzk-0000z8-A7; Thu, 26 Feb 2026 05:53:25 -0500 Received: from CH5PR02CA0012.namprd02.prod.outlook.com (2603:10b6:610:1ed::11) by DM6PR12MB4203.namprd12.prod.outlook.com (2603:10b6:5:21f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:52:58 +0000 Received: from DM2PEPF00003FC5.namprd04.prod.outlook.com (2603:10b6:610:1ed:cafe::3f) by CH5PR02CA0012.outlook.office365.com (2603:10b6:610:1ed::11) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:52:59 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC5.mail.protection.outlook.com (10.167.23.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:52:57 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:40 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:37 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=JszreLvQoTw7+j1mgxC67HWNISN0+GNCzFHlFGVFGsxUV6JU5DRJeydocpcfI5pC413YGByrr0Dh8b3JYezV61Eg7cznbyxk39KYTzwF76gu7v1phKpRTW2CMMbN4vPMAvnMwFPfL1n/wy1OLVxhYIyV4BcpWH8BjEvmRERQvycdq6R6Vxs7Dfkypbx42KcVdjRt8EDjOWSe9FdNf/Thd0adSoqh24x3iAUDdnIbVjdPiz5UZwz+5pSuQFb4RK+i5IoDZ06FzAopqIWCASETvBCney0CC0gG2x+Sxm6bV+hbi5HTGy4kXUtKR7RHoNBiI/UFrF5bx/p9OwMf1rhARQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=H/x6Z53vYtwzADwrqfdwqpRtrFNsOWyKn1F8ehpLf3w=; b=yaI8b87XdtithWyRWv3P0Kun5ezRN0j94ogHBAEFMPIAyJCTbS60zYEPcg+jcMgu32UZoFRBjI+mBz/WMTAMEN7iY+0vKWVh1WDQgEpVeyueoPwhUrE66OA5UhDEhPwNxd7d7ywfcJS6jpAoQprk6kbJbf7KnO15Hg+1LILZhh4LQsdTBfP4lfKFplGLnyzOMKHMRsREqwTnDtlxZiF/vSbZ48gXM+F9KECCVtNmcK/ub+wqw7xh7aTIexk6ay37KgSgtuVDLEP8lyy/bpA2AvENDH/sY+HufGpwJs2mJxTAwBJ5ToVW+RzLqoUYTiJwwqV3ml4q8QliLtAeLZc5GQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H/x6Z53vYtwzADwrqfdwqpRtrFNsOWyKn1F8ehpLf3w=; b=NVFcWIeF7TYaavCQOFTAXHPb7Ow0ep2hI/bIRfbeRj4rAA5qnGBVbJxqQPdRhwTbwgfoNY0t+RA0RX8JMjpniVhWbNY4eAgh6OtCLoNG0xlnkk67kyU+mlmDnEZ0EesGVVCcWYBCTaM4C1bQcVJhzEueei4+5/lSYl6ZhSuIlCRVwWnWDhpr/tljArorrrUpPdiApBC9rvzlz/lrXOzRQXKvddQdU4VHumqlQ+/7drgodeJ3PTxerYFho3TQb4DrGvnzunCpZsC7Rky+Hd9cG5jm1Rx4F0od380PmwkO9zvGyXC7nN1jl4NjfVi99H/8iiqYjIjdgAB07CETVMzupg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 19/32] hw/arm/tegra241-cmdqv: Allocate HW VCMDQs on base register programming Date: Thu, 26 Feb 2026 10:50:43 +0000 Message-ID: <20260226105056.897-20-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC5:EE_|DM6PR12MB4203:EE_ X-MS-Office365-Filtering-Correlation-Id: 85e311c8-bbe3-468b-97ed-08de752533ec X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: YcB67WePBj3kuRkmMZLRyRPxWd0P+YdEGCowZ92shJGdYGEoU+hVAueBPaNenRk+yW1of56O/ERznO+BWayqsqgsIZlgXbS12gIaYZqwlj6msbsBmODYB/DgeALoaU1E0uw5+6XcT7nXj6tAuL8K191OK1Di2rezyzsHgr7H5/Y6YrGrZ6d4yltcqN5DIzokySqI8nAjkcUd6QssvDDAJ5fKThDXIq7zKrmT8dYe296t+aajFHfyT/L1dC3dnyIY6UzuIDCLv5qPBPRTobk49+SlaUcdimY8PmJ/Gsw3LznssvVylTh0dV27HNKEby1bAX9TarUf0ZLnH+iZDffr2qPpgCKuNQCXk9oORzYXRCb7sjQrBreeww+dLdNBHzrPhEUfENUGj3O4/NjQzc75wVefU9T29DJyxaPkPHGbdCrZWfRgo1SXQAToYiv9OioqXCUEf30apI4vpRBWMHjApk1WokuxGan4OCwlObWDVOsmSsW5Z1gKZXbKFIT67GOBIRDHBZDqjUWZLL4cAl86Nu9ICAW/pnvWb09a/a8lBR/3yfUqeTquz5eZMUoh5qnRaLTcvaSqhuNz82wpEpKl7+lbOHeAuan6Mnqkp/kxnEmmEVmh8tvnmoJPOKi8zGaELWqwAbKa1NM+GmTbI/nxNk8OvyqzXXvRbLLqmA6V5/tDxqWSsbme085eUilU+m7Cn3AI28MPpwNz8wQU8UQphty91VSFxdS0fE2pV81Ra77V9mJ5DBkQCk7bu9TDarahsIKCvwYnC4eXn0nsFT4+YFRcvr0tsP4tly13ZLVj1Ir8y6ir7KuHtXyZuNj1KrSSS0jpNV3dNn6L3C5UZvYdvA== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: P5euJr504culk/E/Dme0AOg6ClkRvebcoItYSW3QTbh4n99J7YwKbmylg1WkqHTDf+HjHfVDlzOJYDbUtbt5inCmzBlCYhXQQXQp+t9B6LuQXDIBeaJ99AQY57hkJ2yavo38p2VbxfcEO014NEdlg4nLLr6T4FBLlA6rkZ3aUaXrnmEEUBLCHbigkkKQfZNXWWo8+5seL4912FJR4x8ldhL4CFMdrLnqlmTWd99Ob2X/OeO1pyD0vAael0TQwohrtMa/vDcSmA016wr3vR9UFAbI9Xivgcy+Uzr3WjveWNOmmgOvBwrDu1Ccwb3h/PsHAHynLCvA0M8Cic2R8wLZKGdX0dsTOMUfMZ45l8Z7NhSovx9swXAfJkuvzDwhD6kQBnJ46qRYBgtvEySSL31H0Sd245F/imOppKdl5yv3Yrox14zttAiUK6RFZ+1MWDz2 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:52:57.6534 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85e311c8-bbe3-468b-97ed-08de752533ec X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4203 Received-SPF: permerror client-ip=2a01:111:f403:c100::f; envelope-from=skolothumtho@nvidia.com; helo=BL2PR02CU003.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103381793158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add support for allocating IOMMUFD hardware queues when the guest programs the VCMDQ BASE registers. VCMDQ_EN is part of the VCMDQ_CONFIG register, which is accessed through the VINTF Page0 region. This region is mapped directly into the guest address space (introduced in a subsequent patch), so QEMU does not trap writes to VCMDQ_CONFIG. Since VCMDQ_EN writes are not trapped, QEMU cannot allocate the hardware queue based on that bit. Instead, allocate the IOMMUFD hardware queue when the guest writes a VCMDQ BASE register with a valid RAM-backed address and when CMDQV and VINTF are enabled. If a hardware queue was previously allocated for the same VCMDQ, free it before reallocation. Writes with invalid addresses are ignored. All allocated VCMDQs are freed when CMDQV or VINTF is disabled. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 11 +++++++ hw/arm/tegra241-cmdqv.c | 71 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 79 insertions(+), 3 deletions(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 3ce9f539ae..139e14b61b 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -36,6 +36,7 @@ typedef struct Tegra241CMDQV { SMMUv3AccelState *s_accel; MemoryRegion mmio_cmdqv; qemu_irq irq; + IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ]; void *vintf_page0; =20 /* Register Cache */ @@ -322,6 +323,16 @@ A_VI_VCMDQi_CONS_INDX_BASE_DRAM_L(1) A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(0) A_VI_VCMDQi_CONS_INDX_BASE_DRAM_H(1) =20 +static inline bool tegra241_cmdq_enabled(Tegra241CMDQV *cmdq) +{ + return cmdq->status & R_STATUS_CMDQV_ENABLED_MASK; +} + +static inline bool tegra241_vintf_enabled(Tegra241CMDQV *cmdq) +{ + return cmdq->vintf_status & R_VINTF0_STATUS_ENABLE_OK_MASK; +} + const SMMUv3AccelCmdqvOps *tegra241_cmdqv_get_ops(void); =20 #endif /* HW_ARM_TEGRA241_CMDQV_H */ diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index a3767a85a3..002dde50fc 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -151,6 +151,67 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwad= dr offset, unsigned size) } } =20 +static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index) +{ + SMMUv3AccelState *accel =3D cmdqv->s_accel; + IOMMUFDViommu *viommu =3D accel->viommu; + IOMMUFDHWqueue *vcmdq =3D cmdqv->vcmdq[index]; + + if (!vcmdq) { + return; + } + iommufd_backend_free_id(viommu->iommufd, vcmdq->hw_queue_id); + g_free(vcmdq); + cmdqv->vcmdq[index] =3D NULL; +} + +static void tegra241_cmdqv_free_all_vcmdq(Tegra241CMDQV *cmdqv) +{ + /* Free in the reverse order to avoid "resource busy" error */ + for (int i =3D (TEGRA241_CMDQV_MAX_CMDQ - 1); i >=3D 0; i--) { + tegra241_cmdqv_free_vcmdq(cmdqv, i); + } +} + +static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *cmdqv, int index, + Error **errp) +{ + SMMUv3AccelState *accel =3D cmdqv->s_accel; + uint64_t base_mask =3D (uint64_t)R_VCMDQ0_BASE_L_ADDR_MASK | + (uint64_t)R_VCMDQ0_BASE_H_ADDR_MASK << 32; + uint64_t addr =3D cmdqv->vcmdq_base[index] & base_mask; + uint64_t log2 =3D cmdqv->vcmdq_base[index] & R_VCMDQ0_BASE_L_LOG2SIZE_= MASK; + uint64_t size =3D 1ULL << (log2 + 4); + IOMMUFDViommu *viommu =3D accel->viommu; + IOMMUFDHWqueue *hw_queue; + uint32_t hw_queue_id; + + /* Ignore any invalid address. This may come as part of reset etc */ + if (!address_space_is_ram(&address_space_memory, addr) || + !address_space_is_ram(&address_space_memory, addr + size - 1)) { + return true; + } + + if (!tegra241_cmdq_enabled(cmdqv) || !tegra241_vintf_enabled(cmdqv)) { + return true; + } + + tegra241_cmdqv_free_vcmdq(cmdqv, index); + + if (!iommufd_backend_alloc_hw_queue(viommu->iommufd, viommu->viommu_id, + IOMMU_HW_QUEUE_TYPE_TEGRA241_CMDQV, + index, addr, size, &hw_queue_id, + errp)) { + return false; + } + hw_queue =3D g_new(IOMMUFDHWqueue, 1); + hw_queue->hw_queue_id =3D hw_queue_id; + hw_queue->viommu =3D viommu; + cmdqv->vcmdq[index] =3D hw_queue; + + return true; +} + static bool tegra241_cmdqv_munmap_vintf_page0(Tegra241CMDQV *cmdqv, Error **errp) { @@ -192,7 +253,7 @@ static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241CMD= QV *cmdqv, Error **errp) */ static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, - uint64_t value, unsigned size) + uint64_t value, unsigned size, Error **errp) { switch (offset0) { case A_VCMDQ0_CONS_INDX: @@ -220,11 +281,13 @@ tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwad= dr offset0, int index, (cmdqv->vcmdq_base[index] & 0xffffffff00000000ULL) | (value & 0xffffffffULL); } + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); return; case A_VCMDQ0_BASE_H: cmdqv->vcmdq_base[index] =3D (cmdqv->vcmdq_base[index] & 0xffffffffULL) | ((uint64_t)value << 32); + tegra241_cmdqv_setup_vcmdq(cmdqv, index, errp); return; case A_VCMDQ0_CONS_INDX_BASE_DRAM_L: if (size =3D=3D 8) { @@ -263,6 +326,7 @@ static void tegra241_cmdqv_write_vintf(Tegra241CMDQV *c= mdqv, hwaddr offset, tegra241_cmdqv_mmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; } else { + tegra241_cmdqv_free_all_vcmdq(cmdqv); tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; } @@ -302,6 +366,7 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, if (value & R_CONFIG_CMDQV_EN_MASK) { cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; } else { + tegra241_cmdqv_free_all_vcmdq(cmdqv); cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; } break; @@ -321,7 +386,7 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, case A_VCMDQ0_CONS_INDX ... A_VCMDQ1_GERRORN: index =3D (offset - 0x10000) / 0x80; tegra241_cmdqv_write_vcmdq(cmdqv, offset - 0x80 * index, index, va= lue, - size); + size, &local_err); break; case A_VI_VCMDQ0_BASE_L ... A_VI_VCMDQ1_CONS_INDX_BASE_DRAM_H: /* Same decoding as read() case: See comments above */ @@ -330,7 +395,7 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, case A_VCMDQ0_BASE_L ... A_VCMDQ1_CONS_INDX_BASE_DRAM_H: index =3D (offset - 0x20000) / 0x80; tegra241_cmdqv_write_vcmdq(cmdqv, offset - 0x80 * index, index, va= lue, - size); + size, &local_err); break; default: qemu_log_mask(LOG_UNIMP, "%s unhandled write access at 0x%" PRIx64= "\n", --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103286; cv=pass; d=zohomail.com; s=zohoarc; b=kRtFXmx6/2l5F4PE+z948mMXlvku4leXbOmD9YPH+3WpQGiMgc403CyIxpaPtbi+xB6EH3GRJbQE9JnACze33K0u/7lp6yr59QCPxwK6fpkc8rElu5FBQhJfvEeafNUXb5+WtdTSlYjOhEv9achKQB4KbleWyedmJSfZKLOofL8= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103286; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yp8P7Ylbz3ytWK2EoUZQGTemxRt5gkJftSGzBDQSTM8=; b=QXQWJRFNqiXnsty/uB75BCiaUsb5icLsGbXf/QBA57dCVMea2fO9Fq8m/v7qjp0fwWpQkn3q+qz4zfd3Oujukz2/lkt4ZB2IxlwF+yevBdOfu7rjsujsiXL+LRTfVe/gPh0U4kCaaBM/kiEQhfb5aVXcD16o3VctDXBtNwEggQ8= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103286106483.9545185337496; Thu, 26 Feb 2026 02:54:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzf-0006Qo-Bu; Thu, 26 Feb 2026 05:53:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzd-0006GS-0K; Thu, 26 Feb 2026 05:53:17 -0500 Received: from mail-northcentralusazlp170100001.outbound.protection.outlook.com ([2a01:111:f403:c105::1] helo=CH1PR05CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzb-0000wv-Fn; Thu, 26 Feb 2026 05:53:16 -0500 Received: from SA9P223CA0029.NAMP223.PROD.OUTLOOK.COM (2603:10b6:806:26::34) by SJ0PR12MB6854.namprd12.prod.outlook.com (2603:10b6:a03:47c::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.21; Thu, 26 Feb 2026 10:53:07 +0000 Received: from SN1PEPF000397B2.namprd05.prod.outlook.com (2603:10b6:806:26:cafe::3f) by SA9P223CA0029.outlook.office365.com (2603:10b6:806:26::34) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:53:06 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B2.mail.protection.outlook.com (10.167.248.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:06 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:44 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:41 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=qgDk2CmUIsayL9vUNY17Ol6fClmF68fcJOymD3oqL0Jb3DBeOCb9TPof17i9zN/BQuIOd8DMOZee8WR0hkkr0XO06Q7ZQKbcNjso2xYQwi9Ix3NUwY7Z5yyyIqaWG2yMA1T9h5DcVa2agJbcxEHeO1ofu2yjlZs6noOFmi0rdY5msw1gvWBE+gldg4eRqkr7PUg5xvPcAHhLzHH+wXeu3gPrgWOvEucD84d1MseBSMqaRCTnb7scR9Z+lQHh7YLlkNHUEHaInltFefMOQDOLhAq/8D0VXOtLeq5m6sVT1203VxEquqA/MRFVNLTzUO9W85EW3nTkxL2rdrJUUy7wXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yp8P7Ylbz3ytWK2EoUZQGTemxRt5gkJftSGzBDQSTM8=; b=aF89obXH6QpquzK0hHnJyD5zbsgNW/EGxX7sCguvZ+XjCokdV15AVbyvLZDDJZ9YabJ6TwNm87pGXTeYt2IkvjwBkFv5zjpyZMHgCN51i3njrAp8g0ZnmKu1nsFGe3VwWaewGhD+aXtInnYSjc4wRCJu5FCTQ4cYpWpzqrxLkxoMPzvnCQxRXesBa+851a0RpOo6LsVvNSeeuj7Ps0XhXIEl9kcQ7YYlXsdEpIeEYgRgQKcZe8zxFcsxg8LXL1eFMbl2tf6m8U1lkxc7JbhtgjY4VzLfm1vuZbbwWyXmqim5xYwpuTLweZML7GV94wMu55DAMmYwYSI0As+IkMr/GA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yp8P7Ylbz3ytWK2EoUZQGTemxRt5gkJftSGzBDQSTM8=; b=MPZ8Yb5aAmxrW2gV822i12HAdVcZCid53HD15lWwZW8+eSIXFabKGcgd31lFviKqkoGxtqkygG6FlnmMdt+v/beraI9YaZYWCwQ6kvD0QhASM4PG5zo2sZTn0XslufekHwxDIPMJ+pNlrOhVCPe/V+aOGFRROLEdybGKTjq+AIoaS/P8JF0LKGWnpnyDXlT40wfpAusVmb5b+046fHCboDroCuOqjPQYZpy6dM84v3STQmSo5l+OByvhovXRiUWBTp0C8ZQQOM57JDvGf/3HKm/IOrLEPlZeq0mdPgNmVuH/EKCOelxXMYAJb7EKU0nes05WRRP+EVgTy/FZ8Eup1Q== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 20/32] hw/arm/tegra241-cmdqv: Use mmap'ed VINTF page0 as VCMDQ backing Date: Thu, 26 Feb 2026 10:50:44 +0000 Message-ID: <20260226105056.897-21-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B2:EE_|SJ0PR12MB6854:EE_ X-MS-Office365-Filtering-Correlation-Id: cf1c2047-7978-4414-1b03-08de7525394f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700013|7416014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: m1DNFF4HzQdUhK8jcfMKOQC5e3KS5LVszG7kQX3o5mZ752muw8qCrI+s+/2zQSXlRVCCGYLXoN7ICf91yQ3+O3lL7YPF+5rfZpeqt8LSwHy65bNCKhsPP0xP80+DstnPbzkWY8PN/L+3zJGzCl1HHeX0Za7v5Yv60i0Ur38Es6GFEmA1567u8gcM9awGzhl+BaWXz+3SIqOVDjSSk4XBfpAMn63RR9ncdObfdSlnlw1yzube5+g4x3njHQkQLjVMCRAaqe1avtgKF/L4kVnonhWi7a95rbWFe0+nh//GjL7h1tpc4T2J4AXh9iJggqzbRK4MDJxCSfiphm39J6+zw+cAXymgDoGVA+kDDzRVyu1IKOmk0dPwwhmY9UYQyGCAudGE2MvkV9ZDwh7262jDkDYgCYmmTKJBHaqqLJNuulkNiFLUzJ8biuqe2Csq1wFfkm8eNMIt6zPOyy1Z/CFG9jbmBREz4ss20hlpi8zOLLHArdTyPbWGsfCfuP+Blr1uNGTm2E5mBtsK4HAHk89KIM7LmzhveKfeCxLOEjDkjKGwHh9uonvRUbmbTzjWJLPysZb3TQXDTcntOKJWi8vLQro/C8dkYj3/NrpsDw6zDezdinL4MvTPYKr5lB/Y2O3G+ytBGJ8vf5yVpl7WRR8cP1GLhrp55QEtbbhfmVoC00EAsuMnHyanqujB4seMhcrbStfi/u7+jXQHvvB1pIwwq0DIqUpAiwbaex/YzC7YE8OQHpBiZaUm0hz3AvzJo/r6nhR59mlI2W8bNeXvq5VA4XirYNYFY6+f2TmhRuUP6eTQ+2O1uUAcahHDma+gNF9rv3F+fjbWNvRfJtkXnpvnuQ== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(7416014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dd5R0rKrgqUi6lmNgHL5FSVEWxqhx1mGTqCykLeJl+ZL9+puxeUMnRsGVffmDGkCM27t7WBM5uPPb3pECOwK9IAvTnrQpeisTaTKxYPAXuLXaUJ2dmDAYTX0VVsrmMA+Ch35IDPJLJBnoxphOcLz/Ra74qZaALy0VihPjfGh45S7lfUumKfIcqkwMxZBFa2cU3TNpJLHMLlhN9vxjKAKnqnfGks8Yz+nm459R5rAu9P2UZbaIJoIbCMIWVoamIForoao8ZUB2XzNlgLp+I260Kc5AkUXt8d4IFoFfrx/98PKB24o3i1Xa2pqTciwzZablxU7VI8U3FVOEFy7RkDSkAXmh7oO2nXkX/F1/mOlJh3Ogaki4qsrF5vSYgY3JSfa0FL9YM62+TS4NwgyiBICnQEH2lh8DlDAKEJi/N72b+5A2lHgoA/Uu1vIqixnMVWD X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:06.5943 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf1c2047-7978-4414-1b03-08de7525394f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6854 Received-SPF: permerror client-ip=2a01:111:f403:c105::1; envelope-from=skolothumtho@nvidia.com; helo=CH1PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103287302158500 Content-Type: text/plain; charset="utf-8" When a VCMDQ is allocated and VINTF page0 has been mmap'ed from the kernel, access the VCMDQ registers directly through the VINTF page0 backing instead of using QEMU's cached register state. VINTF page0 provides the backing memory region for VCMDQ registers once a hardware queue is created. In that case, reads and writes should reflect the live backing state. If a VCMDQ is not allocated, or if VINTF page0 is not available, continue to use the cached register values maintained by QEMU. Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 47 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 002dde50fc..17b9552906 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -14,17 +14,44 @@ #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 +static inline uint32_t *tegra241_cmdqv_vintf_ptr(Tegra241CMDQV *cmdqv, + int index, hwaddr offset0) +{ + if (!cmdqv->vcmdq[index] || !cmdqv->vintf_page0) { + return NULL; + } + + return (uint32_t *)(cmdqv->vintf_page0 + (index * 0x80) + + (offset0 - 0x10000)); +} /* * Read a VCMDQ register using VCMDQ0_* offsets. * * The caller normalizes the MMIO offset such that @offset0 always refers * to a VCMDQ0_* register, while @index selects the VCMDQ instance. * - * All VCMDQ accesses return cached registers. + * If the VCMDQ is allocated and VINTF page0 is mmap'ed, read directly + * from the VINTF page0 backing. Otherwise, fall back to cached state. */ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQV *cmdqv, hwaddr off= set0, int index) { + uint32_t *ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, offset0); + + if (ptr) { + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + case A_VCMDQ0_PROD_INDX: + case A_VCMDQ0_CONFIG: + case A_VCMDQ0_STATUS: + case A_VCMDQ0_GERROR: + case A_VCMDQ0_GERRORN: + return *ptr; + default: + break; + } + } + switch (offset0) { case A_VCMDQ0_CONS_INDX: return cmdqv->vcmdq_cons_indx[index]; @@ -250,11 +277,29 @@ static bool tegra241_cmdqv_mmap_vintf_page0(Tegra241C= MDQV *cmdqv, Error **errp) * * The caller normalizes the MMIO offset such that @offset0 always refers * to a VCMDQ0_* register, while @index selects the VCMDQ instance. + * + * If the VCMDQ is allocated and VINTF page0 is mmap'ed, write directly + * to the VINTF page0 backing. Otherwise, update cached state. */ static void tegra241_cmdqv_write_vcmdq(Tegra241CMDQV *cmdqv, hwaddr offset0, int index, uint64_t value, unsigned size, Error **errp) { + uint32_t *ptr =3D tegra241_cmdqv_vintf_ptr(cmdqv, index, offset0); + + if (ptr) { + switch (offset0) { + case A_VCMDQ0_CONS_INDX: + case A_VCMDQ0_PROD_INDX: + case A_VCMDQ0_CONFIG: + case A_VCMDQ0_GERRORN: + *ptr =3D (uint32_t)value; + return; + default: + break; + } + } + switch (offset0) { case A_VCMDQ0_CONS_INDX: cmdqv->vcmdq_cons_indx[index] =3D value; --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103237; cv=pass; d=zohomail.com; s=zohoarc; b=AJd7ucjkE8hcixVmQM4QV/BosjB9GvikmQRhk6ppoyqniqf8nWbaTHNOqIU5RL67hZ487Vg6BJ9g/e7FdHJMjbaKQyW2NfziHDcwgluzHoqHENBN9WVXpDUkdQpetBOnUermVsJ2PO3XvKYxv58ij5Z3TOJiUhMzjCVElGWne+E= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103237; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xxDGX7oD9NhKPcS4NTStGsYZCJknJrP3JSaOIlxsgEU=; b=klh5UpTD/A+bGHfw+hv7hFt/Jcww1M3vESP83r4zr801rY1xALGCnJnWoLczR7GUeItu7Pb7N5VOz0x7ngnFJpPYOor47uHNCDx0xd+3qd8cWeGlVenRTL0hexRDWGnqwJttqGthbYwsv/H2ChoBz4sckD1x0wwoC2JxCiAKJsA= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103237663658.7716981043187; Thu, 26 Feb 2026 02:53:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzj-0006mP-0p; Thu, 26 Feb 2026 05:53:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzh-0006cV-Em; Thu, 26 Feb 2026 05:53:21 -0500 Received: from mail-westus3azlp170100009.outbound.protection.outlook.com ([2a01:111:f403:c107::9] helo=PH7PR06CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzf-0000xV-Jp; Thu, 26 Feb 2026 05:53:21 -0500 Received: from PH0PR07CA0061.namprd07.prod.outlook.com (2603:10b6:510:f::6) by BY5PR12MB4114.namprd12.prod.outlook.com (2603:10b6:a03:20c::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:53:12 +0000 Received: from SN1PEPF000397AE.namprd05.prod.outlook.com (2603:10b6:510:f:cafe::1b) by PH0PR07CA0061.outlook.office365.com (2603:10b6:510:f::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:53:11 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397AE.mail.protection.outlook.com (10.167.248.52) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:11 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:48 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:45 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=JOnP8Ack/fvvA4ShG+IFxbwa7Lh56CitD+L8fNwXkizaX9Au6cTTUu+zfAdYd35Hj9rx5ZOXaSNzUSw2npD955teUxMilLi+Nntd11gadRUl7o8UwPmTDJsiGQgNnqL8Duwkm+1DSCY6qxa6hhhdSOh0bfKIJZy6vFPRk6ly6bH2xZZzI6puly3nNrOY066DvO0wH794I/u2NNtnXJptFxLuQiKamGIsRboSgcAkW9mX6bgDwXBzdvd8EijyI6sP2Bx5xVRtTqPrQOspwGvLGt/7l9mz9joMno+tlycnOkVrWgA6w7jIQh9eOQzaKWR2cBU/O0fX9PyrGzJ8TUAZ5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xxDGX7oD9NhKPcS4NTStGsYZCJknJrP3JSaOIlxsgEU=; b=vm6ZLE1k4bAY60O5SwJtM+0AWGH5eUqJ4x970ylClLF9kx/UFP6SYXYkjZfpapZoBqn2cug6WUKXOA0T8PHDR1chv8ZnLqC8+u85K+SMowLP7Fi4S3BR7e6rNc2wwbEZKfQyLs/QO6WNQYnT6OdmnKd9YBMXnq/feR2hDhW4HAfDITPebeKpWvcu59kdPwNLZ9DNOkW/lihkdFwinGlIphy2DSYhJHMSpFwFdebAD4JDOg7ge7sZkAP6tUTDDyxGckZktUonEfNMoUzXapYS2gxWodXiMqwe7ZrXdSJJXsEOiYP0n+buqVRVENcvuyiCwL7l6uWnSZ56N3WAskulUg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xxDGX7oD9NhKPcS4NTStGsYZCJknJrP3JSaOIlxsgEU=; b=O+hASxDTZipyOC6aXk86c2WlOWkRf0nM2Gg5VHAuiILfhYHpw86Ba06Nlild7HlUjmlHG7Dmn1XfoDnR1mRgOyoQjYx/7Z1Il377lMpxsSaM5sMFzahSyHqJSD50HWzAOA3Bo2bcFTAatB6/71gvFGFEJdT+Gp5husa30OdDsd/VCmbZuxNQT3TLmFfxyE8J9xIgvxJfviDH/YKu9+MwfUWhXdv8WZ5tTcBbQoQvCur59peHty3srBMep6cUjmXSSkLIXEcZTIw8UujilHcFC39olqV6zHLO4CWOkGv4MLahkbL/6x+/w9/m7TC02NCCHZrq25jf12XSnZWQJSaG5w== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 21/32] hw/arm/tegra241-cmdqv: Map VINTF page0 into guest MMIO space Date: Thu, 26 Feb 2026 10:50:45 +0000 Message-ID: <20260226105056.897-22-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AE:EE_|BY5PR12MB4114:EE_ X-MS-Office365-Filtering-Correlation-Id: 31f59f6f-8275-42e3-e92e-08de75253c0b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: GUnvlCuIUh73m6gXUzHwJ7hkaILOWOxZaVQjFAlbcxkVYbeyFfYQU+2zSp6SwdynqjcBhiWYYweL6B2tG2/HIgnKlnEmBliFGLIdg0+JoXzzYbhgXBUSwrMUohwgsqEAJxUquX8WxfN5ekqR4IrNMVn58FxjJUIlCBmFpB7UH9XcLrDGFT0S0Kr8d0Qp7CA9rZy9T8sxgT/T0EWCeDG/DyIVn5LJ9nhgr7lznQFvBMZ9Jtbk9jyRXJEbvoA4kGLjWkgqQX8+L66XfDoUMqSbRDZBr50db1rfKMJlPJF93ggVoF0DiKc207RMNzTfpMk2wg+KEY217/MfAAHUKBA3ZwQzFZOf9HhZ81IAlVXwMqsNBuST243Ba5Pc+qthVaVDvAHKibPMwUGD+i2SegUbmPndxCYzCS8kZdW70qEEUXv/TiKEZNLXzZlBIWxKiMGyp694Xx5VMDp5ZwdvyE1+f0cRT+RLbFa46YklG6D61TXM83rFUN3juFAa03I3cv6TWVGb6pmLk+ySGLVzDx+PHi5WKw0Ea2WeorqsWDkH3wjnKKg9RwskwentjNLNUmiiAE9pu9onEl/0Cn7SWuOe1sAprnFeJye3tWBqzQrm6J7kPZ/0j9BEwp0/KfRsm7Jql/ldvfP635B8bRYJk4O2sLVANRI6XRFcmut83M69VYph41vpVR3xO8sQoOkMDD50drOwAf0XOJDTSdLDHLVIFIocQoMjzh1K2bLChs2JSZtaXmajrXqCe9xHyXlOEr070/AGN+Y8E6p/qLsK+hqdgL9aST4RlmOTT9rPXhWyqAUrcVMKqtqCf+PapM5OUC6zXIlODA/EXcqKn0vq+4I59Q== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BWh/60/Je+6XYvLBmmoxPsRCV4/2U6iHRYwCUPhlfq5iS929Ny9OD9MA4dBX77tYcQ7hf2DnPAHpYVCf2nolq9yiWidpZB+IhGwfAXIuEpWeFVw7O+o3P1xOBkBd4hLQ3pTOvqKJX8BYCHguKyjCFmPzwlbAdzqJlg3RQWDaliEcN3N5f/jQBko9U4lVYqBOwRFSMecNwvcAFjBDeiwzuT85pLM/CBhW8R7Uj4eTI4nV17o8UIMdqNnaTtqv3sXLg/kxC2jEK/G2Nm9pLM17rFXjJefXbKs+PzAGV6s89pyv8Nza+yXPCVnFIvVjkinsEBt3JanqMNe1DQ6NlHz1/jGxrncRUEEcNiFSb+mGBZZWyvz2TZ0LWwGQJYHB4Vad6FjMtzwjt/W6l6UbMbgekohro8BA3UcAFLT776qgazAAnpvcD2qHBpQ76jjZpMir X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:11.1979 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31f59f6f-8275-42e3-e92e-08de75253c0b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4114 Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=skolothumtho@nvidia.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103239077158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen VINTF page0 is backed by host memory returned by the kernel via mmap. Instead of trapping and emulating accesses to this region, map it directly into the guest-visible MMIO space. The VINTF page0 MMIO region is created lazily when the first VCMDQ hardware queue is allocated. When CMDQV or VINTF is disabled, the region is removed. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 1 + hw/arm/tegra241-cmdqv.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 139e14b61b..914977c2ef 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -38,6 +38,7 @@ typedef struct Tegra241CMDQV { qemu_irq irq; IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ]; void *vintf_page0; + MemoryRegion *mr_vintf_page0; =20 /* Register Cache */ uint32_t config; diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 17b9552906..ce144add54 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -178,6 +178,38 @@ static uint64_t tegra241_cmdqv_read(void *opaque, hwad= dr offset, unsigned size) } } =20 +static void tegra241_cmdqv_guest_unmap_vintf_page0(Tegra241CMDQV *cmdqv) +{ + if (!cmdqv->mr_vintf_page0) { + return; + } + + memory_region_del_subregion(&cmdqv->mmio_cmdqv, cmdqv->mr_vintf_page0); + object_unparent(OBJECT(cmdqv->mr_vintf_page0)); + g_free(cmdqv->mr_vintf_page0); + cmdqv->mr_vintf_page0 =3D NULL; +} + +static void tegra241_cmdqv_guest_map_vintf_page0(Tegra241CMDQV *cmdqv) +{ + char *name; + + if (cmdqv->mr_vintf_page0) { + return; + } + + name =3D g_strdup_printf("%s vintf-page0", + memory_region_name(&cmdqv->mmio_cmdqv)); + cmdqv->mr_vintf_page0 =3D g_malloc0(sizeof(*cmdqv->mr_vintf_page0)); + memory_region_init_ram_device_ptr(cmdqv->mr_vintf_page0, + memory_region_owner(&cmdqv->mmio_cmd= qv), + name, VINTF_PAGE_SIZE, + cmdqv->vintf_page0); + memory_region_add_subregion_overlap(&cmdqv->mmio_cmdqv, 0x30000, + cmdqv->mr_vintf_page0, 1); + g_free(name); +} + static void tegra241_cmdqv_free_vcmdq(Tegra241CMDQV *cmdqv, int index) { SMMUv3AccelState *accel =3D cmdqv->s_accel; @@ -236,6 +268,7 @@ static bool tegra241_cmdqv_setup_vcmdq(Tegra241CMDQV *c= mdqv, int index, hw_queue->viommu =3D viommu; cmdqv->vcmdq[index] =3D hw_queue; =20 + tegra241_cmdqv_guest_map_vintf_page0(cmdqv); return true; } =20 @@ -371,6 +404,7 @@ static void tegra241_cmdqv_write_vintf(Tegra241CMDQV *c= mdqv, hwaddr offset, tegra241_cmdqv_mmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status |=3D R_VINTF0_STATUS_ENABLE_OK_MASK; } else { + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); tegra241_cmdqv_free_all_vcmdq(cmdqv); tegra241_cmdqv_munmap_vintf_page0(cmdqv, errp); cmdqv->vintf_status &=3D ~R_VINTF0_STATUS_ENABLE_OK_MASK; @@ -411,6 +445,7 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr o= ffset, uint64_t value, if (value & R_CONFIG_CMDQV_EN_MASK) { cmdqv->status |=3D R_STATUS_CMDQV_ENABLED_MASK; } else { + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); tegra241_cmdqv_free_all_vcmdq(cmdqv); cmdqv->status &=3D ~R_STATUS_CMDQV_ENABLED_MASK; } --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103271; cv=pass; d=zohomail.com; s=zohoarc; b=W6YbyMhecoy2V9iGZ6gE9yn9d9x+NwZxyPPm421tsZsBuvlFsq8xQFkzBZMJhKU1IcDFJGdw9VDC1nGUTqndgE0du3PJOlhCOrGz2dAQSnuoxtyRtH2tgen84w7OzQkp1zqipU6/wbiZCAI0EAotk0CRSI42G7EkwKwoB7jpF30= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103271; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YnHD6DePx9K2xfmOF+WUFcjlE4yDF+Zs0AZtOxp0q4w=; b=Ne995MhqAUJI1raZFjtjnt6kVuhkLeFvyzqrwC4PbL4dpCaLynumBtJ+Ci/nzyeOMVAx3lTsycdb59RouFVvRl77xgLpnesI3RK89uAdPmndUEcDFHG8VoN/REYJ2xL7xH5SpOBNgGWSyJmjL3ngRosRMd212HGiqrcy33yn9zk= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103271981303.6065813791623; Thu, 26 Feb 2026 02:54:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzl-0006oG-6d; Thu, 26 Feb 2026 05:53:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzk-0006np-00; Thu, 26 Feb 2026 05:53:24 -0500 Received: from mail-northcentralusazlp170100001.outbound.protection.outlook.com ([2a01:111:f403:c105::1] helo=CH1PR05CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzi-0000y8-Gd; Thu, 26 Feb 2026 05:53:23 -0500 Received: from SA9P223CA0023.NAMP223.PROD.OUTLOOK.COM (2603:10b6:806:26::28) by SJ1PR12MB6124.namprd12.prod.outlook.com (2603:10b6:a03:459::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.11; Thu, 26 Feb 2026 10:53:17 +0000 Received: from SN1PEPF000397B2.namprd05.prod.outlook.com (2603:10b6:806:26:cafe::3e) by SA9P223CA0023.outlook.office365.com (2603:10b6:806:26::28) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:52:55 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B2.mail.protection.outlook.com (10.167.248.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:15 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:52 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:49 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=vyosYdo3u1OeSgImdFZCFw8uxedjc3esZUc+f6DmumFUSIyfw3FBi90toTfdI/gJ2Uy2FpYBTzwSdDO2flhX19K8VoBwLtqTXjeYPF6DQJEEPznN0zlZf3S+RhqEPLOc4CVl4fLLH1WUQmyCTBVVZumtbsaS3+kZCywOpzabSNwJdMWZMV0MuFGrl40UY7WddNBacQTgwDbTNKfhkwMFG0fwS8RrETF9eSHKEKjjciu8Huc8B66bOgV/RfgZ/uy/6bTyXY1j3vED0kWKzybqBGJZiLR/KSEOWILEdPhPq09i89yEjuT800OmmWgLD8QRnsNsUILtSDC4z3qZzODnsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YnHD6DePx9K2xfmOF+WUFcjlE4yDF+Zs0AZtOxp0q4w=; b=njTX/eEdZLeYmQuy+z0yWTyY25Dsfaq+7p6ZPAnseu+D8A+bV+OqeAEMFEd5+Aud62DojV5uWlVBmzKidG1UY1WfGI3rwYmauW4V+O21IfyqYJsj/AlWzoIO4KDb55IFj5ujh0Ao961y+ZqSOFwJPdLdUHZF3ck9B4XCSzzUYR6P8Y8NyXI1zcWheNzTbdZdEzsQxGpn39cn+7vxO7MtHCDTFD1vIH2u20K82DAypEKu3re/tseNWakhMw66sdzI/Xg4uWHmuxxCQGBX6cbtiwyxm2K1QSCl63RGpVZGdBNAsBaP5EsCW6y5SrHmFjHM42NB1MnztGGIec48W4WEFw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YnHD6DePx9K2xfmOF+WUFcjlE4yDF+Zs0AZtOxp0q4w=; b=kcX9Tj6qKo6GtkarblQjmM8HdRLhc6sHa2f//SbZkPcBowXluih9QCEpSRS20VNgUP20qPH6jenmdmLFuaJXVpwAque8Nr1wDz6exab0+WzuPNfnZjQp24HII+MUZfGUYGdKDfQOwaROUyex+rei/t8LSYrjLtZ3PC+WOKkUAYzVMotPRMw5KBdH7GK5zRWQPpd0yCljzYea94aPkx6cRiMxvf65AFcsyd2IMPr8iSVvWHxBNAN1TyxKlbMt4j6EZ/nLmu1INnqNG+NpcsbFS3vf5lXJZc5CNSYlbfngmXYl56s8h4+2JGNEOV1Diy0dy/p/wPjBnAkSSiYpGMGh9g== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 22/32] hw/arm/tegra241-cmdqv: Add vEVENTQ allocation and free Date: Thu, 26 Feb 2026 10:50:46 +0000 Message-ID: <20260226105056.897-23-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B2:EE_|SJ1PR12MB6124:EE_ X-MS-Office365-Filtering-Correlation-Id: d23282cd-5184-497d-1b81-08de75253ed8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|376014|7416014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: UysgAP8ysrxodLH4elUpIip3pxleDhbSZWly50wNl3fib1jp3VN4MAjhNUVrtz1IIV9LDF+6pvcnrpC4Hu3G2d4z6jjLhsijS/wl5or5oG9MeUOzKFUMfr8ZuOm9eqhQwlV6YurGia6tgDoOmwr/Eyiv2p5exGOmwyeeHpIpfN5KZaQUcCFo7XDP6xf2BkSmYVHjticvoYhtRKDVu1pvWD3TomUuyQu45g8wDn06cCbOkUjRMTr5/Wc34OR9KA6jAIDXS7cRoQNcAhZXvTJ2E+i/qgD2H5folfacbHPaWpWEMrGZq30bPckfDZWSaz4e392zoLf9IIsHanYReyvVmZpkYn01vHeUth7vdoC0oYbEOez7nCVAG/4G+RZxPgwMQFwfVWNdOGkze7+RZeo2pYKdn7HH8OF45QPB996je0Xw+Y3x9FgOgCAAhmiFqrkymen5A+WqgAE6G76hrZRgQjjIi48bM4yG6nZVLdZWiSAciiLOtW2xyzwhoiP83qwgTidRfVZFErTJ0JqjZISa2cG+0KOjaVmbE+exFZ5Y7mMRqbW35LslkwK2i6bbLi5q7360d+Gr4DxPpmJaYfV9Klc3KI6g6LF5OTc9F3wCpVt4B45XMdWVVuoFaqJsXOfDVr+d1i1lmRRrub+wB1OtOYSCxhyMxcdkaNUjnyQBSjtRZ3CLRntvjP5EkxMNclx54jY+Jzfu1KjAIxAKDmjMIxV25g8pycnn3skueRcj3+mny5rYXrHEk73HE9WrxY055RbipWplqajoOpyuVodP2SXPgdRDQMIGMzC8Tg+Lljc5gcxfuDv4tTp8VljoBdR6Seo6VbdAdcX9NNjMYvDtQg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TP8u2JJsUc7PPQEankZZNaCdnixe0YHbBxGUymM/VGIHbVELAfUr2G959EoegTp7HI9sCf0rfpSs3S6atIAcwIGWHv47zafTartAYWB8didK4PlQ8uVFV0g6inguuz/XCmHS7ook+DjwRGzJRAm5b9skJgkON+0gyKXen01KWoxIiqJgZknGO0KRZ4/vz5kxYddPGJPOJVsYfYFHiLQ0/bGo/ATBVEkh70xiKViTuJ4h+J30CvtC0/1sxfeWElQ53vY6Emn37lsPmjYPdLF5npcTep76oM5x0g/yRRhHk9KatAM36pqK9kDVjZJOzJD9dA9DUn3Y1YXIJIQto13MD/kdkZt59KeFgGJOrrbDvhvwsQq8UhyRdhJZC0FsTI26n7f9eJL56OXXBMmGuSZ9h+alYdxsr37kbRD5R+7q+gPxEAMnl38weZXe1JqffwMU X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:15.8966 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d23282cd-5184-497d-1b81-08de75253ed8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6124 Received-SPF: permerror client-ip=2a01:111:f403:c105::1; envelope-from=skolothumtho@nvidia.com; helo=CH1PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103273254158501 Content-Type: text/plain; charset="utf-8" Allocate a CMDQV specific vEVENTQ via IOMMUFD, and add the corresponding teardown path to free the vEVENTQ during cleanup. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 2 ++ hw/arm/tegra241-cmdqv.h | 1 + hw/arm/smmuv3-accel.c | 10 ++++++++- hw/arm/tegra241-cmdqv.c | 47 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 59 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 7d6e4c6b76..4bff90e2c1 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -28,6 +28,8 @@ typedef struct SMMUv3AccelCmdqvOps { uint32_t *out_viommu_id, Error **errp); void (*free_viommu)(SMMUv3State *s); + bool (*alloc_veventq)(SMMUv3State *s, Error **errp); + void (*free_veventq)(SMMUv3State *s); void (*reset)(SMMUv3State *s); } SMMUv3AccelCmdqvOps; =20 diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 914977c2ef..01d446474a 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -37,6 +37,7 @@ typedef struct Tegra241CMDQV { MemoryRegion mmio_cmdqv; qemu_irq irq; IOMMUFDHWqueue *vcmdq[TEGRA241_CMDQV_MAX_CMDQ]; + IOMMUFDVeventq *veventq; void *vintf_page0; MemoryRegion *mr_vintf_page0; =20 diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 4373bbd97b..f6602f51aa 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -576,13 +576,21 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDe= viceIOMMUFD *idev, goto free_bypass_hwpt; } =20 + if (cmdqv_ops && !cmdqv_ops->alloc_veventq(s, errp)) { + goto free_veventq; + } + /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */ hwpt_id =3D smmuv3_accel_gbpa_hwpt(s, accel); if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) { - goto free_veventq; + goto free_cmdqv_veventq; } return true; =20 +free_cmdqv_veventq: + if (cmdqv_ops && cmdqv_ops->free_veventq) { + cmdqv_ops->free_veventq(s); + } free_veventq: smmuv3_accel_free_veventq(accel); free_bypass_hwpt: diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index ce144add54..8cde459b4f 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -487,6 +487,51 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr = offset, uint64_t value, } } =20 +static void tegra241_cmdqv_free_veventq(SMMUv3State *s) +{ + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + IOMMUFDVeventq *veventq =3D cmdqv->veventq; + + if (!veventq) { + return; + } + close(veventq->veventq_fd); + iommufd_backend_free_id(veventq->viommu->iommufd, veventq->veventq_id); + g_free(veventq); + cmdqv->veventq =3D NULL; +} + +static bool tegra241_cmdqv_alloc_veventq(SMMUv3State *s, Error **errp) +{ + SMMUv3AccelState *accel =3D s->s_accel; + IOMMUFDViommu *viommu =3D accel->viommu; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + IOMMUFDVeventq *veventq; + uint32_t veventq_id; + uint32_t veventq_fd; + + if (cmdqv->veventq) { + return true; + } + + if (!iommufd_backend_alloc_veventq(viommu->iommufd, viommu->viommu_id, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, + 1 << 16, &veventq_id, &veventq_fd, + errp)) { + error_append_hint(errp, "Tegra241 CMDQV: failed to alloc veventq"); + return false; + } + + veventq =3D g_new(IOMMUFDVeventq, 1); + veventq->veventq_id =3D veventq_id; + veventq->veventq_fd =3D veventq_fd; + veventq->viommu =3D accel->viommu; + cmdqv->veventq =3D veventq; + + return true; +} + static void tegra241_cmdqv_free_viommu(SMMUv3State *s) { SMMUv3AccelState *accel =3D s->s_accel; @@ -580,6 +625,8 @@ static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D= { .init =3D tegra241_cmdqv_init, .alloc_viommu =3D tegra241_cmdqv_alloc_viommu, .free_viommu =3D tegra241_cmdqv_free_viommu, + .alloc_veventq =3D tegra241_cmdqv_alloc_veventq, + .free_veventq =3D tegra241_cmdqv_free_veventq, .reset =3D tegra241_cmdqv_reset, }; =20 --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103373; cv=pass; d=zohomail.com; s=zohoarc; b=YfoboTLQJOMeYy7ToF1+sjR3zemf4v49yZ0LwkegJcQDu2W8TkxYVTF0ARB/YV2CAgEK43BB4i+CY7DV8k3vIJoVawx6r8/MSq6tYdJZHPqF1L0LeiFCOmgXbi4JuglSweQw4ipCf+V5NPXqknZA8LLnt48wUzr9TQlqB+VuwhU= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103373; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=G4BLP/NinOPuWVcsen0umfOn9ZCCyDrlPUaCh+VyMQk=; b=FX9K3jofXnf/xMSfjCktOqiDlnmGjJJIFs14+dj585Aqb2BVEJdEGHOiI90EVXRdb0lJq/ATLgzfFtj8aiw0Bl0uI6H6DDvgla3LgjpVU5fs3RRhlxPxyjGMIC1SpylEGNZnfGeBP1Lul4iEEpImpC+JngjC4TJ4cIBgJ+JYUfs= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103373762781.9981353820954; Thu, 26 Feb 2026 02:56:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzr-0006tk-DC; Thu, 26 Feb 2026 05:53:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzp-0006r7-7O; Thu, 26 Feb 2026 05:53:29 -0500 Received: from mail-eastusazlp17011000f.outbound.protection.outlook.com ([2a01:111:f403:c100::f] helo=BL2PR02CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzn-00012i-Gy; Thu, 26 Feb 2026 05:53:28 -0500 Received: from SA9P223CA0011.NAMP223.PROD.OUTLOOK.COM (2603:10b6:806:26::16) by MN0PR12MB6032.namprd12.prod.outlook.com (2603:10b6:208:3cc::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.11; Thu, 26 Feb 2026 10:53:20 +0000 Received: from SN1PEPF000397B2.namprd05.prod.outlook.com (2603:10b6:806:26:cafe::c7) by SA9P223CA0011.outlook.office365.com (2603:10b6:806:26::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:53:19 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B2.mail.protection.outlook.com (10.167.248.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:20 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:56 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:53 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=iCidynVrn4nN+hr9gMiY2k2wAjYWFdNqTiarVei0QeocpsNs7CJrwQcrA3xpoTDOjSqmsNUS/eDjND7aksszaMmADNUadtpgelIBZMMK9N34VuC9KuN29uZ9psg6ef8NDa8BWf1k83ZpFsTvaBwahYuGB8MEla1zoAUVGt1Nzu2ughCDHT1/R2uNAYIgAEz8V5eJOqgViaxHCyoJz4Ss+GBlnYfpRjYIeuTfyaJ0wWJDN8Ra2JIy/zYOPV0hcxK0JDO1aKjIlKb4GFjIFatEBRX9haLWnTX38OB3mAss0z1/AYY4WqnFUlBfo2rwqK5lcYjO1tNtiif9+Lv4XVU8Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=G4BLP/NinOPuWVcsen0umfOn9ZCCyDrlPUaCh+VyMQk=; b=aZGsijlK/4JuNBS+EL63LGsBZYYW8kihckGSKj32QNXENGNegwdDO3r4/zrkzMxqrI/C8hJm3okc2X2AGqNZ3ZiJE6C/JF0IiJyAQBHlWT21UtYeekjl9R8LagS4xUrsRvFzG+I1kJqqOvNHd6nrxpa5gTJusK6WmZ8PSP+AikaL7BiEG4EF08DRlo61fwpsE9Ru6P05AdFwrRD1wPg0PbeYQOfdlU2628ZMOL2n0Cdo9xUrrD/E5Uws+6j4Qrk2sHx4Z8MBEGJVPzsna4r0MkROoQETKCz1HsHK7CjPfw5MuGzvrHHqvefpSTcwleVTrpJUz0wgr4WgLU9H6rDalw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=G4BLP/NinOPuWVcsen0umfOn9ZCCyDrlPUaCh+VyMQk=; b=sNontHsoZXdE8pFcIn9+22Zw5z2kSosv1JtNn+tIuV/1MwSwnPkZcg9Sjxk59w31o8y16jSCQYnCuhkoK0ASPcYMTIdZa1mv0TYFYbT/hf/9pIeBHP9dviKNvbvEvdqZgGgzbgaSqRhu0Gj38kL3wJWsXM4hkZ9DgNUTJ6NADvdoayMHCtqRGECETnweiHnK4WQJL1SQzkDRZtRgaF4uaA83lE5taZFLNp3uo1NMZME/lAUOprr2xKUIaFxdlV93pNmNo5/aEl9DaZ7JW9H3wBJMCtvA/5ast47a/cUbT8p0QwE0GVIMwUZITx7bOgQ5NO1eHqXgXwqGV5/0P3nqgg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 23/32] hw/arm/smmuv3-accel: Introduce common helper for veventq read Date: Thu, 26 Feb 2026 10:50:47 +0000 Message-ID: <20260226105056.897-24-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B2:EE_|MN0PR12MB6032:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c4b9d99-cc6d-413e-ce8a-08de75254161 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: IEP6gCz/ME+NYfhmNuEngn2oyiELe+J6mJYYa96OkPcATF7zhjdXuywCFkEVt+ApvQvceTfNWSus8ivWBq1N8MO3yHeJuIUcejxdMC5a8TfT8/C0duMmlaKmGJfBo5DyBIXgGLtLdTUZ1q6vygcH/6l0oWZd0phNmZJ1y1CYL8OAHumULHBlpP6X7Yraug2V61BAwmFMQwQ2Ox6+wzKOhPARkj6CfxDzMWmhAoQSv7nHKqw6qZy+Ple0ttOIv4kLi1ChkGQT3wt0RQv0V9Pioce9vrV+1sck8Ybvp7qNlPsR4l/sdZG9wFhXJI86wp7coAmMLujux0MX3EDXHtE1ZrMYs/duCytL1IxT8dSpmfKRRZUaBiWtTl1jYyhxm2vorj7QK1Z2wDZ0fCSyzzh40nwsTHPvOlClRh74ABoLg4ft44UmC2kGjlfPJjzlEvH9jHnT+xNJ4cmVXHOXRj2UaKEG95dpMu1crqiiMbPBM6K8BA/XchJJZX8YNrwMQ/5h2Yn1Vo01B6gDoEy/uv9ae9pYd+YQ3+OfKgGP1GIcGCq1ilJ7Ado83Sv1zQRzqs/fzcmvZwgLJnRc1KDjD6dpA9ok6qg/ULOaALBrYntQF1NtSunz0RwiIhBvzgNIBjEIp0fNXQiImrQkO5dmY16PAuSBnk+w5nErbdKvbbCNg2Lc30T7TZWRGqgF7olWvMi3auFYvsS1XQzzW/k3FLID9s9KyQsKG7eJ8JchJZX1UZKLkMEldmw86F8pvI05l8jAJzwk4C7beCJlUks88XMf/XUkwhdeDDdsvIQtPd8flA/698UQd+qsFeS3P36ZGL7wvGHMyG4s8SCiNn/ET47ACA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nAaU7slPUzO278Vv+1XhLtjqGVg2W6Km+zNXCJ6ArliqNZ2xi9s1gg0dq5KghoaBNq8m0wvPZ45hLessPVLosSJddz2vY01WoYWGu6uBWmJTTagkqufoiiC9Tgte43rXjfnK0OcS+NYgNDQeB3D1+qINHVxNcmwAafiyOAMoMgc80FSXsf79CqNLCj0FSfz9tEEJZC7Hn/G5U2thoFDRgYfVMNsDirPIfiio127Q6z2uIBSTSjcN22ypfopWkFeGu0Pi4JXa3wvHQ/jYWgmgE5gYBXruEEwom4HEQvxORIJ3WXng7ezgKbtb1uUaxatA/mPcvm5M+DQvxQBZ7SyTNdjqvxIRZc3mcJjrOcT1gV0shDqGQY/2MKM9awQ4n+A049cK/wwbUH4x7sfg7kNkSKBLHieig6qzp1re4fAQpVOU+748KKj9RoypmczxndX+ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:20.1432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c4b9d99-cc6d-413e-ce8a-08de75254161 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6032 Received-SPF: permerror client-ip=2a01:111:f403:c100::f; envelope-from=skolothumtho@nvidia.com; helo=BL2PR02CU003.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103375764158500 Content-Type: text/plain; charset="utf-8" Move the vEVENTQ read and validation logic into a common helper. The helper performs the read(), checks for overflow and short reads, validates the sequence number, and updates the sequence state. This helper can be reused in the subsequent patch for Tegra241 CMDQV vEVENTQ support. Error handling is slightly adjusted: instead of reporting errors directly in the read handler, the helper now returns errors via Error **. Sequence gaps are reported as warnings. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 2 ++ hw/arm/smmuv3-accel-stubs.c | 6 ++++ hw/arm/smmuv3-accel.c | 67 ++++++++++++++++++++++--------------- 3 files changed, 48 insertions(+), 27 deletions(-) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index 4bff90e2c1..c349981e79 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -70,6 +70,8 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd= , SMMUDevice *sdev, Error **errp); void smmuv3_accel_idr_override(SMMUv3State *s); bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp); +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp= ); void smmuv3_accel_reset(SMMUv3State *s); =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c index 870fc2a71c..1d5d3bb10c 100644 --- a/hw/arm/smmuv3-accel-stubs.c +++ b/hw/arm/smmuv3-accel-stubs.c @@ -42,6 +42,12 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **= errp) return true; } =20 +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp) +{ + return true; +} + void smmuv3_accel_idr_override(SMMUv3State *s) { } diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index f6602f51aa..5f296ea763 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -391,47 +391,60 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void= *cmd, SMMUDevice *sdev, sizeof(Cmd), &entry_num, cmd, errp); } =20 -static void smmuv3_accel_event_read(void *opaque) +bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, + void *buf, size_t size, Error **errp) { - SMMUv3State *s =3D opaque; - IOMMUFDVeventq *veventq =3D s->s_accel->veventq; - struct { - struct iommufd_vevent_header hdr; - struct iommu_vevent_arm_smmuv3 vevent; - } buf; - enum iommu_veventq_type type =3D IOMMU_VEVENTQ_TYPE_ARM_SMMUV3; - uint32_t id =3D veventq->veventq_id; uint32_t last_seq =3D veventq->last_event_seq; + uint32_t id =3D veventq->veventq_id; + struct iommufd_vevent_header *hdr; ssize_t bytes; =20 - bytes =3D read(veventq->veventq_fd, &buf, sizeof(buf)); + bytes =3D read(veventq->veventq_fd, buf, size); if (bytes <=3D 0) { if (errno =3D=3D EAGAIN || errno =3D=3D EINTR) { - return; + return true; } - error_report_once("vEVENTQ(type %u id %u): read failed (%m)", type= , id); - return; + error_setg(errp, "vEVENTQ(type %u id %u): read failed (%m)", type,= id); + return false; } - - if (bytes =3D=3D sizeof(buf.hdr) && - (buf.hdr.flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) { - error_report_once("vEVENTQ(type %u id %u): overflowed", type, id); + hdr =3D (struct iommufd_vevent_header *)buf; + if (bytes =3D=3D sizeof(*hdr) && + (hdr->flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) { + error_setg(errp, "vEVENTQ(type %u id %u): overflowed", type, id); veventq->event_start =3D false; - return; + return false; } - if (bytes < sizeof(buf)) { - error_report_once("vEVENTQ(type %u id %u): short read(%zd/%zd byte= s)", - type, id, bytes, sizeof(buf)); - return; + if (bytes < size) { + error_setg(errp, "vEVENTQ(type %u id %u): short read(%zd/%zd bytes= )", + type, id, bytes, size); + return false; } - /* Check sequence in hdr for lost events if any */ - if (veventq->event_start && (buf.hdr.sequence - last_seq !=3D 1)) { - error_report_once("vEVENTQ(type %u id %u): lost %u event(s)", - type, id, buf.hdr.sequence - last_seq - 1); + if (veventq->event_start && (hdr->sequence - last_seq !=3D 1)) { + warn_report("vEVENTQ(type %u id %u): lost %u event(s)", + type, id, hdr->sequence - last_seq - 1); } - veventq->last_event_seq =3D buf.hdr.sequence; + veventq->last_event_seq =3D hdr->sequence; veventq->event_start =3D true; + return true; +} + +static void smmuv3_accel_event_read(void *opaque) +{ + SMMUv3State *s =3D opaque; + IOMMUFDVeventq *veventq =3D s->s_accel->veventq; + struct { + struct iommufd_vevent_header hdr; + struct iommu_vevent_arm_smmuv3 vevent; + } buf; + Error *local_err; + + if (!smmuv3_accel_event_read_validate(veventq, + IOMMU_VEVENTQ_TYPE_ARM_SMMUV3, &= buf, + sizeof(buf), &local_err)) { + warn_report_err_once(local_err); + return; + } smmuv3_propagate_event(s, (Evt *)&buf.vevent); } =20 --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103465; cv=pass; d=zohomail.com; s=zohoarc; b=bi2Kp15KWxMd70Ia7ZvGOFRUSc3Q1SV3BwrS1g1SDcH/i4nCc2U2K41jAPAbOqpoBlQjNcWRo/ZYxZVMjD0McFb7Ah4McYF6OB0CdbJwdoyT2e4z0efiXH1fr8pZ3nRAYcIJdjxMMKjUpO1oTO3kCC0VbAhH8x4Vn6cUNsY6N74= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103465; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=h/c8blDUhOE7bV+G0gEI0dRRnDqaAgxiGgCB18bAe8w=; b=aQjmo//5qPdqXr3A1xDC49yVL6JUoaGwUg977hbJkkKZKONvtLyom7GiRe5gzMf60O6vyu6cMZdzcNs/aKpiz98bG1L0I9dVvoILnFWEcyJ3GI8MMUgYjtVfw3qRsPlBrfFGMNKIZZc9MKaCe8jHkE8YJlwO0grtXPEg4v0m5sU= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103465419346.3441212568024; Thu, 26 Feb 2026 02:57:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzv-0006wP-8a; Thu, 26 Feb 2026 05:53:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzt-0006vY-P3; Thu, 26 Feb 2026 05:53:33 -0500 Received: from mail-westus3azlp170120001.outbound.protection.outlook.com ([2a01:111:f403:c107::1] helo=PH8PR06CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzs-00013a-45; Thu, 26 Feb 2026 05:53:33 -0500 Received: from SA9P223CA0016.NAMP223.PROD.OUTLOOK.COM (2603:10b6:806:26::21) by CYYPR12MB8921.namprd12.prod.outlook.com (2603:10b6:930:c7::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.11; Thu, 26 Feb 2026 10:53:24 +0000 Received: from SN1PEPF000397B2.namprd05.prod.outlook.com (2603:10b6:806:26:cafe::8a) by SA9P223CA0016.outlook.office365.com (2603:10b6:806:26::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:53:02 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B2.mail.protection.outlook.com (10.167.248.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:23 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:00 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:52:57 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=POllceQoF0pgnphqP/KZm6G3zcwDLJ8OrbN9WwgqcQ0NaYy9eVET0Gl3e0qVM4OYfkwMq5WAOtyVGdNFD7iLNrbiWbBdCxfnTREAcAQxHdX8Le+m9T/hWeOD72lqHtRyDIEdk9OpaZanDMguNZTmBhfY+uhFpScHAUPc+8cNe8rCl0LO8XSxgtpfZVz4aefHKfgh/XVpPKBTEfFSJtWdGahjAsfw1fZLP7oleu/I5jOLPeKuBrl/Hq+CbV6UY4Hz4qWwHRp5B61PGLfShwHMdol64ihj8y2uK2zZzohVb/maz1htDNnzYFwcg98LH+eVlfO2/86cvGN1UXvls774kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=h/c8blDUhOE7bV+G0gEI0dRRnDqaAgxiGgCB18bAe8w=; b=JFMDwpxLe17FIYXsCrc5h9BeSy0gK0HwShdec/41KTJ/tF2TzPUVZQ8hhuL/Pgw/PhNoccNXm5guVX+/g07NzZXRg7qLIg353Dv4YICabKsMHtsrZMo2X0MBltRl61RtRmecE9B/3YemjGWGphtPp0eZ1InWnCD+qSYKKpuHHlL6HNyLxwU4M4HTrFqufLjMhkoZMj9tyU7OEePUJj/OjML+wmjWNUPksVUWmtCaYDVUDPqozdAZy8vATSF1D/fRxVg4CeJbetIPmca8LRJcdnAVClGew8X4lFylTrllj3CibfxJVI8qwHvMomqHBiAcLJIYknxHlsLwp++NICtuvw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h/c8blDUhOE7bV+G0gEI0dRRnDqaAgxiGgCB18bAe8w=; b=aDZLeCY/WlDw0BPIWIBmlsIGvqYCB0320zPU3uykDCcgtoKFPz5XiHXO3mlpPGT/XeEMRSav+dCd+eZr1wMtql3aKVTIS8a/e6qbD0WBkBMJnZPJgEGPQ/zgjcXIcS5D9CkafhqgJA0FAqHkONj3mztqI+og4t0TMTGdnh26O+P4ou1Sh22qLOPjWbVD2DSVLDsJ/2uBbdCrlfXtIsTXvFaCdq+R9P+qytaN+UhlquvymkAJc+ceqwRndQNCo7p4co8CZwXHEWLz/e/5Ffay6kbuwonZZqrca9Z/mHC0xv8Sq1JyQTaebd90rphcqjjtF245tqkUi342Baiu9lGLvg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 24/32] hw/arm/tegra241-cmdqv: Read and propagate Tegra241 CMDQV errors Date: Thu, 26 Feb 2026 10:50:48 +0000 Message-ID: <20260226105056.897-25-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B2:EE_|CYYPR12MB8921:EE_ X-MS-Office365-Filtering-Correlation-Id: e55079d9-9032-4fc8-29c6-08de75254395 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: 1MRXbAJt47qw4myJOZvZBd4VIR3NErA4xhaUkRpTNLbXGEgdp7QKcK23AJtBfdXiKAq/WH4lvq9Y2dmTDH97EwCSqbMU75dDxEHcXRnqvVOSqQ2wzIdcUsYuHeCDu//orcCzy/BSozsUcEc1QBv+e8AmRogYQg0Km/MetGraaxX5GjZBu3CqXt9Yq3DAwb0ssP0iUooopK03wqlSxxn2o7Kd9ggD1z3dJFt80M4CC91odxij2pV1LEOzwGRJ5mkTBmHFG79H+tF3kbyqeuUVLX3q2gUSempM4UQinbyyRknwO6Otg2gIXr8tAhZUOW9ltMMrvR1Wlv6NZrGDyO9qsqj6Uu3B3V+unnGgBHbYHeEsV0HrDetLrjbcU2eBw9AT9g7PYHm70WMWztCHTV+naedBLiShWvbUHQVLC3MKGDqjr92ncs+mjE/Feq1v6urbAIibVASGBDddzPgMMQ5jo5uO7J3Cl8sp9e/eA994078WPpHnC9TBH9pLet8wvYL3dx3LUwiPGOWtFKuXM//bSd6d1+0TFpz2e7Vbf75RkGLZf+jeMTUE9Lo5hRidKzOSoP7P22rD+7VahdrGwI9/MdRsg5ZpVdT5JUQGUVJKN5WDcAuSgDhjjHyyg+l9btc7o9on46ffcJFVpyWFoICJpKu4K/ROCekRZ9hYN1bXXQ8Wdx99trwrYChsldZXwqmk+uSv11j9cGMNA+ic1LCKOhU13gF0uWFyKGAk9g0vLQNTTBbXVqp014M0F+8iLb7D1sK+B8t16U8CIuoQD2iJ40FnZSBdaJQ0T6jzaeu7GG5XTGgFu0/6poGNYkBcaS1eJrud3ca4t2juPe3ayvUizA== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MwvVyp1/Qaw7qrKMfB9eyzdF6x0e3sQVeYKgLz4wMVAU/XgkUUrI8sDw9JRYAIu4HLk5E3uWimBNln6DSs4ScW6q5ulxfGid7T/I72tf8O/OlSJDmPl/hwyzkPgKuIAjGJFrYL4UBbzXY7xesnIaMfx9QlGvxbkr6UdIl8xL1nmu2sdk41V/D/qx/A+oytMbI5H/NQJoEk0Hzvo8+69b1fSEzLzySjp7z9OrPw3VySQ90sH8xx3ge0J4OhOf7em+F1bW5bOEuFSg9RV0FyNWP0gF0s2ZqwUyYWAN4p5ZE5RXpBUozN0MAPyyoHlkTqpD1S9Bue5lW2fL2xJJVTLUEpiG2BvEQGngrYr9w/pDrRCFve3esCpxZwV77eWx9rNwOor1ujQD0mcUAenNj9kzZJ2kBRnyRNojOhv9xZ7iBitZVJWGPBAQxzFOZH3L0LZu X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:23.8207 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e55079d9-9032-4fc8-29c6-08de75254395 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8921 Received-SPF: permerror client-ip=2a01:111:f403:c107::1; envelope-from=skolothumtho@nvidia.com; helo=PH8PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103466154158500 Install an event handler on the CMDQV vEVENTQ fd to read and propagate host received CMDQV errors to the guest. The handler runs in QEMU=E2=80=99s main loop, using a non-blocking fd regis= tered via qemu_set_fd_handler(). Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 58 +++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 3 +++ 2 files changed, 61 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 8cde459b4f..99b85e698f 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -9,8 +9,10 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "trace.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/core/irq.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 @@ -487,6 +489,43 @@ static void tegra241_cmdqv_write(void *opaque, hwaddr = offset, uint64_t value, } } =20 +static void tegra241_cmdqv_event_read(void *opaque) +{ + Tegra241CMDQV *cmdqv =3D opaque; + IOMMUFDVeventq *veventq =3D cmdqv->veventq; + struct { + struct iommufd_vevent_header hdr; + struct iommu_vevent_tegra241_cmdqv vevent; + } buf; + Error *local_err; + + if (!smmuv3_accel_event_read_validate(veventq, + IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQ= V, + &buf, sizeof(buf), &local_err)) { + warn_report_err_once(local_err); + return; + } + + if (buf.vevent.lvcmdq_err_map[0] || buf.vevent.lvcmdq_err_map[1]) { + cmdqv->vintf_cmdq_err_map[0] =3D + buf.vevent.lvcmdq_err_map[0] & 0xffffffff; + cmdqv->vintf_cmdq_err_map[1] =3D + (buf.vevent.lvcmdq_err_map[0] >> 32) & 0xffffffff; + cmdqv->vintf_cmdq_err_map[2] =3D + buf.vevent.lvcmdq_err_map[1] & 0xffffffff; + cmdqv->vintf_cmdq_err_map[3] =3D + (buf.vevent.lvcmdq_err_map[1] >> 32) & 0xffffffff; + for (int i =3D 0; i < 4; i++) { + cmdqv->cmdq_err_map[i] =3D cmdqv->vintf_cmdq_err_map[i]; + } + cmdqv->vi_err_map[0] |=3D 0x1; + qemu_irq_pulse(cmdqv->irq); + trace_tegra241_cmdqv_err_map( + cmdqv->vintf_cmdq_err_map[3], cmdqv->vintf_cmdq_err_map[2], + cmdqv->vintf_cmdq_err_map[1], cmdqv->vintf_cmdq_err_map[0]); + } +} + static void tegra241_cmdqv_free_veventq(SMMUv3State *s) { SMMUv3AccelState *accel =3D s->s_accel; @@ -496,6 +535,7 @@ static void tegra241_cmdqv_free_veventq(SMMUv3State *s) if (!veventq) { return; } + qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL); close(veventq->veventq_fd); iommufd_backend_free_id(veventq->viommu->iommufd, veventq->veventq_id); g_free(veventq); @@ -510,6 +550,7 @@ static bool tegra241_cmdqv_alloc_veventq(SMMUv3State *s= , Error **errp) IOMMUFDVeventq *veventq; uint32_t veventq_id; uint32_t veventq_fd; + int flags; =20 if (cmdqv->veventq) { return true; @@ -523,13 +564,30 @@ static bool tegra241_cmdqv_alloc_veventq(SMMUv3State = *s, Error **errp) return false; } =20 + flags =3D fcntl(veventq_fd, F_GETFL); + if (flags < 0) { + error_setg(errp, "Failed to get flags for vEVENTQ fd"); + goto free_veventq; + } + if (fcntl(veventq_fd, F_SETFL, O_NONBLOCK | flags) < 0) { + error_setg(errp, "Failed to set O_NONBLOCK on vEVENTQ fd"); + goto free_veventq; + } + veventq =3D g_new(IOMMUFDVeventq, 1); veventq->veventq_id =3D veventq_id; veventq->veventq_fd =3D veventq_fd; veventq->viommu =3D accel->viommu; cmdqv->veventq =3D veventq; =20 + /* Set up event handler for veventq fd */ + qemu_set_fd_handler(veventq_fd, tegra241_cmdqv_event_read, NULL, cmdqv= ); return true; + +free_veventq: + close(veventq_fd); + iommufd_backend_free_id(viommu->iommufd, veventq_id); + return false; } =20 static void tegra241_cmdqv_free_viommu(SMMUv3State *s) diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 3457536fb0..76bda0efef 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -72,6 +72,9 @@ smmuv3_accel_unset_iommu_device(int devfn, uint32_t devid= ) "devfn=3D0x%x (idev dev smmuv3_accel_translate_ste(uint32_t vsid, uint32_t hwpt_id, uint64_t ste_1= , uint64_t ste_0) "vSID=3D0x%x hwpt_id=3D0x%x ste=3D%"PRIx64":%"PRIx64 smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_i= d) "vSID=3D0x%x ste type=3D%s hwpt_id=3D0x%x" =20 +# tegra241-cmdqv +tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103299; cv=pass; d=zohomail.com; s=zohoarc; b=iNhbNSeEPFu8kEzjXo4loo2OdrHh5wAQpzNQpcdr+rZRdypMqe3PPiDj2SPZ+mQcwmvOhI3+VpyaO49AvI1kffGkb+qDbV5t5nVsSGald7PFfSX0K98RuVipkHDpZ/PqxPsBp3pPyJuS8QNpSspStWXMKs75S+MOQkgBvrAx2v8= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103299; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1/72YRWM+mVm23vb5IbHHiwmc/mHd/68sDgMPUM6iuo=; b=WudBTfOH51EHOZDrC6IhVK4HdWn/xix8uF7wEOFnpMa/R3rG0DJ5QBA53VZl+ljUjp2gBzM6ZuCkj2ajg+m41BDrh33U1MSexQ8u9zNttIRo1WjPzYPdLNJoMO3WYMwWx5MZ8sM6DXZxtuzWhDht7WkQVIfLTa17T+9P1SbcWvU= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103299383358.7290382783199; Thu, 26 Feb 2026 02:54:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzw-0006xG-MV; Thu, 26 Feb 2026 05:53:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzu-0006vs-Dy; Thu, 26 Feb 2026 05:53:34 -0500 Received: from mail-eastus2azlp170100001.outbound.protection.outlook.com ([2a01:111:f403:c110::1] helo=BN1PR04CU002.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzs-00013m-Pl; Thu, 26 Feb 2026 05:53:34 -0500 Received: from DS7PR03CA0035.namprd03.prod.outlook.com (2603:10b6:5:3b5::10) by DS5PPF7671D5CC0.namprd12.prod.outlook.com (2603:10b6:f:fc00::653) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9611.10; Thu, 26 Feb 2026 10:53:25 +0000 Received: from DM2PEPF00003FC7.namprd04.prod.outlook.com (2603:10b6:5:3b5:cafe::4a) by DS7PR03CA0035.outlook.office365.com (2603:10b6:5:3b5::10) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.22 via Frontend Transport; Thu, 26 Feb 2026 10:53:25 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC7.mail.protection.outlook.com (10.167.23.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:24 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:04 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:01 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DcvrjCteGOO4nx4dhfEpmo2h/824uPWcYGcyMdUSwuJRYhffGkG6wjLrNg1lIZDz/Va3aEXxvYjbrXH9DxhYTx/BwobXfoGic7c0orjwLv98uLfCy/NF29btU5wQl8FHkFDS7bnXhSSc63lwHJ68OO8+wrhjwyZ0dmMhzSIkRPkSWdOZfzjFFgezc91uIsyn9zCVQdhTwLPRXTb5QyjvO2cLYYsGtkHAnQfDzYY1eDdebkb/zm4V4XUZFngDSUv4t9Ts911XJaGjbHuxFjQ4tNy7H6ok7/TZHtEtCCoGFzwei/vWxR6UTWvxq5QAHlQ5A5q0SC5ZfuoylcX03QIAmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1/72YRWM+mVm23vb5IbHHiwmc/mHd/68sDgMPUM6iuo=; b=pCRZ09B8pbzJSY0IeHwTIIQnD1c7hMMmfhNlEytNmP+hPpQml5j9lAp0QspRZx4CnYxoEEBd7sZnq/v1l3O/VnZD4nehJts6e0C5eskPaXcHDByjehnhkQwh3+CvRP7VsMtmPwaSzCV89sRzXVA5G0KJTWQoOGcR5wkWO4llbKT/o7EI607a0juteoJXb91wSxC6iAU3FUghU5jlF4pJLuABbMY1JAmDk9nBUqCBeloH+OfS+7mKabNUC23l2f/7/FVJUpLQymk2F9kZ+/9fPBJg1QLcJLvYyhuf4umYq0pkU8FaS+abFVVdiIgx4fT7+y1SZkbhSK3atdQMOW7y6Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1/72YRWM+mVm23vb5IbHHiwmc/mHd/68sDgMPUM6iuo=; b=WYMS5B0wlRudD8S1zU2LplE/iKtk2/IVl8AerJGZPoDLiveXjB9bJEJFkAZdT5O9/zSBAWF9nAJ9nRIm980Y2WI/3+LAT7Ijl73KGCf3Vu5pWaH5ydoXDbozddc9QuY4/gvSMyw8CxH9kn/+Tb1gYe+yp1pbzi/faf6rOWxiCmW3PKWXjqFZjeduTecmz9/sWewhfRyrBbDeWXxBMM0HSjXfHHDDdfx6CnlFEIBhnG6VnMdjjt/dty4kxKwUHORRotwKZV0Pe8LBmcrf9qqn9HXdHL3F+6Gk97AcJvUQ9itzhuP028a1ZhJcy1JFxVt8FfhS0oxc3BJ2g9sR9Vewkg== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 25/32] hw/arm/tegra241-cmdqv: Add reset handler Date: Thu, 26 Feb 2026 10:50:49 +0000 Message-ID: <20260226105056.897-26-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC7:EE_|DS5PPF7671D5CC0:EE_ X-MS-Office365-Filtering-Correlation-Id: c92c1a8d-e88a-44b2-2184-08de7525442e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|7416014|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: iCw7Rru0MzKTmzUo4hucKf8godBSsJsuhfQBT1ryZGg4v8I/wNtyeQ4K3RQhZ/lS6Zo8en44ceaEFkBEexzw6EmM+UKy/3GKJfDzcIS7bgfwaRBKlc+QSuoQDkZLu3vlOqUOCdCQsoNj7DW4swfLvPtVvy9wnfROSyEZwF6IYwC26Z7DFNegN88oOixf3eLlFvIdoXsa5yt3JO2ZrKFRXhlyX01eHHLPC+kqsDLAqnmvk1G2YP16Sa7Wyjwj9MoCpHpc2EsMRZ9YcCxYzkWwdIjf1esaMAaLDyiUDIC8u0Tmc4wgOObsxY+3arpsG3QxIgqZCvKydWpYV389nXzuU9B1BhfoK5adUUdd0JOOdlXeDB03x5HolSXrXDX9qxIMaWH+eG5llMf/9FF2JAnxuOtKYEPkgCWsINGYw0lJqS94chBSeWoXDBc+yJENyWUtjiAUoYzMX1IwhvkEG1HnES2WtHR+EWlgj5IFXUikx3RVpPXaLwjEPG+yL5+zfHyyTwKdwKA4hN5ZClOXUjLUa7qlGt6wgzePnQn5RFOkqLt+P7btp/XlRbyGxHwT9rgWVc4UapB8i7z9WZkEbV3NfIpcmiEiBlA2qA0/D5YmEwBBbm3AZLSHLtsBt/Usn+oxBKzUK1TjxrhRyjrNpUuerqhYuNzm3eM/u5E+7QDtTACpGhHwVcX6hC3nJGCwzIif71i0h+E97jyxENiDUn+O1ztsj8hcK1dyeH+d8LjRjTfJi1PLUcUvdrJQhfb88fdAdqPbbCrhU39myeOGKtIaMjr6bC6G5XazlyZUnupfCku1UzYknXl8ulDqy2PI+5TDiqzJAtlOMX5Y4vv+7bWk6Q== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: i1plI1zwSP4FtnIa2TjxjZa9/Y7G8aqb6D/roeETxHdlk1ig7IbIiIoV7I5AaDpcdI6WAANqrYNrT06Zj4GHH3mksi1z9GxJNE7e8I9VSihkK72zv206AUPFQLoKiGCr3fU483uFyxbVw/TdZ+eIEd3aGKinc22nS5xh0jOk7S6tqQD1fK1w9hNUcg9UTdQ33t9Itw8k2t4rZ4Oaq6Bo2dcNEpV8BY8zIxncKVnbRUHOhLVAXdU84jaXEE5A6fkZkp2QW4wrVnj0XoDbpELywBa7EJ2x3GfsgfOzGokIkWsZOx5Pbh9LekxzobeUwq6+Xq+LV7e8ZTHVN3hcS6L1+/NQ3vb+oAQyPrG+OjjAqMRwNmsmVJswtSt2Dm9QFxuj6eRSlAdcA84e0E8hI5wmylu2qQ4IepXU3VWsS+lQTFL0Wq8fMO6XigusUGQDnEdl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:24.8499 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c92c1a8d-e88a-44b2-2184-08de7525442e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF7671D5CC0 Received-SPF: permerror client-ip=2a01:111:f403:c110::1; envelope-from=skolothumtho@nvidia.com; helo=BN1PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103301388158500 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Introduce a reset handler for the Tegra241 CMDQV and initialize its register state. CMDQV gets initialized early during guest boot, hence the handler verifies that at least one cold-plugged device is attached to the associated vIOMMU before proceeding. This is required to retrieve host CMDQV info and to validate it against the QEMU implementation support. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.h | 2 ++ hw/arm/smmuv3-accel.c | 12 +++++++++- hw/arm/tegra241-cmdqv.c | 50 +++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + 4 files changed, 64 insertions(+), 1 deletion(-) diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index 01d446474a..96a737eb4e 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -72,6 +72,8 @@ FIELD(CONFIG, CMDQ_MAX_CLK_BATCH, 4, 8) FIELD(CONFIG, CMDQ_MAX_CMD_BATCH, 12, 8) FIELD(CONFIG, CONS_DRAM_EN, 20, 1) =20 +#define V_CONFIG_RESET 0x00020403 + REG32(PARAM, 0x4) FIELD(PARAM, CMDQV_VER, 0, 4) FIELD(PARAM, CMDQV_NUM_CMDQ_LOG2, 4, 4) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 5f296ea763..9a570b8af9 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -774,7 +774,11 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, QLIST_REMOVE(accel_dev, next); trace_smmuv3_accel_unset_iommu_device(devfn, idev->devid); =20 - if (QLIST_EMPTY(&accel->device_list)) { + /* + * Keep the vIOMMU alive when CMDQV is present, as the vIOMMU to host + * SMMUv3 association cannot be changed via device hot-plug. + */ + if (QLIST_EMPTY(&accel->device_list) && !accel->cmdqv) { smmuv3_accel_free_viommu(accel); } } @@ -966,6 +970,12 @@ void smmuv3_accel_reset(SMMUv3State *s) /* Attach a HWPT based on GBPA reset value */ smmuv3_accel_attach_gbpa_hwpt(s, NULL); =20 + if (s->cmdqv =3D=3D ON_OFF_AUTO_ON && QLIST_EMPTY(&accel->device_list)= ) { + error_report("cmdqv=3Don: requires at least one cold-plugged " + "vfio-pci device"); + exit(1); + } + if (accel->cmdqv_ops && accel->cmdqv_ops->reset) { accel->cmdqv_ops->reset(s); } diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 99b85e698f..5afdc5c8a4 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -8,6 +8,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/log.h" #include "trace.h" =20 @@ -617,8 +618,57 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUD= eviceIOMMUFD *idev, return true; } =20 +static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) +{ + int i; + + cmdqv->config =3D V_CONFIG_RESET; + cmdqv->param =3D + FIELD_DP32(cmdqv->param, PARAM, CMDQV_VER, TEGRA241_CMDQV_VERSION); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_CMDQ_LOG2, + TEGRA241_CMDQV_NUM_CMDQ_LOG2); + cmdqv->param =3D FIELD_DP32(cmdqv->param, PARAM, CMDQV_NUM_SID_PER_VM_= LOG2, + TEGRA241_CMDQV_NUM_SID_PER_VM_LOG2); + trace_tegra241_cmdqv_init_regs(cmdqv->param); + cmdqv->status =3D R_STATUS_CMDQV_ENABLED_MASK; + for (i =3D 0; i < 2; i++) { + cmdqv->vi_err_map[i] =3D 0; + cmdqv->vi_int_mask[i] =3D 0; + cmdqv->cmdq_err_map[i] =3D 0; + } + cmdqv->vintf_config =3D 0; + cmdqv->vintf_status =3D 0; + for (i =3D 0; i < 4; i++) { + cmdqv->vintf_cmdq_err_map[i] =3D 0; + } + for (i =3D 0; i < TEGRA241_CMDQV_MAX_CMDQ; i++) { + cmdqv->cmdq_alloc_map[i] =3D 0; + cmdqv->vcmdq_cons_indx[i] =3D 0; + cmdqv->vcmdq_prod_indx[i] =3D 0; + cmdqv->vcmdq_config[i] =3D 0; + cmdqv->vcmdq_status[i] =3D 0; + cmdqv->vcmdq_gerror[i] =3D 0; + cmdqv->vcmdq_gerrorn[i] =3D 0; + cmdqv->vcmdq_base[i] =3D 0; + cmdqv->vcmdq_cons_indx_base[i] =3D 0; + } + return; +} + static void tegra241_cmdqv_reset(SMMUv3State *s) { + SMMUv3AccelState *accel =3D s->s_accel; + Tegra241CMDQV *cmdqv =3D accel->cmdqv; + + if (!cmdqv) { + return; + } + + tegra241_cmdqv_guest_unmap_vintf_page0(cmdqv); + tegra241_cmdqv_munmap_vintf_page0(cmdqv, NULL); + tegra241_cmdqv_free_all_vcmdq(cmdqv); + + tegra241_cmdqv_init_regs(s, cmdqv); } =20 static const MemoryRegionOps mmio_cmdqv_ops =3D { diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 76bda0efef..ef495c040c 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -74,6 +74,7 @@ smmuv3_accel_install_ste(uint32_t vsid, const char * type= , uint32_t hwpt_id) "vS =20 # tegra241-cmdqv tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" +tegra241_cmdqv_init_regs(uint32_t param) "hw info received. param: 0x%04X" =20 # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103404; cv=pass; d=zohomail.com; s=zohoarc; b=KQfegyf/r72qV4zSdomW22sRWGd2hgpv72mxNDW7P2Ho+jGChUsTt2IUgjpxsaAEpa9KbC06SrB71d5UmOmKoAJRYoF34sMLVVBn2lP7KW70z6bMeQNwNPgvGsjhCCvSuZyryhrGdixEB12wfNns4Vlrj8UGoVcJgGOsYC4TUpk= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103404; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=S61x7R63ORUo7+JtXUZhMBJsd312E3/fyghDga51pPs=; b=PatFI/QlvjpkBXQCSO5nOPlorNr49Dy0N1UJz3pJw9de6dveq/7HWKOE6HnJ5BRnvjJH/Lrhx1GJUMj1kX/ukICOEIT7scsvHOwjEubpBFc++1r2yXZKWkRrV3EF/t3srwe72iPYvcXbaxbtiS+bTdGyVUL2TiIFJd9fwqcol6s= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103404534583.6449549219111; Thu, 26 Feb 2026 02:56:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvYzy-0006y2-Qi; Thu, 26 Feb 2026 05:53:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzw-0006xR-Rr; Thu, 26 Feb 2026 05:53:36 -0500 Received: from mail-westusazlp170120002.outbound.protection.outlook.com ([2a01:111:f403:c001::2] helo=SJ2PR03CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzv-000143-AO; Thu, 26 Feb 2026 05:53:36 -0500 Received: from DS7PR03CA0060.namprd03.prod.outlook.com (2603:10b6:5:3b5::35) by IA0PR12MB8325.namprd12.prod.outlook.com (2603:10b6:208:407::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:53:29 +0000 Received: from DM2PEPF00003FC7.namprd04.prod.outlook.com (2603:10b6:5:3b5:cafe::8f) by DS7PR03CA0060.outlook.office365.com (2603:10b6:5:3b5::35) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:53:28 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC7.mail.protection.outlook.com (10.167.23.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:28 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:08 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:05 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=qk0P8M6LXgRFcf97qEUuEcJFYl1lm7czgiDGOPz03iAzoxw87hBW21O21GKi8+EnXU+sYLiav/Gk49z1bEWJnqh3c/EYSipJfiCeCVqIcr+Fqv3iR4nW7wYsJX2NGfcFosjNUF3RW8b+5jEGKkXjFGdmalovTwGZXQQRCCyUyktH6B7W+cPXviqtRzBGZBOnVJRylwc/FP8wCtD5XXO9i1VdbpnS/bY7hEBZGktSmsF8Mfiy0KBZK4fZ5jY73Vj4WOWSkSs0Rk02PFTp3iajsCbh/PzKJu2bmKWTBqJ0ncey/FIruqy2fbbCW/Rql1Qsq5bCI6jYb3jKiz3o++3yrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=S61x7R63ORUo7+JtXUZhMBJsd312E3/fyghDga51pPs=; b=dwZp7mpvmBBFitmtp0u0ZIRazT7I8mePE0iZbgKnjkfRHfshb9CtgTwEE3Zf5GPAMusKylNHwgULPY3kDA2vfBEWTq2st5WT3zxNbXh3xeQCgBAjhzCxAQ0Xy0YqOm1Vwhecy83ZpYTpB2g/4glZUMMvnufhHxiWotFLUsz535rQsen3s8JthfNwNmz+0j5mSfvi0Qd/64qNZGeq8liFD10OP4HLS9BixAlX+H2XeUPR8cGCH7KSVfV8jDzcg9OPjJtMrBEB7QZFwKYTDxv4vM4p4EfT3AreX9SdzUD0YHtCMiQ52gOnjuQKUBV7N6O/pU1eK7R455WePh5f0rQsgQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=S61x7R63ORUo7+JtXUZhMBJsd312E3/fyghDga51pPs=; b=piKbn7qrSsrc57f7IxUNDoNU7VFWNqmM4hPaTzqKe82HOiV3ScHXfBa01VoYSav/WPXC82h28h0KNt4KF156PBbly6h3G4glvMfs2QZyAoD8BXTrCVgGANww+DRATBE5/KIqAtEz/S/o2q4GichZqjdQp5xwcpx1siIsTXdzv6eD+5rM4Jo4ic0J0ewS1SiHCzwlbI2Wpu2RSzf80SERw2NLAmpEZ7V0YnLxoy+XXBOiyhacBgmYBTVp/zab7z9wUSZ2xQW38o9sOXXQvE1IAp0S9DUnldI++zejxLQXxB5i0/3l82pm5GQmWjEf45VAU8DzFM9gJvgRygFWl+tZKw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 26/32] hw/arm/tegra241-cmdqv: Limit queue size based on backend page size Date: Thu, 26 Feb 2026 10:50:50 +0000 Message-ID: <20260226105056.897-27-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC7:EE_|IA0PR12MB8325:EE_ X-MS-Office365-Filtering-Correlation-Id: 623d5f8e-a148-4f8b-7d6f-08de7525467a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: uF/5v+AT/t2Bmjo4aQsEQ0BptsHMkWhFSnqbVzs6edtck0Ysit0Z9W0RUg9iTKy+DYyArR/2umC0gtRyj/UqzVIljCt2imTVaZRuu8xj853jIE5uitx9Csd+yiW6uivO5ioejS6R8ybb1dF7ib0pEFxByeRqzxlqcr+7sUXamvym4S3kJSv45q+2as734cMFhR1eXGSSpwJTwut+TjZ4QBouk+2Xov4K+GgHyK/MfdkFNTYC3+8J0oK7tG+z0BxlyCA1NsHue1VMyDyMWFj2nwVcPFI5vwbbMWxISUzQDSVrqupqZ+18z/kKTdRojackolXQOx5jahFZUudYPdYzhur/xRQn8/w12Weiz5YDHpA3JOZF0bsyc74u9Z8t27FC99+6YF8aHnsCDKOeDrO2KvbCOpvoEW9buL9btX5ouRa96c2/qsYKf7Vi39SU/f+8O8/zt01oSAJ5xRTUPQR3wUTXGzDR6tffz3ZbfXQE3LJvyBTLvgKYYedOi7Fo5h0Tonsu8Y7kYZfBNdw8VETAeCixPFA1Uut0e+372/NaPHqR68k9AFVEESeDd3kGxbOJKwPUsKe1LyLg3EgwYp45SqAtFMb6Wto/AzB0cMQOkEFGttLHOduJoFjt0ir1eHOjtc+58aoJzxgSZGkXSzpqjHVO1Jb9RXGG2/wVivVoomRhb56Ulbnvr7I+RNAgjLI/ULZ1U4hYeGhyPXC4jpcT4S58gj9MvvtSkACe3ZBof+Ed4g3gjL/tHcUAdsb0sIIpEdj5Ks6bfdwlyrDhr+c5wrO4qRIqnSr+uv1ywiBWW5N+GAvJ7UDHtl5ITspaHFaUIKo7MVkG3yXHCq+jgBeVIw== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(7416014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /SfHyAJYPPgd3FpUrZufHMtTE6iXsBKeXKz0PRthMdcdOul/O477oHMZjyfHdE51unEwaTdtSFUlLGpG0Bq23s1q6rfpxs5cIT4Ztv7UgU48bUnb3Bh0Q67LDbSxjRtg6aPwtpt6KC6G8Wr3EhTKrNWvdc265xvr8xXAoBWq+XJdlk8EgusQBEMof6kWWSyIeSB8ly2D7TMBEpOwV+u7EyDBWg9jt6V4PkyQL3UMIAUYT5FE8D8ut+2tAX0nNuZtbw793jI3jUIbekS/aQ7+GbePlJx5rx/V/sPNwWzcZdNTQ49BRi6Y/0sNJvg/Zs2WXUmNGknGRoSx9a63xjiiq70Sb4VPjewzYHa2cSl27OLlb9vsVPhyJuaBwNl4K3M4K81mSz3/++1PwuCrywnGPKIi/mSOtgRIG/vuQrnoXHv7IcBL6U6NL6j/tJGL1sj3 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:28.7244 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 623d5f8e-a148-4f8b-7d6f-08de7525467a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8325 Received-SPF: permerror client-ip=2a01:111:f403:c001::2; envelope-from=skolothumtho@nvidia.com; helo=SJ2PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103405843158500 From: Nicolin Chen CMDQV HW reads guest queue memory in its host physical address setup via IOMUUFD. This requires the guest queue memory isn't only contiguous in guest PA space but also in host PA space. With Tegra241 CMDQV enabled, we must only advertise a CMDQV size that the host can safely back with physically contiguous memory. Allowing a CMDQV larger than the host page size could cause the hardware to DMA across page boundaries leading to faults. Limit IDR1.CMDQS so the guest cannot configure a CMDQV that exceeds the host=E2=80=99s contiguous backing. Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 5afdc5c8a4..a379341c0a 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -11,10 +11,14 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "trace.h" +#include =20 #include "hw/arm/smmuv3.h" #include "hw/core/irq.h" #include "smmuv3-accel.h" +#include "smmuv3-internal.h" +#include "system/ramblock.h" +#include "system/ramlist.h" #include "tegra241-cmdqv.h" =20 static inline uint32_t *tegra241_cmdqv_vintf_ptr(Tegra241CMDQV *cmdqv, @@ -618,9 +622,38 @@ tegra241_cmdqv_alloc_viommu(SMMUv3State *s, HostIOMMUD= eviceIOMMUFD *idev, return true; } =20 +static size_t tegra241_cmdqv_min_ram_pagesize(void) +{ + RAMBlock *rb; + size_t pg, min_pg =3D SIZE_MAX; + + RAMBLOCK_FOREACH(rb) { + MemoryRegion *mr =3D rb->mr; + + /* Only consider real RAM regions */ + if (!mr || !memory_region_is_ram(mr)) { + continue; + } + + /* Skip RAM regions that are not backed by a memory-backend */ + if (!object_dynamic_cast(mr->owner, TYPE_MEMORY_BACKEND)) { + continue; + } + + pg =3D qemu_ram_pagesize(rb); + if (pg && pg < min_pg) { + min_pg =3D pg; + } + } + + return (min_pg =3D=3D SIZE_MAX) ? qemu_real_host_page_size() : min_pg; +} + static void tegra241_cmdqv_init_regs(SMMUv3State *s, Tegra241CMDQV *cmdqv) { int i; + size_t pgsize; + uint32_t val; =20 cmdqv->config =3D V_CONFIG_RESET; cmdqv->param =3D @@ -652,6 +685,16 @@ static void tegra241_cmdqv_init_regs(SMMUv3State *s, T= egra241CMDQV *cmdqv) cmdqv->vcmdq_base[i] =3D 0; cmdqv->vcmdq_cons_indx_base[i] =3D 0; } + + /* + * CMDQ must not cross a physical RAM backend page. Adjust CMDQS so the + * queue fits entirely within the smallest backend page size, ensuring + * the command queue is physically contiguous in host memory. + */ + pgsize =3D tegra241_cmdqv_min_ram_pagesize(); + val =3D FIELD_EX32(s->idr[1], IDR1, CMDQS); + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, MIN(log2(pgsize) - 4,= val)); + return; } =20 --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103436; cv=pass; d=zohomail.com; s=zohoarc; b=JWeMe1LsyYPYNdrlmE3kKQcxsh7CfGI+R97pFfZVVfGLopi6QqwibbHJnodjURbD8VT+My42uXgjSLL5DCzD0HALU73IzKadPJ2ZWTADcA1EFOJDSiSK8WPYjQtic+OwMLOiwDsrAlOS61zsK17hfW1kIsebQrjquZ5KJN342U0= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103436; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bbjzwuQlr3TunnV2CPcAmMDvTbpm0QcjsfrYU1zb37A=; b=Mh+XCdLg6dVoniedV1586xVryjXvRgFNq/HQXy8bNO4COJLJxXbAlZTeJkMnbe1clDeDY8IFz0yzn8vigIGnyu0RrL/fGrl3zrolGWyAGd9/dh/tSRokImP1/KBa64LV5DN+ZQPDDl2zOhM+9Ifnhv4dijT/usUAfSSNUV41W+o= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103436906855.6286102807823; Thu, 26 Feb 2026 02:57:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvZ01-0006yi-E0; Thu, 26 Feb 2026 05:53:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ00-0006yN-87; Thu, 26 Feb 2026 05:53:40 -0500 Received: from mail-eastusazlp17011000f.outbound.protection.outlook.com ([2a01:111:f403:c100::f] helo=BL2PR02CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvYzy-000151-QR; Thu, 26 Feb 2026 05:53:40 -0500 Received: from DS7PR03CA0041.namprd03.prod.outlook.com (2603:10b6:5:3b5::16) by LV9PR12MB9759.namprd12.prod.outlook.com (2603:10b6:408:2ea::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.22; Thu, 26 Feb 2026 10:53:35 +0000 Received: from DM2PEPF00003FC7.namprd04.prod.outlook.com (2603:10b6:5:3b5:cafe::9) by DS7PR03CA0041.outlook.office365.com (2603:10b6:5:3b5::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.22 via Frontend Transport; Thu, 26 Feb 2026 10:53:35 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC7.mail.protection.outlook.com (10.167.23.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:34 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:12 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:09 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=eXtOsGfP5kzLVSLrS6IAKojPCQh43dtHZPW/PPlmj0je86E+hdtMc+0WoGf484GP2Xm2+ouh8kbDtREYx+EXHipicgU8TQz+3m3RY4J4jykkGmWSLgJPGlCi0sStqlRbI3WMpPntqiwipNfxJQHCDEcOIV24eC1GCFg6p7+FiuS04p1wyBJJvjvaZskWXg7c5dyGIxLLb2U4jHXv1Ig7rU6fovqas/5hjGnqtGyjSeKs+4FRSz+ZPmzgNHMRouf2vUOEdTqLHsEgWR0tyHVaItVd9as2CCxY0FjvDKx4yem0ywvaxJS1OW2yt8tZeM4TiY0/WG3EATLSjbz1AcZ7tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bbjzwuQlr3TunnV2CPcAmMDvTbpm0QcjsfrYU1zb37A=; b=FNoMyKRVs4Ke+gTil4beYN1OlFQWoeZPsalrcOPMFfTuPElkbqXPzWUX8awedhqr8nY5InURrIB/fkuIocYc490Gsvf5mlkgR7w3pRmls9k4dED1mEADLU/bIbOj6vU4lMj7c+SmGgvlBk7IYM5skXMRKeDSwxU2qlfafJBgvi4xXzBg4fOX9RStlU7fNf+ZIMcLi/pV6QnzDrMWSwfaShVMpm6POFftNKdS0EacxViKoi0RyDfrtKlrA4N3kqrPX8DnXF4dc+qiNzPcNyhEcrkZppB0Y8b1DWvHOTJkEicrE+eSvGmZcP3NIVjTdyoj1hx1KcQ2f4jcZUnDaVciJA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bbjzwuQlr3TunnV2CPcAmMDvTbpm0QcjsfrYU1zb37A=; b=e7wISq2JSIbu9c3ybSE6HpaIkTlM9Y65CSfAmafZxsX9DN0j5Fd7PGCNylI65yurWuPxDa5KWe8a0NSNNhDHoJaSmSV624CjE+Rw0/gk00qxnXvGV6dbLe3Lx6uO1CZ4wg8pD+b2v3b6veZeL+gkzX3w9S7FYzYY3gpoFv2WNVBjHEWuicgzISYRA8v/DqiUBSGistgPKAEwHFHg/CxWA0eu5+85bj7SRMbojHIeDZ2HnZ0xgILS7kNBSvnQQyk9uB9KbUiYf4p0DoYgngaemnC3axZNec0giFJ7fmS7MZ+CT9H0t6Ebm3u9tQqlXpEpdnpWsTt6AH9lY4xz8fppiw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 27/32] tests/qtest/bios-tables-test: Prepare for IORT SMMUv3 node identifier change Date: Thu, 26 Feb 2026 10:50:51 +0000 Message-ID: <20260226105056.897-28-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC7:EE_|LV9PR12MB9759:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e7e10f1-f4f6-48d0-018c-08de75254a3a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|7416014|1800799024|376014; X-Microsoft-Antispam-Message-Info: A0Tx0VbSp1K9C1xJHR8H5H/l9ScdM8NzLlOAz7qQYv/CWiOuPS0ngmY7MWeSuQBqLVcvVDBwhHlZ7SV4G+/aKByH2oD3unHyRl7VR2Q8UxdywPyuZ8EM7lWVNK2hxRmHhcOH+GQoUBfkfl7C7itMa4X2P05Ps2azY0DqhtF0e2ZNyFUcEleuAoGhc+Qhfy3hSUGCUhITHe3hnYRB+eCMff5L72RXaPZoCpqCEpsbW/K78yRYViidUFKeulxlAlldr6IN6cbCzkfPv7Gs7cH3fDZYwkjS8QOL/HZ0fQQOSF+sKuM9tUSiBTGQVsGowZ/ua2YF93ZUL46AXldLpO45CEluNKnmxtrvxW4Lqox+dmj18y1jvhGceahL8GOBGB7Wijrqlf96alqKyBj9ZcGpJbAHx/W+jy+Fve6jbMy0+Nvz23/yifhiNoXm9GSQZCRz9v+qBeix1iF/uzNvgDJC41cSj8RWy+63apimXcxk6sdzbW1hS+I+x7N3klIJu37QfJjaGH3xG5oV24EI4vk2e+sypXZhNtoeYRxVUdpvsPLt1LmjYGcGuzln/NhGCOLAJdPbrdtfqXf9uC/VFKHiu8JrVoh1lYZyEaCBvAYqE7jmLaNZ/Y7wDrM59DMuiqpPGeUYyM1AmibbFNOM0vgzbleAPyyWa77n/hWStSVWTyJkf8fbuPD2rkMoilm6W5PMOqsC04UwG+6OXO8/x6Kyv+BQOuTjJU1cpC2yDvemWhllsQx8kaGIiPzz8As7gjLoexU0Vly5VvejtqAoakWwqczkzlrEuBFYLZuooS8q/Epx5p9wGrR4NnWAnKIinto9khg6j5DrNL9HX6NbioA7Gw== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(7416014)(1800799024)(376014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: c+zN3WPZUKYhNXLiW1+/tipLKAPRbEknNXlGm913/BkuanZZuUWHk8dL/uxWWKekfQA0uiC1cuTgrxSWXclCKR+jRIq3+z87uXftR07owG6qtanaADGfIO+faPNmaS2vFD8SiY3kSb/aEWvGgo3zwZCK/9elGuhxQsOnZEEHqV4zxb7FvcsujkTKVU9ZcjLVq0FCcK82WH59BWffeWCuW9x0OTI2MjDQwXAob9yFwXogO9EKAAG7KX4Jnp/IeHTalgpVZRvYq+1/kd6TjuRpYfomZtOhuYFQdSovVamlkZQAKjzxYfCoxcsucxJP+pcYtCidfjXclm1QyKXasHRNLm8UvH2rtKI5RxpIA0oB84zSVJtCLDk+gt25TQBGyaWOkIuftnMzHbtli0QX/uVag0UjfBSWDpCeDAErQFZJuSnd8w6BzEZkLEMRGnYn9JBf X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:34.9600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e7e10f1-f4f6-48d0-018c-08de75254a3a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV9PR12MB9759 Received-SPF: permerror client-ip=2a01:111:f403:c100::f; envelope-from=skolothumtho@nvidia.com; helo=BL2PR02CU003.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103456063158500 Content-Type: text/plain; charset="utf-8" The IORT SMMUv3 node Identifier field will be derived from a new per-device "identifier" property instead of relying on enumeration order. Add the affected IORT blobs to allowed-diff list for bios-table tests. Signed-off-by: Shameer Kolothum --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..df5fe417c0 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/IORT.its_off", +"tests/data/acpi/aarch64/virt/IORT.msi_gicv2m", +"tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy", +"tests/data/acpi/aarch64/virt/IORT.smmuv3-dev", --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103386; cv=pass; d=zohomail.com; s=zohoarc; b=JTjqvAND8rmCJScuWHfKnRb9pQMzIerNqOD2ctFisr6K6Zq6QlTM//TZCuI8Hicx1AtjFbC2vpOTXpaHtf6M9OVb/y05hCrOCQBj5meuBnbVFwYYna5+VJO8aJEaCzutHtWc0vfCwR38Qo+I1vVVMlxy/0FU/BZHGn8mj5blbqE= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103386; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AXRl+XfEVLGSXf9AyNCdXjp7dIVPuoCktsrlsKHZbgk=; b=DBsOZJZes8NW/Hwc/IIRBCpmJmk5WTN9zW+e/qfxcwbcDbkoDR9YcsZcAsL9LfH7cgGLo7hJhHRDpDX/tzVZSpnDftC7sXIsYxOfXdQh5K2YXyHWbJzQhBURqeAQoGOflJp41G5EIfO9pRjU2NtnmIMnQDlC7xltW1cGQdgR/Qk= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103386778179.39289757300583; Thu, 26 Feb 2026 02:56:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvZ08-0007Pz-DC; Thu, 26 Feb 2026 05:53:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ06-0007E4-TD; Thu, 26 Feb 2026 05:53:46 -0500 Received: from mail-northcentralusazlp170100001.outbound.protection.outlook.com ([2a01:111:f403:c105::1] helo=CH1PR05CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ05-00015d-B3; Thu, 26 Feb 2026 05:53:46 -0500 Received: from PH8P220CA0003.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:345::27) by DS2PR12MB9822.namprd12.prod.outlook.com (2603:10b6:8:2ba::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.11; Thu, 26 Feb 2026 10:53:38 +0000 Received: from SN1PEPF000397AF.namprd05.prod.outlook.com (2603:10b6:510:345:cafe::f) by PH8P220CA0003.outlook.office365.com (2603:10b6:510:345::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:53:31 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397AF.mail.protection.outlook.com (10.167.248.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:37 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:16 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:12 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=tB3U/RbwYl6Nbo5/E5jkMPXhcLEHH2cetDR+CHYIMAuK34+T9t0DqMqR0v3jQBe8l4H6z7G2XEgAoR6bTXwOLdvByIjO4ZQE40TZkri8m56+sS2bjqtuwKglCHYFCRXIsHCoRA+98nOd5f0vBD14nEzhI0uzEijn6AeUU3UMqj/KU4eE2w0HTxmF/Bc3t64gP/N00SXB+duJS1gSO20y8fbznpdpWdixQCk1iMzShW88HFw6m/LHexGBhHvKMgw8dZw86sLnJAUYlReiXEvZP9NuQV+WhCqB5gfWeh7NPAMXP6T3aT/aSAAG3QvcLdrrQuN0XIsp4Ux8IUNqayXJbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AXRl+XfEVLGSXf9AyNCdXjp7dIVPuoCktsrlsKHZbgk=; b=sDmB721/5Uqc5nfIGmvdnrvUUnK1uO6Fy7uRY6sc5ETgau4ipWauWM858Rld9xBu2cDCdd3ZEdipJ56OYlG/a3Hwo/6FQ7px1z0MRbbodk38nDBH1u+NzNM4rJH6NjO1w/FfkHPcGBTQ4tuELDbYelfAXgpM4MN2ZSZXwIx3bwmCJ/CJCenUOVaTB+smx9LBj9gMvmQVt/kYBW/sQaSUsjiSoXz4Fd6+WMGDxRwHAi4EtVxpQ+Q5Uu/gMiBc1s3uRVXUmEbBHMtiZRZ+Ge+7CxiBM9wcOS9Mmf28+wcbzY1lrhZAJ9oaUIePq+Dn0FaGEJITzfphbcTBWnXTJwwBKA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AXRl+XfEVLGSXf9AyNCdXjp7dIVPuoCktsrlsKHZbgk=; b=U/Zqkiv/mDIQ/CLrhjXnyuA3tQL8Bcpd21WZ8pbC6kodNdTasBjVZQf9MXycPAm2Z3VGGNzZYHJLfznVtPJi6rVdPJjXitG1oUySpxBVWjTeg2Mmm0RoE4vVOhwm1vfJDeY1sqaA6rpeVben5gITTHeclByayoyHgoFhdr1Bagez8jUIIlcvKh5V88jcX6Wgg9DPvGyXCnCpDsQ/sTAe78D+nUSmhcpG/mhQ0jXz7v7WSMFW98F9AU7k2yKtAhnQR3JZoGBM1xaymZEsRmupRTfcESm1lz6PCz0uhCbAxBwK7HkY3MFexBse3BVxCHn1PBkr1++1vS1yhTSGcRrWJw== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 28/32] hw/arm/smmuv3: Add per-device identifier property Date: Thu, 26 Feb 2026 10:50:52 +0000 Message-ID: <20260226105056.897-29-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|DS2PR12MB9822:EE_ X-MS-Office365-Filtering-Correlation-Id: 250e055e-5dc9-497d-528f-08de75254bee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|1800799024|376014|7416014; X-Microsoft-Antispam-Message-Info: i3tt5DOByRExznmwCH/EBA9rkCva47G7Pc7BkVkg/3g6CVAc13/Gjgt4sNoDJWuDVzkDJ1ZAA/sxbub564F9P/6OG3GPMHI5VL5uoHNmrnEGgyj4CyAf+yTsbGam+eawMWjq53HH0aIR2lenEaoaGjIyC/tD9fG6gjBfffiNZzI99AED2cxsPlCNudPRmi2PIEXomrRvr9M3CdzDy98ga/W/xCAMrJIczDhYIXhw8t1JBwA+Og9pf5nGkiQaYCoyWnvcU4P+dyi83Hrog2WsizdQiw1nm3ck9iR/oR2An4VsLuFy3EAZ+LhP8Vg0VhlCPu4yz1kdMkZMo0T7KbbqqCsCFxmdokOEpKQ9BQComkk9Y06YTv75dCfac8sQmRPZjylNTUsUM3ROS6NaDoUQJwL+fLIOiCrh0sAR+XXSQYcaUdUVu7vWNgua747RbbfPkzmxtE6eJwmp9+GENwtOkNtK37PNzP8bETJxl5F1gt5UWpocV1yJ6gtI28p2D8GqCYbZoW047QpD0dmmSar947TwHVfOhjVRPEp7ZQ/qbntlPjzqKi73PZQe5DzoN0peK0hSFCRhGsLmx6K7KgwHJP/z6U24aS8eOKur0fVC35vjl3G/4HsE+GokpYEco7Jbrck3LgyBmWi/CHD6qDQutoTjeyR1q8y3w0o5/3WuZM5g6vPvLtR7zRGbuJ2Ngu8YQSKXZuBkQwV9Ld6erxtyQrtJCYJYvE346XgQQY8V6fR8VCxsB0A7rPWzVmjqP5OxFloyagkG5cbAIex/qdUYZCp5066XxhBu3r4naTuQRD7bu150rd5FQ7PeVW9mtDRZuoMBIoERssyqeVSmhn/xtw== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(7416014); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jPGlsW9rbnluDXgx4GCdPcvItFXW7nk8MIdGMN4kYpfweHTt3qtXPitJ3S/n231G91BWspJe266D12szro7xrJCGaeVtzZRzk/Aen82Aw5Dpi9fwpKwF5/yXuc4g+vP9v3ds7k6XOPmyy6lQedLbMhf0NMdHgCKLCkS6a5Q+0/dFVJNH3LxoGsf9J7hvpcwABvKezfNbf0GdtVARCisf+wftCAc/4ammn9GW8CzG/ccD2XQufYmJOkztKn+IUNDZDZG9tIuJa7B68s8TYV7kR3jeunMIJ/YAZEjc0Ah/iScEqjsjQOvSBE7yfpz/N5xMwq3ywUWRIF8s9C6u2Ad2aZNHaaHCc805FWPh6y6QY3+7BHIdXh+aDS9ZM9X+eAdoWXCSJCqqbXMUCGz1jflRwV6AApkgeI3/HcOHUpUxiKqem35eCTI8BBkCafIoxcxN X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:37.8348 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 250e055e-5dc9-497d-528f-08de75254bee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9822 Received-SPF: permerror client-ip=2a01:111:f403:c105::1; envelope-from=skolothumtho@nvidia.com; helo=CH1PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103387777158500 Content-Type: text/plain; charset="utf-8" Add an "identifier" property to the SMMUv3 device and use it when building the ACPI IORT SMMUv3 node Identifier field. This avoids relying on device enumeration order and provides a stable per-device identifier. A subsequent patch will use the same identifier when generating the DSDT description for Tegra241 CMDQV, ensuring that the IORT and DSDT entries refer to the same SMMUv3 instance. No functional change intended. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- include/hw/arm/smmuv3.h | 1 + hw/arm/smmuv3.c | 2 ++ hw/arm/virt-acpi-build.c | 4 +++- hw/arm/virt.c | 3 +++ 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 648412cafc..73b8f39aaa 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -63,6 +63,7 @@ struct SMMUv3State { qemu_irq irq[4]; QemuMutex mutex; char *stage; + uint8_t identifier; =20 /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 468135bb24..c1f84bedd4 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -2109,6 +2109,8 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + /* Identifier used for ACPI IORT SMMUv3 (and DSDT for CMDQV) generatio= n */ + DEFINE_PROP_UINT8("identifier", SMMUv3State, identifier, 0), DEFINE_PROP_BOOL("accel", SMMUv3State, accel, false), /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index ae78e9b9e0..20605185c5 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -342,6 +342,7 @@ static int iort_idmap_compare(gconstpointer a, gconstpo= inter b) typedef struct AcpiIortSMMUv3Dev { int irq; hwaddr base; + uint8_t id; GArray *rc_smmu_idmaps; /* Offset of the SMMUv3 IORT Node relative to the start of the IORT */ size_t offset; @@ -404,6 +405,7 @@ static int populate_smmuv3_dev(GArray *sdev_blob, VirtM= achineState *vms) &error_abort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort= ); sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); + sdev.id =3D object_property_get_uint(obj, "identifier", &error_abo= rt); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); @@ -630,7 +632,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) (ID_MAPPING_ENTRY_SIZE * smmu_mapping_count); build_append_int_noprefix(table_data, node_size, 2); /* Length */ build_append_int_noprefix(table_data, 4, 1); /* Revision */ - build_append_int_noprefix(table_data, id++, 4); /* Identifier */ + build_append_int_noprefix(table_data, sdev->id, 4); /* Identifier = */ /* Number of ID mappings */ build_append_int_noprefix(table_data, smmu_mapping_count, 4); /* Reference to ID Array */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c75a8d6e9e..44c6b99c96 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3138,6 +3138,7 @@ static void virt_memory_plug(HotplugHandler *hotplug_= dev, } } =20 +static uint8_t smmuv3_dev_id; static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { @@ -3196,6 +3197,8 @@ static void virt_machine_device_pre_plug_cb(HotplugHa= ndler *hotplug_dev, OBJECT(vms->sysmem), NULL); object_property_set_link(OBJECT(dev), "secure-memory", OBJECT(vms->secure_sysmem), NULL); + object_property_set_uint(OBJECT(dev), "identifier", smmuv3_dev= _id++, + NULL); } if (object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { hwaddr db_start =3D 0; --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103250; cv=pass; d=zohomail.com; s=zohoarc; b=EwmkO09f6L6ZHCarYp99ZNHREpWrbaui5nFH9amr80U2GTIiaGR855FstujZDIAlzucOQHYKMvPorH08C72SlwU1p+Gm08tgj1/KaHJNP4+KJ8QqhentkxaI5RbU/urMnl22Je4T0Bfxi1uI4hAWhQPHeRBQc0y3kyOCUH3cn84= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103250; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZPO3285NFZW58Qfr2Ufe7ruqPU+jqaG8EJNayzxmPpg=; b=jzFmX3V4gN+s7uoYN252R9nFYkmADK552OFmcTtf2JXno3duY5vhFgCWZUu8cQ9DpU7IL9zvH/qfW8DYLVAZW8zl7dtgx+azCt5mwTy4CcyepIPUSf8ubSfjNKMHz8NLFjrTPeSX4I6yZD0QzNFX6bUjhDV6fvIDh0bR8Bdm0V4= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103250644171.4803813092965; Thu, 26 Feb 2026 02:54:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvZ0B-0007au-N5; Thu, 26 Feb 2026 05:53:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ0A-0007a5-H6; Thu, 26 Feb 2026 05:53:50 -0500 Received: from mail-westus2azlp170120002.outbound.protection.outlook.com ([2a01:111:f403:c007::2] helo=MW6PR02CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ08-00015y-Ts; Thu, 26 Feb 2026 05:53:50 -0500 Received: from DS7PR03CA0041.namprd03.prod.outlook.com (2603:10b6:5:3b5::16) by DS0PR12MB7771.namprd12.prod.outlook.com (2603:10b6:8:138::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:53:42 +0000 Received: from DM2PEPF00003FC7.namprd04.prod.outlook.com (2603:10b6:5:3b5:cafe::cd) by DS7PR03CA0041.outlook.office365.com (2603:10b6:5:3b5::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.22 via Frontend Transport; Thu, 26 Feb 2026 10:53:42 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC7.mail.protection.outlook.com (10.167.23.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:42 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:20 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:16 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oO8Qhf45hoKM8O+d/nRlMEhNp2O+OOFSTT4WfV0xPv3k24XShtEbhyFS+Hau69qMbHM9qvTcFj0mfQXUmr0yDFTndrSZeYw/C1BdusJludc9fWnt1ZbeEWFzqRS5QPAuMdM+ga1nie/eBnwwRxUE8xk445XWe9arHjcUI5WNiiNSSqDrA7h9ncy0nYrVQB3J8g8SvaPmMhp+t+L8Tzlg+dW296asSuDDb4lneJwzL5eEO8821syHhBPaKDMHnaMOpPYEhLTpDWKKMxF8ojo3ayI+x3Ir8hTHItk6vvcTKT+4NOYitcMQZlCStcjVDDK21PL/IQx9A0+2UXimTgo5xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZPO3285NFZW58Qfr2Ufe7ruqPU+jqaG8EJNayzxmPpg=; b=fifVfLXDW7BQO4bwD9xGt9LE5GTsBqpMxA6Q8a32rBwQ4+Im9t+gPx9nBXlL/W0TS3bwH1QwTXGyFCVNyL8S7QzMKqw70nDmwMjOXMu30wHOcYTffWNVqXJFq040nx3IW+yM6wzc8SS9PxwnAWr1X2a7W1NLOi9tqeU9VROP6jT0mBLp6GuEVgqCI/PSYtrUC88LF6eUxP0L1g+E65J076/AjDx5x/TQ6CAnZCGI8Z9TwBFvOPVxP8QA7vjdcT5NH2ROEGdIL3UeTMRXG6Qc+LtxbqX4RAnaUJ440gU1BC7xYyICG9VozsnJzdBgRLxKrAXvqdir3shN15r3fN/AJg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZPO3285NFZW58Qfr2Ufe7ruqPU+jqaG8EJNayzxmPpg=; b=jF7dLSZB8uPTgjqvPp+1Uy2ABQc7Lm4b10Pwv1pEVSCrAw3ZOn9dX7wTqJqHjLxgfgTdN09NM3ZrC6SNoXWQUnnh+aNpIhjzAnR8f3jk7cu5m1BmOx5EZCLUO7jwcRDhIVB5EBhXteLWsMA9SLNXQRjYz+6e4z4ul9gzmr4NkuSmdyrJJhMvtjLIQSLL9QgqcEu61hVRoaqYBvOmELVAciGqSqbYHFlf1YhcsvFixWj73I0TVRIiVB0QXIbBvag/hFgstXZw02cFrrCCsEtFh4+WfiN2seC0/C67LFF2Ri2QItpdaXv4ux03aFWjKgFKuUt8B085C/BWXXHMABp3Ag== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 29/32] tests/qtest/bios-tables-test: Update IORT blobs for SMMUv3 identifier change Date: Thu, 26 Feb 2026 10:50:53 +0000 Message-ID: <20260226105056.897-30-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC7:EE_|DS0PR12MB7771:EE_ X-MS-Office365-Filtering-Correlation-Id: b37a069d-264e-498e-85b0-08de75254e7e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: ES4n1Msm4eFRsYbBMhWZlHbv2HpMPwh1rQvsRxi5chSqrFxCzVIVcCWQiyqi7kncFKR9TFrQqwgT7YGu9TmmXYmwULvxV7RkF7gCyO/dBiIaM6cVOd5MZO6AVQX58MjR5nf9RJi2YbCw9ar4EQvN3DN5YOMKuz05w1ZSaDNjrWJ20Pj8vQjMChMToIYHSFJacCgkr0extc4Q7BYQwuhCpsnhj+zlnBq3lhsJNEE/YCWvaq7Vq3/LRGvilrYimk1lh6dzU7FsrL/9bCyjVJ40gnQclJKRSY9TvvTR/HkIPJZCeRif9dywKvGAFC9uM+mo+2VSxvvl1Xbh5ohui/KRrVlejTP8/S0NtVdY9aobZJ2jvaJqu3ZkOl5R/bLrg4MDIvjtKai+K3j8CzYEXzThVZMstOCvwAJlAn8/931Yz0V3eTnkfcpwUVWxlWmsjwBS94MdLcbegVgI9zsAbNw3wHrbVLWttf6BGE69iSwm3gl7aC8GHq0cI57ZUM1iOmKeWZA0jKBPBRFDMF6HuSfCHpUQ0SSg81hh5jrCrM/V2VPWSE9pz947SyFHew1Gdt59SKWHEdJgYLUNCjpj49aQ2StkDH6fHF/lUijo2Ya3JzTZ8vPB+OyjeS6lmh2xOg0wHdrrmBce9yt58S3GjGAP+E3JdxxswHdEKToGUtC7w2MDAavvGrrOnOtR4lNGLjEIDJLkamx00aS9RanL7fJXF/FP9ONM/QyCi6Qi1DCl0IB5o0DpJD2cCw7Xybmcy4agOLLPElExUrjvTOSSMSNFPsEPUw/+Mq6epuSLVp1zjH+7Ba4pNBatj503tkvouacVDREkuGeDyc9ymm9EURHWPg== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: by4TODZtJvu5C+Mj5r5d4tN2P8bqt0LSNJGEx0bf5Rm1t5Pl+jUHTL54JVNYuBDfF7NWHuc1hk0o+/ZL2u0nbXdimSwebsqxT6sEKNOf32Ddb1SqjtWcpeR5GdzVpepsb0ejRwRh8bOQQgOyvf/N0rzV5eHezwt/1zUpv8Lvk5oVbDqkJM5D5scYE6+08QRoD2/aSKakoFBp1XKE0zG3XPNZBMSVma9Jsj/HyJYH0t274/Jeauv1xzufQWR3VAOFUDfYPNSkVVxFMGrUamk1OVo5e62BaWDtcAdcFUyXMFn7cB9puKU6e2UuUbDjKyjxc2Bxj9x05tVXVIPihsPLDibosb0r45e6HhgTWB5YaABaAdDXUdJVjm4E5GKKO4pVxLqwONsP1ppMwezbscrFTuDkc7s3S01Nt66lVf7agunfhEViJbP/M9n1DCnsnY1Y X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:42.1019 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b37a069d-264e-498e-85b0-08de75254e7e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7771 Received-SPF: permerror client-ip=2a01:111:f403:c007::2; envelope-from=skolothumtho@nvidia.com; helo=MW6PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103275588158500 Content-Type: text/plain; charset="utf-8" Update the reference IORT blobs after identifier change for SMMUv3 nodes. This affects the aarch64 'virt' IORT tests. IORT diff is the identifier change in SMMUv3 nodes: /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20230628 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * - * Disassembly of tests/data/acpi/aarch64/virt/IORT.its_off, Wed Feb 25 16= :36:44 2026 + * Disassembly of /tmp/aml-KVO1K3, Wed Feb 25 16:36:44 2026 * * ACPI Data Table [IORT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (i= n hex) */ [000h 0000 004h] Signature : "IORT" [IO Remapping Tab= le] [004h 0004 004h] Table Length : 000000AC [008h 0008 001h] Revision : 05 -[009h 0009 001h] Checksum : 95 +[009h 0009 001h] Checksum : 96 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 004h] Node Count : 00000002 [028h 0040 004h] Node Offset : 00000030 [02Ch 0044 004h] Reserved : 00000000 ... [074h 0116 001h] Type : 02 [075h 0117 002h] Length : 0038 [077h 0119 001h] Revision : 03 -[078h 0120 004h] Identifier : 00000001 +[078h 0120 004h] Identifier : 00000000 [07Ch 0124 004h] Mapping Count : 00000001 [080h 0128 004h] Mapping Offset : 00000024 [084h 0132 008h] Memory Properties : [IORT Memory Access Propert= ies] [084h 0132 004h] Cache Coherency : 00000001 [088h 0136 001h] Hints (decoded below) : 00 Transient : 0 Write Allocate : 0 Read Allocate : 0 Override : 0 [089h 0137 002h] Reserved : 0000 [08Bh 0139 001h] Memory Flags (decoded below) : 03 Coherency : 1 Device Attribute : 1 [08Ch 0140 004h] ATS Attribute : 00000000 [090h 0144 004h] PCI Segment Number : 00000000 [094h 0148 001h] Memory Size Limit : 40 [095h 0149 002h] PASID Capabilities : 0000 [097h 0151 001h] Reserved : 00 [098h 0152 004h] Input base : 00000000 [09Ch 0156 004h] ID Count : 000000FF [0wA0h 0160 004h] Output Base : 00000000 [0A4h 0164 004h] Output Reference : 00000030 [0A8h 0168 004h] Flags (decoded below) : 00000000 Single Mapping : 0 ... Signed-off-by: Shameer Kolothum --- tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- tests/data/acpi/aarch64/virt/IORT.its_off | Bin 172 -> 172 bytes tests/data/acpi/aarch64/virt/IORT.msi_gicv2m | Bin 172 -> 172 bytes tests/data/acpi/aarch64/virt/IORT.smmuv3-dev | Bin 260 -> 260 bytes tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy | Bin 192 -> 192 bytes 5 files changed, 4 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index df5fe417c0..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,5 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/IORT.its_off", -"tests/data/acpi/aarch64/virt/IORT.msi_gicv2m", -"tests/data/acpi/aarch64/virt/IORT.smmuv3-legacy", -"tests/data/acpi/aarch64/virt/IORT.smmuv3-dev", diff --git a/tests/data/acpi/aarch64/virt/IORT.its_off b/tests/data/acpi/aa= rch64/virt/IORT.its_off index 0cf52b52f671637bf4dbc9e0fc80c3c73d0b01d3..295dc381063fa4c415a933c5c69= 0ca0fc8ffd6dc 100644 GIT binary patch delta 23 ecmZ3(xQ3C-(?2L=3D4FdxM>$Hhnd5jDbD~$n68wN1| delta 23 ecmZ3(xQ3C-(?2L=3D4FdxM>(q%{d5nw`D~$n676vf@ diff --git a/tests/data/acpi/aarch64/virt/IORT.msi_gicv2m b/tests/data/acpi= /aarch64/virt/IORT.msi_gicv2m index 0cf52b52f671637bf4dbc9e0fc80c3c73d0b01d3..295dc381063fa4c415a933c5c69= 0ca0fc8ffd6dc 100644 GIT binary patch delta 23 ecmZ3(xQ3C-(?2L=3D4FdxM>$Hhnd5jDbD~$n68wN1| delta 23 ecmZ3(xQ3C-(?2L=3D4FdxM>(q%{d5nw`D~$n676vf@ diff --git a/tests/data/acpi/aarch64/virt/IORT.smmuv3-dev b/tests/data/acpi= /aarch64/virt/IORT.smmuv3-dev index 60cfed1361976ef26b280c11ba2e233f1cfd9383..12f3e0f01864acf24fc86d4cde2= de561aa92f878 100644 GIT binary patch delta 23 ecmZo+YGLB?^bZPQVPs%n^`6MJiIHLAUUvXH(*=3DzH delta 23 ecmZo+YGLB?^bZPQVPs%n^_ (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103424421547.5004111023493; Thu, 26 Feb 2026 02:57:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvZ0G-0007mS-KF; Thu, 26 Feb 2026 05:53:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ0F-0007gY-2R; Thu, 26 Feb 2026 05:53:55 -0500 Received: from mail-westus3azlp170120001.outbound.protection.outlook.com ([2a01:111:f403:c107::1] helo=PH8PR06CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ0D-00016V-IH; Thu, 26 Feb 2026 05:53:54 -0500 Received: from SN1PR12CA0065.namprd12.prod.outlook.com (2603:10b6:802:20::36) by PH0PR12MB8173.namprd12.prod.outlook.com (2603:10b6:510:296::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.16; Thu, 26 Feb 2026 10:53:48 +0000 Received: from SN1PEPF000397B1.namprd05.prod.outlook.com (2603:10b6:802:20:cafe::c8) by SN1PR12CA0065.outlook.office365.com (2603:10b6:802:20::36) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.24 via Frontend Transport; Thu, 26 Feb 2026 10:53:52 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B1.mail.protection.outlook.com (10.167.248.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:47 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:24 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:20 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=C+ggAhyjtW0KTsv8DaZMjhfeC8IAtO5j4lzN2u8vpkkGoT8QjER9gPbGa4dkphjpkKCs2PllD4dB9LsCiKTGNfUjGjy9cqvyDiJAA9FgYfwRE45qa371F7rdM2zLPE+Zgtyx2eQBFv/bjsypxpbA6sLTSSNtHanCVY3gTW823LrkxLEzzEiEUXFjjtx1/y7hWjDbKbfCgdKUGySgrAMcWuuoEC0c9KpPQd5yjygLfThVyeJ4svJJUBTS8EOnQLGhJKp7rgNgX7SxmEgViw6gGsXBZmwORQPnUzdbyS1TSHCPodlAmKFoct08W+mrfTW3xtY6s31X8AqT+cTLG0VmHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hamSleTIM41lOBwZx562HF/+XNgbHUgVmAYDhcA1vM8=; b=PBDEcQesD/8Q7bZRUCuniljcDvBJ2bBhDEtaFN/JAaF6IJjy938VAZCsDaECYc6DEj87WRi2yv9Fy9bJOLiwGFt0ZJD3JNw+Wm3IUKL5UnOmeoO4+Jp4/Hy0EmPmCCpCwNFnTg9KRD2vlJuf7shsv5wZfcRcxc+ZeZCI3exxAA3upDxdN7YYEV+4zNtXZyNeFm/PpNC/esx/RD7YDQcGmGtHf5G6k2+gbFdTQgP0dJlCE/9f026J4Q8TsjDm7RYvVhVrKXD43tKZVPLuG1lhLXHA+1ovRoUkGKGqGx15qiZZyE8cEgZoVGh81BpqHlOy+Tac9OQXSanbc6OZ3eVylA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hamSleTIM41lOBwZx562HF/+XNgbHUgVmAYDhcA1vM8=; b=l5fYlXNamnIdjXOTP61U04WUmamSYZflal8zanNIyu4AgVQ0GogBGjwwMJJg59RfglDRKzTSb+at3qO6gGkXRQ4IAQHSOsV3oHDgBv2T0S9acD36m3UfCdGHijuGGaQdotPaHN+CP+Fj+KPuVySbsLh9IQsDfcvcgJ8ksMcWLHcH9HpF60tIWGtlJZkuZs+yvxMz4hKCPv5ioIF5UV9alcmTAqKRrKfJ4/hPAKfnDRSiyD3ouK+LKYXTNjyBaezVjqwDzb1ddXbwT1NphEgNm4rtLGEDRIehy58AinP0fs21qka178PQNkVDrB7FEpzp1VDi+te0JdLidcGHGPR7QA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 30/32] hw/arm/smmuv3-accel: Introduce helper to query CMDQV type Date: Thu, 26 Feb 2026 10:50:54 +0000 Message-ID: <20260226105056.897-31-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|PH0PR12MB8173:EE_ X-MS-Office365-Filtering-Correlation-Id: 0088907a-bfaf-4bd3-933d-08de752551c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: CFoeFdVw0kFFRKTYPdBwb5bW5yr9Jfa1FAxDEgsfS0ktSwz4jYu1X1Ern3jNhIhYvgsIRiSNWrEww3L+wnzCWyURlE/Hx8t4A//uGiffZO7K3J6hQ04S6vSTG98wm6BaXk8V6Xfhl+nHbCnJ/kU65Nv2k2rWedqRWcQgBryIUWiGr1MrfZTnUZp1SAWG44I5UBoIAuT64x6CTm6WcOQRgTaphP6eKiy5ORiSh1KE6Nh/nrWdDdGQUJPWcaEdI4rHjFQ7n3elnccHQelbJfXNnUhCnOqrwiY8sj0VelDRN+zEn9+Q67g5Xmdb7/KMO8Dal44vWoGvXFX9KsV2N6m6Cn79Qmj6Z95ZlxB1ErLDx1TTFtMX92t+phH5ql/LJ0yV82lrYgnxJ4cp3d20vqQIbkPWPfyw7cM7vRudNuVyBzSAhVUqBSQAds910gicnQ2oJ3Io2DNNXx6c09w21iq6jbJeqiwjNt2QLyr/s5LgjeG6t0C+j4LdZGgZiv5VvrJQ+fr8eiOwbPGbm176YDQVp0sDrWv+k4bdPZs1R7Tnw2f3ySejNRtJDIIUmVvxWrTS+d6t75o5iem3VIIY+iVLEnXUoxMseSlq7Cza30CEYHiOmzaIOHYbF90JIVW72cC87na7p85C3XLlPJu8JEoLmBd8ETEVBqETF05+6ZPzufr1AZUNQxMmotdAV4hDMHunOX7nhVZFLyRK77z9iDFaokKZCESkKcnTjSTm3U7lcSilhhgXS13bPWFu3LCfgos5HmP95TTBvVl32GtCMfnQ/vMStwvPwn74JhJ97WTz5TvohLYf8jMcWh2VnOcRh3U0rs8oEQ5NGhj3939LSP4QKw== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(1800799024)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RTGm9rcoIf270eAdz/DDpoGf1lx9jU//+sVV/b/rHrHC6rP5mnCwVHDzu7jnnv/DNYaunVmtPe5Bi2ikdsuRzNE89gd7fIMyuOwDBQdvZzhurgIeZIMQ1nnsTfGT2xtEjppji2clQmi5EFK6griG9EozU7MbgZP6/b/Lp6JS4vfX0LALul2s5cEhZIWyddEbeeBQRBiyLJp4Ph4vF2pN/wXLgy+OtVe5qi1fQxcEAcJeJ3VlQTwMraBZz/oha9zM8rCvyBhhuR8quFY+jtdeAF8bHULXso3XHF6UlBoOhUYoIrajRuAmI82pahgPosr/6MnAny+b/4wG340R8nFbb9Nbfy4EE3IME/rVtxg0Apvmy+e9BekGpSxDqQuotoGo2gbpWLggWcntcK3U6uuznytoip0qohUZEfHY7pQVeiRNeIhfnjO8bXFRUo18oVkZ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:47.5040 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0088907a-bfaf-4bd3-933d-08de752551c7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8173 Received-SPF: permerror client-ip=2a01:111:f403:c107::1; envelope-from=skolothumtho@nvidia.com; helo=PH8PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103425976158500 Content-Type: text/plain; charset="utf-8" Introduce a SMMUv3AccelCmdqvType enum and a helper to query the CMDQV implementation type associated with an accelerated SMMUv3 instance. A subsequent patch will use this helper when generating the Tegra241 CMDQV DSDT. Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3-accel.h | 7 +++++++ hw/arm/smmuv3-accel-stubs.c | 5 +++++ hw/arm/smmuv3-accel.c | 12 ++++++++++++ hw/arm/tegra241-cmdqv.c | 6 ++++++ 4 files changed, 30 insertions(+) diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h index c349981e79..6d21788006 100644 --- a/hw/arm/smmuv3-accel.h +++ b/hw/arm/smmuv3-accel.h @@ -15,6 +15,11 @@ #include #endif =20 +typedef enum SMMUv3AccelCmdqvType { + SMMUV3_CMDQV_NONE =3D 0, + SMMUV3_CMDQV_TEGRA241, +} SMMUv3AccelCmdqvType; + /* * CMDQ-Virtualization (CMDQV) hardware support, extends the SMMUv3 to * support multiple VCMDQs with virtualization capabilities. @@ -30,6 +35,7 @@ typedef struct SMMUv3AccelCmdqvOps { void (*free_viommu)(SMMUv3State *s); bool (*alloc_veventq)(SMMUv3State *s, Error **errp); void (*free_veventq)(SMMUv3State *s); + SMMUv3AccelCmdqvType (*get_type)(void); void (*reset)(SMMUv3State *s); } SMMUv3AccelCmdqvOps; =20 @@ -73,5 +79,6 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **e= rrp); bool smmuv3_accel_event_read_validate(IOMMUFDVeventq *veventq, uint32_t ty= pe, void *buf, size_t size, Error **errp= ); void smmuv3_accel_reset(SMMUv3State *s); +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj); =20 #endif /* HW_ARM_SMMUV3_ACCEL_H */ diff --git a/hw/arm/smmuv3-accel-stubs.c b/hw/arm/smmuv3-accel-stubs.c index 1d5d3bb10c..5ca94d605f 100644 --- a/hw/arm/smmuv3-accel-stubs.c +++ b/hw/arm/smmuv3-accel-stubs.c @@ -55,3 +55,8 @@ void smmuv3_accel_idr_override(SMMUv3State *s) void smmuv3_accel_reset(SMMUv3State *s) { } + +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj) +{ + return SMMUV3_CMDQV_NONE; +} diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 9a570b8af9..585b460943 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -998,6 +998,18 @@ static void smmuv3_accel_as_init(SMMUv3State *s) address_space_init(shared_as_sysmem, &root, "smmuv3-accel-as-sysmem"); } =20 +SMMUv3AccelCmdqvType smmuv3_accel_cmdqv_type(Object *obj) +{ + SMMUv3State *s =3D ARM_SMMUV3(obj); + SMMUv3AccelState *accel =3D s->s_accel; + + if (!accel || !accel->cmdqv_ops || !accel->cmdqv_ops->get_type) { + return SMMUV3_CMDQV_NONE; + } + + return accel->cmdqv_ops->get_type(); +} + bool smmuv3_accel_init(SMMUv3State *s, Error **errp) { SMMUState *bs =3D ARM_SMMU(s); diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index a379341c0a..42d7dbfde7 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -736,6 +736,11 @@ static bool tegra241_cmdqv_init(SMMUv3State *s, Error = **errp) return true; } =20 +static SMMUv3AccelCmdqvType tegra241_cmdqv_get_type(void) +{ + return SMMUV3_CMDQV_TEGRA241; +}; + static bool tegra241_cmdqv_probe(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *i= dev, Error **errp) { @@ -778,6 +783,7 @@ static const SMMUv3AccelCmdqvOps tegra241_cmdqv_ops =3D= { .free_viommu =3D tegra241_cmdqv_free_viommu, .alloc_veventq =3D tegra241_cmdqv_alloc_veventq, .free_veventq =3D tegra241_cmdqv_free_veventq, + .get_type =3D tegra241_cmdqv_get_type, .reset =3D tegra241_cmdqv_reset, }; =20 --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103462; cv=pass; d=zohomail.com; s=zohoarc; b=GW2cTNU2XcFzrTRNi0udoi//s355q6U3JjRcDeszy5ULOa5g/Y3h0TthdMQds7ScaKjU3U7m3Jjh8E+2wB+sQHh3Yp/Z4eXullh4UqkSXkdquqKDd/O/iJ1Woo+NQ8kpkuxryL3sRknf9eurn6l6+HCpeIhm16h9zYXIZErnbP8= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103462; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YxoSTmn0IdwEHqvVNyPghOQkMLMIdfnmmlyncbAej8Y=; b=Mzcou1GJUJurvphDBFgDEt+Wr4J5skB4+ncmvfBHiCZxQBPHvmcANFWw0Wv+yRjUhd60CWgT5snuH87/fFnOojn99r5ZX4t5S6/m1QwX+ln5/CG2zU214GQlPvq9QzmmtJd7WK7v+62H/GGkVxPJV6iDyAns/UUEzxpWy3wZjuQ= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103462229829.0574639992175; Thu, 26 Feb 2026 02:57:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvZ0N-00080j-Bn; Thu, 26 Feb 2026 05:54:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ0L-00080F-Lg; Thu, 26 Feb 2026 05:54:01 -0500 Received: from mail-southcentralusazlp170110003.outbound.protection.outlook.com ([2a01:111:f403:c10d::3] helo=SN4PR0501CU005.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ0K-00017I-19; Thu, 26 Feb 2026 05:54:01 -0500 Received: from DM5PR07CA0083.namprd07.prod.outlook.com (2603:10b6:4:ad::48) by SJ2PR12MB7821.namprd12.prod.outlook.com (2603:10b6:a03:4d2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.22; Thu, 26 Feb 2026 10:53:52 +0000 Received: from DM2PEPF00003FC4.namprd04.prod.outlook.com (2603:10b6:4:ad:cafe::70) by DM5PR07CA0083.outlook.office365.com (2603:10b6:4:ad::48) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.26 via Frontend Transport; Thu, 26 Feb 2026 10:53:52 +0000 Received: from mail.nvidia.com (216.228.117.160) by DM2PEPF00003FC4.mail.protection.outlook.com (10.167.23.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:51 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:28 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:24 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=LdmF9DaFZi1/ZqV0epWl8gD+6BFFxyCkhxrPF9lNYZBB3JRCwbMwlV79RpTyGE/hH7+loARSMNGKjbBUwFvfRDeSu4izN2uPU+QAwOAGVjZrLFGIfOnNbMZHUIZlskj7tg7/CWy8DwvAAt+LD5F4zW2TytIVU06/E+G5zHeBMcIAowq2CCCcHPC3fJxE+/MV8TkIwdlqd5Brm9mHiAhz10kKIIrS/fDcbaG6zxL1MijTvdz98JL8/YLe38fXgP1U65L41RAZxJQWeEibJO2OLG/xZ4lHIFCkZ+fmDB56q9UCk6/y1yrzJUh0mYc/G4VL52gVxB9sry/DuaRTBAZIag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YxoSTmn0IdwEHqvVNyPghOQkMLMIdfnmmlyncbAej8Y=; b=dCZiOVbgDxPtYT/3DwTjOV6HfGJEkLwgUqXQMUDGk4nsnrwIfKTtlzeVPNSO71bOsPDnC/5N+TS+cQsSDrUNQ7aSgozFyygvASfKm8Sa8k9uUyMXnxtLd1GOcKRjcxpGifgdpXBkAgq0NTIoY9O+d4JAoUOVlnjGqErjtXeREuFCBnj3AXxrBewSIGzLSeuB7DV48QjQa7ZJo21/9p88fXXGI4b+X7bLHd8ZAhT/Z5X4prApQsX8Fe8DfbFrssCGeO8JKxozpRPtx654dEQNwwcwJQPSQ/ZtKPTwe2nQEmYe62/yKjmxcW0B/EOKzEhjJ8oKineBj5cgsU9wdvbpHQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YxoSTmn0IdwEHqvVNyPghOQkMLMIdfnmmlyncbAej8Y=; b=kZoqG6gjfxc6/SAx9G/AfMpzW86FBYYmXpn/5XxV1iSmcxkB/niInecP78/tFtsfFbwHaUa/Z50JYGWTfkVr1vfsoh7dJIvN/O+9U5L+NFLVh+snEdknioLSlUPgeTvqI35uBgxocT021Ag2cL1+11TybNirwtsucDTpw/FHspvg8BGYFwUk7ALCIFbqXEHy+jg+TGj+lyYxbMrdsQws9u2hNzqBxvJY7Yz8l6TKvNlXtW4yq+WPBDbdrDKRItUzg+g8/Anwub3y6anV0qaHkh5rwHHdYSeqj8TGK9px8YKqRpNdr1u8XzMWvPIegJUTePH0i2xO7y0QDjGtgFpdtA== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 31/32] hw/arm/virt-acpi: Advertise Tegra241 CMDQV nodes in DSDT Date: Thu, 26 Feb 2026 10:50:55 +0000 Message-ID: <20260226105056.897-32-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC4:EE_|SJ2PR12MB7821:EE_ X-MS-Office365-Filtering-Correlation-Id: 9c074a3d-e00a-4a49-fc2b-08de75255433 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: vqgCBiG/lhy6Wdzt4U3VBa0KLy2dY4CCa5crUJiM5yBX8HxYVz8mzt2lgWyzHtsIzGItK3d8paVw8AVHBI+dlDmVhQrP5blXuS0Hb4Beag5m33ne1LMAdK+IkFS/vYfPAJ/NE2DprBYMS2r0qtZalG/jlQkl/5FeyWiOBzjqlZiz/LHFr5+cJAfxQ8TxKG8GGuu9vocePPcM1XrzIHv4vdmy46bNi6tCaFDm3c9S5S+LHbO577OKDIH8PKVMKG36A+xgacMr6E8dVtvGJQn26oMqvWZJgZrSXsGveEcLbnBYaAEnhJ6Ys43UFhEIevh4VCvO+sUYW6D5l5jpHkDmw/DdUNVW2AvHQl0C9luXLMs/W29MECeSXNNWIbsXuB880uPAFpRA22vZYiamJbOhILJgPMETRv8LVMXWZalHCB0sNJkP2WQPEjnovO/Hgc3Xs00++IdOnzwkG7ENH32v3pC8YdCBxDduI1FdMzAqU25BL4lifLTNdh+zLBXd7X73m7YwDOe65h/99JxsTMUPn9IhJSh1DczO+eK7i4rgs6SW+Ryr4Bcl6N5iMmt7sRsp6ySV4jr5BG3NCghgtC0aDvAogCWPCLrfa7zgQBPzkcp/nw3lEM4onhAP5bppVHHCdYYGorsGd7TwYjItWjBtP3wP4TW+aG5TWjJEri4XrJh7klR3SBjNW7Cl5fY07IabLmTeN1fjCRgKKIvq3P1Dzm9uaabGfZHjEpzWa9dYUbo385+geq5PaZnkxA6WSvPyxpDhrHHj4pMBb0HXA51Y/gxmSUZX6vKnsWNhC/c3AGqbkST/1eQRyczAOaLp+vEwxGZTtuk6XZmpze1H7q5O9w== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0QNbrugAT1e0FQqkY2k2uPaCRUNH0T5WPLwAHlzdG9zp1iS2zVSMf/Jy+QiIAs1Fb2SuPyHtdQNLjgJ40gEzr8G1OSCVVCRji3SrzVzCCYWrB4JnCIj7JpV3crgFdLtYi0W5OzzgzE5BUB3qjX4S9vHvjqHO9TJxA55SUcNh6wDdlztWN7EkkumLhbl6gwsg440cUkVdhOpxpf6GUo6eBVLsWzBnrmTACO5ABdYnSBrRzbGLDYkYIR7Rrwl/t+JEMF9haAVDDaOO1y1If0nukMSknlS+ye25JiIHbzbimEIuT8UABxQUX2dXSY4VsOrVlMVibfL0CeOG1nvvk4+umz4Ctikqn5sXpbq8M82JujwLQfru7ugicy5jK+2Ybn2wHi8n1LMXnF9pBwd8wVdYLpXeCGAbIutaxhHdxpKbSui6adz0dQNtHzj0VbNSPU0J X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:51.6860 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c074a3d-e00a-4a49-fc2b-08de75255433 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7821 Received-SPF: permerror client-ip=2a01:111:f403:c10d::3; envelope-from=skolothumtho@nvidia.com; helo=SN4PR0501CU005.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103464209158501 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen Add ACPI DSDT support for Tegra241 CMDQV when the SMMUv3 instance is created with tegra241-cmdqv. The SMMUv3 device identifier is used as the ACPI _UID. This matches the Identifier field of the corresponding SMMUv3 IORT node, allowing the CMDQV DSDT device to be correctly associated with its SMMU. Because virt-acpi-build.c now includes CONFIG_DEVICES via the Tegra241 CMDQV header, the Meson file entry is updated to build it as part of arm_ss instead of arm_common_ss Signed-off-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/virt-acpi-build.c | 52 ++++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 1 + 2 files changed, 53 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 20605185c5..462faa6a2b 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -65,6 +65,9 @@ #include "target/arm/cpu.h" #include "target/arm/multiprocessing.h" =20 +#include "smmuv3-accel.h" +#include "tegra241-cmdqv.h" + #define ARM_SPI_BASE 32 =20 #define ACPI_BUILD_TABLE_SIZE 0x20000 @@ -1113,6 +1116,51 @@ static void build_fadt_rev6(GArray *table_data, BIOS= Linker *linker, build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id); } =20 +static void acpi_dsdt_add_tegra241_cmdqv(Aml *scope, VirtMachineState *vms) +{ + for (int i =3D 0; i < vms->smmuv3_devices->len; i++) { + Object *obj =3D OBJECT(g_ptr_array_index(vms->smmuv3_devices, i)); + PlatformBusDevice *pbus; + Aml *dev, *crs, *addr; + SysBusDevice *sbdev; + hwaddr base; + uint32_t id; + int irq; + + if (smmuv3_accel_cmdqv_type(obj) !=3D SMMUV3_CMDQV_TEGRA241) { + continue; + } + id =3D object_property_get_uint(obj, "identifier", &error_abort); + pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); + sbdev =3D SYS_BUS_DEVICE(obj); + base =3D platform_bus_get_mmio_addr(pbus, sbdev, 1); + base +=3D vms->memmap[VIRT_PLATFORM_BUS].base; + irq =3D platform_bus_get_irqn(pbus, sbdev, NUM_SMMU_IRQS); + irq +=3D vms->irqmap[VIRT_PLATFORM_BUS]; + irq +=3D ARM_SPI_BASE; + + dev =3D aml_device("CV%.02u", id); + aml_append(dev, aml_name_decl("_HID", aml_string("NVDA200C"))); + aml_append(dev, aml_name_decl("_UID", aml_int(id))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + crs =3D aml_resource_template(); + addr =3D aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_F= IXED, + AML_CACHEABLE, AML_READ_WRITE, 0x0, base, + base + TEGRA241_CMDQV_IO_LEN - 0x1, 0x0, + TEGRA241_CMDQV_IO_LEN); + aml_append(crs, addr); + aml_append(crs, aml_interrupt(AML_CONSUMER, AML_EDGE, + AML_ACTIVE_HIGH, AML_EXCLUSIVE, + (uint32_t *)&irq, 1)); + aml_append(dev, aml_name_decl("_CRS", crs)); + + aml_append(scope, dev); + + trace_virt_acpi_dsdt_tegra241_cmdqv(id, base, irq); + } +} + /* DSDT */ static void build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) @@ -1177,6 +1225,10 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, V= irtMachineState *vms) acpi_dsdt_add_tpm(scope, vms); #endif =20 + if (!vms->legacy_smmuv3_present) { + acpi_dsdt_add_tegra241_cmdqv(scope, vms); + } + aml_append(dsdt, scope); =20 pci0_scope =3D aml_scope("\\_SB.PCI0"); diff --git a/hw/arm/trace-events b/hw/arm/trace-events index ef495c040c..e7e3ccfe9f 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -9,6 +9,7 @@ omap1_lpg_led(const char *onoff) "omap1 LPG: LED is %s" =20 # virt-acpi-build.c virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out." +virt_acpi_dsdt_tegra241_cmdqv(int smmu_id, uint64_t base, uint32_t irq) "D= SDT: add cmdqv node for (id=3D%d), base=3D0x%" PRIx64 ", irq=3D%d" =20 # smmu-common.c smmu_add_mr(const char *name) "%s" --=20 2.43.0 From nobody Mon Mar 2 08:45:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1772103292; cv=pass; d=zohomail.com; s=zohoarc; b=kBqe1FVDkUtOIkMeeLj06y6RGn7Otgj9Uscz8P20HZdloUtmDuxSNa4OB1QaJpfHthp7Dq/DnrhXTEf4Q77GnQa8ad4x7rblEq33Qs9NQTN5zGrzbprU0SqEAoliLOkRgevocDCvy5E6ebhI3rm6Oced6SEmqkLNWuu4qXwWPKo= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772103292; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=b6zcL8egW8OBg5Hzxr3z7eDDsDzF6ejiccc7ySyLxUU=; b=KfXC/2LkCmTfN5FkVWGOQo/Ho4Y7HhNGU87cHQQMPvTwnHRGAPur40X/bj4vHGcxPh6BLocjQRtpPMpCNJtfMe7Pda2ejuwaq/SvoNDeF13bkdp3tvMTFnuG30Mnc11qQrX4QWAUU/reNEMkeepRRjG9QJ/Io6cWjcfJQ1tItbU= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772103292938712.7593728501213; Thu, 26 Feb 2026 02:54:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vvZ0Q-0008Cs-92; Thu, 26 Feb 2026 05:54:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ0O-00081F-2a; Thu, 26 Feb 2026 05:54:04 -0500 Received: from mail-westcentralusazlp170100005.outbound.protection.outlook.com ([2a01:111:f403:c112::5] helo=CY7PR03CU001.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vvZ0M-00017Z-J8; Thu, 26 Feb 2026 05:54:03 -0500 Received: from SN1PR12CA0070.namprd12.prod.outlook.com (2603:10b6:802:20::41) by DM4PR12MB5892.namprd12.prod.outlook.com (2603:10b6:8:68::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9654.14; Thu, 26 Feb 2026 10:53:56 +0000 Received: from SN1PEPF000397B1.namprd05.prod.outlook.com (2603:10b6:802:20:cafe::f) by SN1PR12CA0070.outlook.office365.com (2603:10b6:802:20::41) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9632.25 via Frontend Transport; Thu, 26 Feb 2026 10:53:45 +0000 Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF000397B1.mail.protection.outlook.com (10.167.248.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9632.12 via Frontend Transport; Thu, 26 Feb 2026 10:53:56 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:32 -0800 Received: from NV-2Y5XW94.nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 26 Feb 2026 02:53:28 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=WVkxUYsZqttR6k48W+6PQsLitfDFsaWwLNFvjC3I+GXMhiVLiu15y0cuyq+Q80jDAuvcs+YOKKAq3Lz37lOQBuJiO399VUJL/QAJBQ8KOa9PdGqPhOcZQILcA6kI8GJEdsy2jN21N9QrGG3Rj+2UMgh5IqM0N5+6o+rVeB1Voj+JhXSCUkDLGKb+8viM+oK8JqbSlij1KVMi14KHghjWQHsMxCZGelDzySzzWvJX81Vr2t5/6XbDpRUTPEI1LT9RxdVB7jF/ZTetqlvqbmFb6P1EAaJ4dg364c+27UXjnhCgED6N68N5sgVnrv2mtkO2lfPNCYfm3bzCR8+G7XymQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=b6zcL8egW8OBg5Hzxr3z7eDDsDzF6ejiccc7ySyLxUU=; b=xo3WBEqFcgZnvGleN0xiuhmij4h6m6NEWVwqpCvtO05Fr1/rYWQWXet3zVX+T4enJxApJWmih7fE5DdS6VXeKfAwdOO14K7tWRjQvEjVJH4LwwxlF0zEtI5U08XdI5kvqvukCOEKAAhkJ7wcP7khuABnSgBQBiUZ77k+Yjqgf8UGxKEzXMUBTS5L/Y2xbjzHlj5mdAQkIj9uCRrF30BQKKCZq42S3f1ZkkYZ1+zFctBjLL62BY5kIwspMAyaFYKZ46Q6jxb6myRt+eHLmDOSPS8q14xogzXYh57q3XBTzpOTuRmKZblgP2PNp9NkXqbDqwN3NE+mGSDeYfT19acwPw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=nongnu.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=b6zcL8egW8OBg5Hzxr3z7eDDsDzF6ejiccc7ySyLxUU=; b=qVdKUT7kNhtR0gMbm7nej0CAZ76Lsz2OpgixSBfXywI90qIRcoDvlIyvklCmP+CMyy3nzbN3cQILpPGs8/lf8jj/NbAEC8xfqZsjUZMazh/SyXg84aU27u0vU0VJUHN1042oQ8tH1v+XZKz6IksX/1eH2hM+0/xj1VG6kMpWFgaaaZ4lPTgyDa5bijuTxLvHTQCNzW6RSpTqnaCjzylUnBmPvmpKe21jDGclnMZj4DNZlf+BmnWSHpQl1+QzwLfTyOmc3xorhWcIAbdnMo3Q3Eje5+n2ewtFiCHTKG6xa9r6V9neZACHG8P/ge8Zcw9r0fdUJa2Gs2a38YQMCVoyjQ== X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C From: Shameer Kolothum To: , CC: , , , , , , , , , , , , , , Subject: [PATCH v3 32/32] hw/arm/smmuv3: Add cmdqv property for SMMUv3 device Date: Thu, 26 Feb 2026 10:50:56 +0000 Message-ID: <20260226105056.897-33-skolothumtho@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260226105056.897-1-skolothumtho@nvidia.com> References: <20260226105056.897-1-skolothumtho@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B1:EE_|DM4PR12MB5892:EE_ X-MS-Office365-Filtering-Correlation-Id: be09bc0f-5fd5-4c13-9829-08de752556d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|7416014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: riCYYDGN7s6y8vYdUZ0Zjp4CE0OJutu7UA4PRrS8zVsHQ0qOY4+v2aZ/5Eygzxj9lneZWEfgpJP0ND1NICo4IG7nZ+qo7azqfBeScmGpuquiUsmlFoaQdgO9xSAF2crc8F9wM7sTslsOBTye5mINWHwxek3utHpFyX3BrYcBcCodIibWtUJzlhdH/XJGmPGiTZoAAFWjax/rWAy4jooFRKYSxvBNYXIM5DelWoqFleyIWa7dAEWtvKVy+Ho0GAdCDiPRWj8iwB7VIe40j5EgrugKLMwQ/Bc79Egd8UNG+yGUD60itPEpMW9u4UR9iinuwxRnQPrfnWrOwWzTGKcWePHXqfvCCbrfDqaY3kfbvN6M7XhtnpDX43uOoXvrl08rpbjBdVDnYf53c7i+Z+qBBGjZkdtGYtmRFWAzlVjgzjaSloUH3G5I+7BY7HRAlUEwOrIDCmCVWMG1vxxXmIDRMX5jMv40ShE65sHLHn7tNSFRJP0WJGb5pr0WSvVjUbTWuo8HR5eVfp7FuWVZ2ttGbKQ4QJClwy/mgDYgozcH5qpwHdeI5umN0jBfpvVz+rWlbDdRma2i0d2sDBPKfJgeA4IaS4yvfiq7U/QMV4yQOlpk0nYqQeAjHZett6R7GHw0uYScsZRLQqcvSBsmQR7d5kK1OJ1mir2pv+o3xIws6qU3BgjGvJ1Ib0Y1+b06UKhHEWPgZctpyhHJNVoZ/1x6+WRXyn8udg3+T73N+p4aPs+WB7Ld0mGlutFqzcx2PXrpJpCaSb1Q8Cty6npG4g/dCvtrDOFl6dw1L0QBA1RnQ1//beK7VJvQMewVJweRZRnaksPYW2BmumYCQNvFiNDYfg== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(82310400026)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Oey/rwzRGwEJAo2mVR/JrB1RDa1SEkT7gOnrZROwM4OqSZRNyclkkyDb5iaS02mWdtPI3KSHjKNdNVtt0bCqSXsFPfA6Udl7B9EmzGXHjD2YfXPh5oZVT9IOkIhzEbiHJ4hIXIVBW7gKY91gq+6L+20VWpSCQ8wfwQXGYzhx1uq4fUx25deT+6k+wfUtbNEi/8XVV2tDwfDML47UldmnRB5hWTHAEFBoiCRCElZgWdHp4tB8j+QRLep3ia3/WHdd0+zYrRkCST5PVCk0XV7vNZLgi+Tdws/NwPdRdnWv7Cl5OEDtAihyF8e9n5WXwNcDBypaiDxDGw3HfUuyZ1JhyMLa85jGeVikqBl062bF6VaIkJ+nkzuDjXpqOZ7U17qz/KpVXCE4ED67vHftzsZNMIsj6gj+aIqfRT640nFvQBEHBv3SpZGUJGxEZFb43Jjy X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2026 10:53:56.1228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be09bc0f-5fd5-4c13-9829-08de752556d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5892 Received-SPF: permerror client-ip=2a01:111:f403:c112::5; envelope-from=skolothumtho@nvidia.com; helo=CY7PR03CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1772103293280158501 Introduce a =E2=80=9Ccmdqv=E2=80=9D property to enable Tegra241 CMDQV suppo= rt. This is only enabled for accelerated SMMUv3 devices. Reviewed-by: Nicolin Chen Signed-off-by: Shameer Kolothum --- hw/arm/smmuv3.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c1f84bedd4..70135af015 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1967,6 +1967,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ssidsize can only be set if accel=3Don"); return false; } + if (s->cmdqv =3D=3D ON_OFF_AUTO_ON) { + error_setg(errp, "cmdqv can only be enabled if accel=3Don"); + return false; + } return true; } =20 @@ -2119,6 +2123,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), + DEFINE_PROP_ON_OFF_AUTO("cmdqv", SMMUv3State, cmdqv, ON_OFF_AUTO_AUTO), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2158,6 +2163,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Valid range is 0-20, where 0 disables SubstreamID support. " "Defaults to 0. A value greater than 0 is required to enable " "PASID support."); + object_class_property_set_description(klass, "cmdqv", + "Enable/disable CMDQ-Virtualisation support (for accel=3Don)"); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, --=20 2.43.0