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Wed, 25 Feb 2026 10:06:52 -0800 (PST) From: Daniel Paziyski To: qemu-devel@nongnu.org Cc: mst@redhat.com, pbonzini@redhat.com, Daniel Paziyski Subject: [PATCH] hw/intc/apic: mask LVTs when software disabling the APIC Date: Wed, 25 Feb 2026 19:05:55 +0100 Message-ID: <20260225180555.154428-1-danielpaziyski@gmail.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=danielpaziyski@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 25 Feb 2026 13:28:30 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772044135391158500 Content-Type: text/plain; charset="utf-8" According to the Intel SDM Vol. 3 and the AMD64 Programmer's Manual Vol. 2,= when the APIC is software disabled, doing so by clearing the software enable bit= from the spurious interrupt register, the LVT entries must then have their mask = bit set, and any attempts to clear them must be ignored until the APIC is software e= nabled again. This patch implements that behavior. Signed-off-by: Daniel Paziyski --- hw/intc/apic.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 8766ed0..ef52961 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -919,6 +919,13 @@ static void apic_send_msi(MSIMessage *msi) apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode); } =20 +static void apic_mask_lvts(APICCommonState *s) +{ + for (int i =3D 0; i < APIC_LVT_NB; i++) { + s->lvt[i] |=3D APIC_LVT_MASKED; + } +} + static int apic_register_write(APICCommonState *s, int index, uint64_t val) { trace_apic_register_write(index, val); @@ -964,6 +971,11 @@ static int apic_register_write(APICCommonState *s, int= index, uint64_t val) case 0x0f: s->spurious_vec =3D val & 0x1ff; apic_update_irq(s); + + if (!(val & APIC_SV_ENABLE)) { + apic_mask_lvts(s); + } + break; case 0x10 ... 0x17: case 0x18 ... 0x1f: @@ -997,6 +1009,9 @@ static int apic_register_write(APICCommonState *s, int= index, uint64_t val) { int n =3D index - 0x32; s->lvt[n] =3D val; + if (!(s->spurious_vec & APIC_SV_ENABLE)) { + s->lvt[n] |=3D APIC_LVT_MASKED; + } if (n =3D=3D APIC_LVT_TIMER) { apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)= ); } else if (n =3D=3D APIC_LVT_LINT0 && apic_check_pic(s)) { --=20 2.53.0