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Tue, 24 Feb 2026 07:43:49 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 2/4] target/arm: use FIELD_DP32 instead of open-coding syn_wfx Date: Tue, 24 Feb 2026 15:43:44 +0000 Message-ID: <20260224154347.344219-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260224154347.344219-1-alex.bennee@linaro.org> References: <20260224154347.344219-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771947922155158500 We can use the registerfields API to safely set the individual fields and avoid open coding magic numbers. The EC and IL fields are still driven by defines but we could convert them later. Signed-off-by: Alex Benn=C3=A9e --- target/arm/syndrome.h | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index bff61f052cc..86a2d5ea9d0 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -26,6 +26,7 @@ #define TARGET_ARM_SYNDROME_H =20 #include "qemu/bitops.h" +#include "hw/core/registerfields.h" =20 /* Valid Syndrome Register EC field values */ enum arm_exception_class { @@ -352,11 +353,24 @@ static inline uint32_t syn_breakpoint(int same_el) | ARM_EL_IL | 0x22; } =20 +FIELD(WFX_ISS, TI, 0, 2) +FIELD(WFX_ISS, RV, 14, 1) +FIELD(WFX_ISS, RN, 15, 5) +FIELD(WFX_ISS, COND, 20, 4) +FIELD(WFX_ISS, CV, 24, 1) + static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) { - return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | - (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | - (cv << 24) | (cond << 20) | ti; + uint32_t res =3D (EC_WFX_TRAP << ARM_EL_EC_SHIFT); + + res =3D FIELD_DP32(res, WFX_ISS, CV, cv); + res =3D FIELD_DP32(res, WFX_ISS, COND, cond); + res =3D FIELD_DP32(res, WFX_ISS, TI, ti); + + if (!is_16bit) { + res |=3D ARM_EL_IL; + } + return res; } =20 static inline uint32_t syn_illegalstate(void) --=20 2.47.3