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Tue, 24 Feb 2026 04:10:16 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 1/8] target/arm: set the correct TI bits for WFIT traps Date: Tue, 24 Feb 2026 12:10:07 +0000 Message-ID: <20260224121014.279248-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260224121014.279248-1-alex.bennee@linaro.org> References: <20260224121014.279248-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771935072634158500 The WFIT trap should be reported as 0b10. Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 4d708635068..aa14f15eb62 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -448,7 +448,7 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) =20 if (target_el) { env->pc -=3D 4; - raise_exception(env, excp, syn_wfx(1, 0xe, 0, false), target_el); + raise_exception(env, excp, syn_wfx(1, 0xe, 2, false), target_el); } =20 if (uadd64_overflow(timeout, offset, &nexttick)) { --=20 2.47.3 From nobody Fri Mar 20 20:20:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771935150; cv=none; d=zohomail.com; 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Tue, 24 Feb 2026 04:10:18 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 2/8] .eca: basic configuration for Editor Code Assistant Date: Tue, 24 Feb 2026 12:10:08 +0000 Message-ID: <20260224121014.279248-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260224121014.279248-1-alex.bennee@linaro.org> References: <20260224121014.279248-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::643; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x643.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771935152491158501 This is a basic configuration for eca which is a editor agnostic frame work for connecting skills and tools to an agententic workflow. This is important if you don't want to be tied to a particular platforms editor choice. These would often be user specific but I've included them in this series to show what sort of things they can do. Signed-off-by: Alex Benn=C3=A9e --- .eca/config.json | 43 +++++++++++++++++++++++++++++++++ .eca/skills/checkpatch/SKILL.md | 9 +++++++ .eca/skills/gtags/SKILL.md | 7 ++++++ 3 files changed, 59 insertions(+) create mode 100644 .eca/config.json create mode 100644 .eca/skills/checkpatch/SKILL.md create mode 100644 .eca/skills/gtags/SKILL.md diff --git a/.eca/config.json b/.eca/config.json new file mode 100644 index 00000000000..81b0c97782e --- /dev/null +++ b/.eca/config.json @@ -0,0 +1,43 @@ +{ + "customTools": { + "gtag_find_symbol_definition": { + "description": "Use GNU global tags to search for the symbol def= intion. Return in ctags-x format", + "command": "global --result ctags-x -d {{pattern}}", + "schema": { + "properties": { + "pattern": { + "type": "string", + "description": "an extended regex pattern or literal= string to search for" + } + }, + "required": ["pattern"] + } + }, + "gtag_find_symbol_completions": { + "description": "Use GNU global tags to list potential symbol com= pletions for a word stem.", + "command": "global -c {{stem}}", + "schema": { + "properties": { + "stem": { + "type": "string", + "description": "an string stem of a symbol" + } + }, + "required": ["stem"] + } + }, + "gtag_find_symbol_references": { + "description": "Use GNU global tags to find references to a symb= ol. Returns results in ctags-x format.", + "command": "global --results ctags-x -r {{pattern}}", + "schema": { + "properties": { + "pattern": { + "type": "string", + "description": "an extended regex pattern or literal= string to search for." + } + }, + "required": ["pattern"] + } + } + } +} diff --git a/.eca/skills/checkpatch/SKILL.md b/.eca/skills/checkpatch/SKILL= .md new file mode 100644 index 00000000000..49c556bed2e --- /dev/null +++ b/.eca/skills/checkpatch/SKILL.md @@ -0,0 +1,9 @@ +--- +name: checkpatch +description: run checkpatch on a file or patch to validate style issues +--- + +# Instructions +Run `./scripts/checkpatch.pl [FILE]` to check a file for style issues. + +You can also use a GIT-REV-LIST to check against git, e.g. run `./scripts/= checkpatch.pl HEAD^..` to run checkpatch on the last commit. diff --git a/.eca/skills/gtags/SKILL.md b/.eca/skills/gtags/SKILL.md new file mode 100644 index 00000000000..b158981b1ae --- /dev/null +++ b/.eca/skills/gtags/SKILL.md @@ -0,0 +1,7 @@ +--- +name: update gtags +description: update the GNU global tags file. +--- + +# Instructions +Run `make gtags` in the root of the source tree. --=20 2.47.3 From nobody Fri Mar 20 20:20:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 24 Feb 2026 04:10:17 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 3/8] AGENTS.md: add basic AGENTS.md for QEMU Date: Tue, 24 Feb 2026 12:10:09 +0000 Message-ID: <20260224121014.279248-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260224121014.279248-1-alex.bennee@linaro.org> References: <20260224121014.279248-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771935158486158500 This was written by ECA based on it's initial understanding of the code base. It's mostly quick facts and pointers to common tasks. Signed-off-by: Alex Benn=C3=A9e --- ajb: - I made a slight tweak to use pyenv to run single tests --- AGENTS.md | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 AGENTS.md diff --git a/AGENTS.md b/AGENTS.md new file mode 100644 index 00000000000..5b54763f4b1 --- /dev/null +++ b/AGENTS.md @@ -0,0 +1,18 @@ +# QEMU Agent Guide + +## Build & Test +- **Build**: `ninja -C build` (from build directory) or `make` +- **Test All**: `make check` +- **Single Test**: `./pyvenv/bin/meson test ` (e.g., `meson test= qtest-x86_64/boot-serial-test`) +- **Suites**: `make check-unit`, `make check-qtest`, `make check-functiona= l`, `make check-rust` +- **Debug**: Append `V=3D1` for verbose output or `DEBUG=3D1` for interact= ive test debugging. + +## Code Style +- **Formatting**: 4-space indents, NO tabs, 80-char line limit (max 100). +- **C Braces**: Mandatory for all blocks (if/while/for). Open brace on sam= e line (except functions). +- **C Includes**: `#include "qemu/osdep.h"` MUST be the first include in e= very `.c` file. +- **C Comments**: Use `/* ... */` only. No `//` comments. +- **Naming**: `snake_case` for variables and functions; `CamelCase` for ty= pes and enums. +- **Memory**: Use GLib (`g_malloc`, `g_free`, `g_autofree`) or QEMU (`qemu= _memalign`) APIs. No `malloc`. +- **Errors**: Use `error_report()` or `error_setg()`. Avoid `printf` for e= rrors. +- **Lints**: Run `./scripts/checkpatch.pl` on C patches. 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Tue, 24 Feb 2026 04:10:17 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 4/8] PLAN.md: add plan for the current work Date: Tue, 24 Feb 2026 12:10:10 +0000 Message-ID: <20260224121014.279248-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260224121014.279248-1-alex.bennee@linaro.org> References: <20260224121014.279248-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771935080346158500 This is entirely generated by ECA/Gemini using the gemini-3-flash-preview model. My initial prompt was: I want to generate a PLAN.md for a piece of development work. Recently support for WFE was added for M-profile but I want to extend that support to A-profile along side proper semantics for WFI, WFE, WFIT and WFET instructions. That includes setting the full ISS fields for the traps (RN and RV fields of the ISS encoding from WF* intructions). See syn_wfx() for where we currently build this up. Keep in mind we want each commit to be kept small and review-able while maintaining bisect-ability. We also should think about how we can test and defend the functionality in QEMU's testing suite. This will form the "guide" for the agents next steps. Signed-off-by: Alex Benn=C3=A9e --- PLAN.md | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 PLAN.md diff --git a/PLAN.md b/PLAN.md new file mode 100644 index 00000000000..49f330b802d --- /dev/null +++ b/PLAN.md @@ -0,0 +1,77 @@ +# Plan: Extend WFX Support for A-profile + +This document outlines the plan to extend WFE support to A-profile ARM and= ensure proper semantics for WFI, WFE, WFIT, and WFET instructions, includi= ng full ISS field support for traps. + +## 1. Syndrome Enhancements + +### 1.1 Update `syn_wfx` in `target/arm/syndrome.h` +- Modify `syn_wfx` to include `rd` (RN) and `rv` (Register Valid) fields. +- Ensure the bitfields match the ARM ARM for EC 0x01. +- Bit layout: + - ISS[24]: CV + - ISS[23:20]: COND + - ISS[19:15]: RN (rd) + - ISS[14]: RV + - ISS[1:0]: TI + +### 1.2 Update WFX Syndrome Construction in Helpers +- In `target/arm/tcg/op_helper.c`, update `HELPER(wfi)`, `HELPER(wfit)`, a= nd implement `HELPER(wfet)` to: + - Check `is_a64(env)`. + - For AArch64: Set `cv =3D 0` and `cond =3D 0xf`. + - For AArch32: Maintain `cv =3D 1` and `cond =3D 0xe` (or pass the actua= l condition). + - Pass the correct `rd` and `rv` based on the instruction. + +## 2. Instruction Helpers and Translation + +### 2.1 Update `HELPER(wfit)` and `trans_WFIT` +- Change `HELPER(wfit)` to accept the register number `rd`. +- Update `trans_WFIT` in `target/arm/tcg/translate-a64.c` to pass `a->rd`. + +### 2.2 Implement `HELPER(wfet)` and update `trans_WFET` +- Create `HELPER(wfet)` in `op_helper.c`. It should: + - Check for traps using `check_wfx_trap(env, true, &excp)`. + - If trapped, raise exception with `ti=3D1` and `rv=3Dtrue, rd=3Drd`. + - If not trapped, check `event_register` and timeout. +- Update `trans_WFET` to call the new helper instead of just setting `DISA= S_WFE`. + +### 2.3 Refactor `HELPER(wfe)` for A-profile +- Update `HELPER(wfe)` to handle A-profile: + - Check for traps using `check_wfx_trap(env, true, &excp)`. + - If trapped, raise exception. + - If not trapped: + - If `env->event_register` is set, clear it and return. + - Otherwise, halt the CPU (`cs->halted =3D 1`, `cs->exception_index = =3D EXCP_HLT`, `cpu_loop_exit`). + +## 3. Wake-up Logic and Event Register + +### 3.1 Update `HELPER(sev)` +- Ensure `event_register` is set for all CPUs, not just M-profile. +- Kick all other CPUs to wake them from `EXCP_HLT`. + +### 3.2 Update `arm_cpu_has_work` +- Modify `target/arm/cpu.c` to check `event_register` for A-profile CPUs a= s well. +- This ensures that a CPU halted by WFE wakes up when the event register i= s set. + +## 4. Testing and Verification + +### 4.1 TCG Tests +- Add a new test case in `tests/tcg/aarch64` that: + - Executes WFI, WFE, WFIT, WFET. + - Verifies that WFE/WFI halt the CPU and can be woken up. + - (Optional) Exercises traps by running at EL0 with SCTLR_EL1.nTWE/nTWI = =3D 0 and verifying the syndrome in a signal handler or a small EL1 kernel. + +### 4.2 Regression Testing +- Ensure no regressions for M-profile WFE. +- Run `make check-qtest` and `make check-tcg`. + +## Commit Breakdown (Proposed) + +1. `target/arm: Update syn_wfx to include RN and RV` +2. `target/arm: Update HELPER(wfi) to use correct CV/COND for AArch64` +3. `target/arm: Update HELPER(wfit) to accept rd and use correct syndrome` +4. `target/arm: Implement HELPER(wfet) and update trans_WFET` +5. `target/arm: Update HELPER(wfe) to implement proper A-profile semantics` +6. `target/arm: Update HELPER(sev) and arm_cpu_has_work for A-profile even= t register` +7. `tests/tcg/aarch64: Add tests for WFX instructions` + +=F0=9F=A4=96 Generated with [eca](https://eca.dev) --=20 2.47.3 From nobody Fri Mar 20 20:20:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 24 Feb 2026 04:10:21 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , eca Subject: [PATCH 5/8] target/arm: extend WFX support for A-profile Date: Tue, 24 Feb 2026 12:10:11 +0000 Message-ID: <20260224121014.279248-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260224121014.279248-1-alex.bennee@linaro.org> References: <20260224121014.279248-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771935122502158500 This commit extends support for WFI, WFE, WFIT, and WFET instructions for A-profile ARM CPUs, ensuring proper architectural semantics and full ISS (Instruction Specific Syndrome) field support for traps. Key changes: - Update `syn_wfx` in `target/arm/syndrome.h` to include `RN` (register number) and `RV` (register valid) fields using `registerfields.h` macros. - Refactor `HELPER(wfi)` and `HELPER(wfit)` to use correct AArch64 syndrome values (CV=3D0, COND=3D0xf). - Implement `HELPER(wfet)` and update `trans_WFET` to support the new Wait For Event with Timeout instruction. - Update `HELPER(wfe)` to implement proper A-profile semantics, including trap checks and event register handling. - Extend `event_register` handling to all ARM CPUs (not just M-profile) by updating `HELPER(sev)` and `arm_cpu_has_work`. - Declare WFxT helpers as `TCG_CALL_NO_WG` as they can raise exceptions. =F0=9F=A4=96 Generated with [eca](https://eca.dev) Co-Authored-By: eca --- ajb - this commit is a bit big, it didn't follow the instructions to keep the commits small - I had to add DEF_HELPER_FLAGS_3 to the helpers as it didn't realise we need to ensure rd is potentially rectified. --- target/arm/syndrome.h | 24 ++++++-- target/arm/tcg/helper-defs.h | 3 +- target/arm/cpu.c | 6 +- target/arm/tcg/op_helper.c | 101 +++++++++++++++++++++++---------- target/arm/tcg/translate-a64.c | 17 +++--- 5 files changed, 104 insertions(+), 47 deletions(-) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index bff61f052cc..49861758262 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -26,6 +26,7 @@ #define TARGET_ARM_SYNDROME_H =20 #include "qemu/bitops.h" +#include "hw/core/registerfields.h" =20 /* Valid Syndrome Register EC field values */ enum arm_exception_class { @@ -352,11 +353,26 @@ static inline uint32_t syn_breakpoint(int same_el) | ARM_EL_IL | 0x22; } =20 -static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) +FIELD(WFX_ISS, TI, 0, 2) +FIELD(WFX_ISS, RV, 14, 1) +FIELD(WFX_ISS, RN, 15, 5) +FIELD(WFX_ISS, COND, 20, 4) +FIELD(WFX_ISS, CV, 24, 1) + +static inline uint32_t syn_wfx(int cv, int cond, int rd, int rv, int ti, b= ool is_16bit) { - return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | - (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | - (cv << 24) | (cond << 20) | ti; + uint32_t res =3D (EC_WFX_TRAP << ARM_EL_EC_SHIFT); + + res =3D FIELD_DP32(res, WFX_ISS, CV, cv); + res =3D FIELD_DP32(res, WFX_ISS, COND, cond); + res =3D FIELD_DP32(res, WFX_ISS, RN, rd); + res =3D FIELD_DP32(res, WFX_ISS, RV, rv); + res =3D FIELD_DP32(res, WFX_ISS, TI, ti); + + if (!is_16bit) { + res |=3D ARM_EL_IL; + } + return res; } =20 static inline uint32_t syn_illegalstate(void) diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h index 5a10a9fba3b..d54eb63eef6 100644 --- a/target/arm/tcg/helper-defs.h +++ b/target/arm/tcg/helper-defs.h @@ -55,7 +55,8 @@ DEF_HELPER_2(exception_pc_alignment, noreturn, env, vaddr) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) -DEF_HELPER_2(wfit, void, env, i64) +DEF_HELPER_FLAGS_3(wfit, TCG_CALL_NO_WG, void, env, i64, i32) +DEF_HELPER_FLAGS_3(wfet, TCG_CALL_NO_WG, void, env, i64, i32) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 10f8280eef2..bc789515af9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -144,10 +144,8 @@ static bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); =20 - if (arm_feature(&cpu->env, ARM_FEATURE_M)) { - if (cpu->env.event_register) { - return true; - } + if (cpu->env.event_register) { + return true; } =20 return (cpu->power_state !=3D PSCI_OFF) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index aa14f15eb62..37538daea74 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -393,13 +393,17 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) } =20 if (target_el) { - if (env->aarch64) { + int cv =3D 1, cond =3D 0xe; + + if (is_a64(env)) { env->pc -=3D insn_len; + cv =3D 0; + cond =3D 0xf; } else { env->regs[15] -=3D insn_len; } =20 - raise_exception(env, excp, syn_wfx(1, 0xe, 0, insn_len =3D=3D 2), + raise_exception(env, excp, syn_wfx(cv, cond, 0, 0, 0, insn_len =3D= =3D 2), target_el); } =20 @@ -409,7 +413,7 @@ void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) #endif } =20 -void HELPER(wfit)(CPUARMState *env, uint64_t timeout) +void HELPER(wfit)(CPUARMState *env, uint64_t timeout, uint32_t rd) { #ifdef CONFIG_USER_ONLY /* @@ -448,7 +452,7 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) =20 if (target_el) { env->pc -=3D 4; - raise_exception(env, excp, syn_wfx(1, 0xe, 2, false), target_el); + raise_exception(env, excp, syn_wfx(0, 0xf, rd, 1, 2, false), targe= t_el); } =20 if (uadd64_overflow(timeout, offset, &nexttick)) { @@ -469,14 +473,50 @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout) #endif } =20 +void HELPER(wfet)(CPUARMState *env, uint64_t timeout, uint32_t rd) +{ +#ifdef CONFIG_USER_ONLY + return; +#else + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); + uint32_t excp; + int target_el =3D check_wfx_trap(env, true, &excp); + uint64_t cntval =3D gt_get_countervalue(env); + uint64_t offset =3D gt_direct_access_timer_offset(env, GTIMER_VIRT); + uint64_t cntvct =3D cntval - offset; + uint64_t nexttick; + + if (env->event_register || cpu_has_work(cs) || cntvct >=3D timeout) { + env->event_register =3D false; + return; + } + + if (target_el) { + env->pc -=3D 4; + raise_exception(env, excp, syn_wfx(0, 0xf, rd, 1, 3, false), targe= t_el); + } + + if (uadd64_overflow(timeout, offset, &nexttick)) { + nexttick =3D UINT64_MAX; + } + if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { + timer_mod_ns(cpu->wfxt_timer, INT64_MAX); + } else { + timer_mod(cpu->wfxt_timer, nexttick); + } + cs->exception_index =3D EXCP_HLT; + cs->halted =3D 1; + cpu_loop_exit(cs); +#endif +} + void HELPER(sev)(CPUARMState *env) { CPUState *cs =3D env_cpu(env); CPU_FOREACH(cs) { ARMCPU *target_cpu =3D ARM_CPU(cs); - if (arm_feature(&target_cpu->env, ARM_FEATURE_M)) { - target_cpu->env.event_register =3D true; - } + target_cpu->env.event_register =3D true; if (!qemu_cpu_is_self(cs)) { qemu_cpu_kick(cs); } @@ -493,33 +533,34 @@ void HELPER(wfe)(CPUARMState *env) */ return; #else - /* - * WFE (Wait For Event) is a hint instruction. - * For Cortex-M (M-profile), we implement the strict architectural beh= avior: - * 1. Check the Event Register (set by SEV or SEVONPEND). - * 2. If set, clear it and continue (consume the event). - */ - if (arm_feature(env, ARM_FEATURE_M)) { - CPUState *cs =3D env_cpu(env); + CPUState *cs =3D env_cpu(env); + uint32_t excp; + int target_el =3D check_wfx_trap(env, true, &excp); =20 - if (env->event_register) { - env->event_register =3D false; - return; + if (env->event_register) { + env->event_register =3D false; + return; + } + + if (target_el) { + bool is_16bit =3D false; + if (is_a64(env)) { + env->pc -=3D 4; + } else { + is_16bit =3D env->thumb; + env->regs[15] -=3D (is_16bit ? 2 : 4); } =20 - cs->exception_index =3D EXCP_HLT; - cs->halted =3D 1; - cpu_loop_exit(cs); - } else { - /* - * For A-profile and others, we rely on the existing "yield" behav= ior. - * Don't actually halt the CPU, just yield back to top - * level loop. This is not going into a "low power state" - * (ie halting until some event occurs), so we never take - * a configurable trap to a different exception level - */ - HELPER(yield)(env); + raise_exception(env, excp, + syn_wfx(is_a64(env) ? 0 : 1, + is_a64(env) ? 0xf : 0xe, + 0, 0, 1, is_16bit), + target_el); } + + cs->exception_index =3D EXCP_HLT; + cs->halted =3D 1; + cpu_loop_exit(cs); #endif } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5d261a5e32b..f76a00d1329 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2064,7 +2064,7 @@ static bool trans_WFIT(DisasContext *s, arg_WFIT *a) } =20 gen_a64_update_pc(s, 4); - gen_helper_wfit(tcg_env, cpu_reg(s, a->rd)); + gen_helper_wfit(tcg_env, cpu_reg(s, a->rd), tcg_constant_i32(a->rd)); /* Go back to the main loop to check for interrupts */ s->base.is_jmp =3D DISAS_EXIT; return true; @@ -2076,14 +2076,15 @@ static bool trans_WFET(DisasContext *s, arg_WFET *a) return false; } =20 - /* - * We rely here on our WFE implementation being a NOP, so we - * don't need to do anything different to handle the WFET timeout - * from what trans_WFE does. - */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_WFE; + if (s->ss_active) { + /* Act like a NOP under architectural singlestep */ + return true; } + + gen_a64_update_pc(s, 4); + gen_helper_wfet(tcg_env, cpu_reg(s, a->rd), tcg_constant_i32(a->rd)); + /* Go back to the main loop to check for interrupts */ + s->base.is_jmp =3D DISAS_EXIT; return true; } =20 --=20 2.47.3 From nobody Fri Mar 20 20:20:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771935081; cv=none; d=zohomail.com; s=zohoarc; b=hIdhfXnfaqVDm4XoIUG8SQcbdbFha826FEnIQTHB8VIl09qKmdreBOzIwHtRilKkMa2iz9NI7dSVp0TuJ4ovuamnj506raBDbAUdSeEhSCxi3K08WhA7lT9r60/vNY5+N+3V4aDA2r+KT2NuYrm/FRUm+fLmEqfl8ZvwPkhacsA= ARC-Message-Signature: i=1; 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Tue, 24 Feb 2026 04:10:20 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , eca Subject: [PATCH 6/8] tests/tcg/aarch64: Add WFX instructions system test Date: Tue, 24 Feb 2026 12:10:12 +0000 Message-ID: <20260224121014.279248-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260224121014.279248-1-alex.bennee@linaro.org> References: <20260224121014.279248-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771935082252158500 This commit adds a new system-mode TCG test to verify the behavior of WFI, WFE, WFIT, and WFET instructions on AArch64. The test ensures: - WFI correctly wakes on a timer interrupt. - WFE returns immediately if the event register is set (via SEV). - WFIT and WFET correctly sleep until the specified timeout. =F0=9F=A4=96 Generated with [eca](https://eca.dev) Co-Authored-By: eca --- ajb: - removed an excess setting of QEMU_OPTS in the Makefile --- tests/tcg/aarch64/system/wfx.c | 113 ++++++++++++++++++++++ tests/tcg/aarch64/Makefile.softmmu-target | 2 + 2 files changed, 115 insertions(+) create mode 100644 tests/tcg/aarch64/system/wfx.c diff --git a/tests/tcg/aarch64/system/wfx.c b/tests/tcg/aarch64/system/wfx.c new file mode 100644 index 00000000000..59436c381fd --- /dev/null +++ b/tests/tcg/aarch64/system/wfx.c @@ -0,0 +1,113 @@ +/* + * WFX Instructions Test (WFI, WFE, WFIT, WFET) + * + * Copyright (c) 2024 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +#define __stringify_1(x...) #x +#define __stringify(x...) __stringify_1(x) + +#define read_sysreg(r) ({ \ + uint64_t __val; \ + asm volatile("mrs %0, " __stringify(r) : "=3Dr" (__val)); \ + __val; \ +}) + +#define write_sysreg(r, v) do { \ + uint64_t __val =3D (uint64_t)(v); \ + asm volatile("msr " __stringify(r) ", %x0" \ + : : "rZ" (__val)); \ +} while (0) + +#define isb() asm volatile("isb" : : : "memory") +#define sev() asm volatile("sev" : : : "memory") +#define wfi() asm volatile("wfi" : : : "memory") +#define wfe() asm volatile("wfe" : : : "memory") +#define wfit(reg) asm volatile("wfit %0" : : "r" (reg) : "memory") +#define wfet(reg) asm volatile("wfet %0" : : "r" (reg) : "memory") + +static void wait_ticks(uint64_t ticks) +{ + uint64_t start =3D read_sysreg(cntvct_el0); + while ((read_sysreg(cntvct_el0) - start) < ticks) { + /* spin */ + } +} + +int main(void) +{ + uint64_t start, end, elapsed; + uint64_t timeout; + + ml_printf("WFX Test\n"); + + /* 1. Test WFI with timer interrupt */ + ml_printf("Testing WFI..."); + /* Setup virtual timer to fire in 100000 ticks (~2ms at 50MHz) */ + start =3D read_sysreg(cntvct_el0); + write_sysreg(cntv_tval_el0, 100000); + write_sysreg(cntv_ctl_el0, 1); /* Enable timer, no mask */ + isb(); + + /* + * We don't have a full interrupt handler, but WFI should wake up + * when the interrupt is pending even if we have it masked at the CPU. + * PSTATE.I is set by boot code. + */ + wfi(); + end =3D read_sysreg(cntvct_el0); + elapsed =3D end - start; + if (elapsed < 100000) { + ml_printf("FAILED: WFI woke too early (%ld ticks)\n", elapsed); + return 1; + } + ml_printf("PASSED (elapsed %ld ticks)\n", elapsed); + write_sysreg(cntv_ctl_el0, 0); /* Disable timer */ + + /* 2. Test WFE and SEV */ + ml_printf("Testing WFE/SEV..."); + sev(); /* Set event register */ + start =3D read_sysreg(cntvct_el0); + wfe(); /* Should return immediately */ + end =3D read_sysreg(cntvct_el0); + elapsed =3D end - start; + if (elapsed > 1000) { /* Should be very fast */ + ml_printf("FAILED: WFE slept despite SEV (%ld ticks)\n", elapsed); + return 1; + } + ml_printf("PASSED\n"); + + /* 3. Test WFIT */ + ml_printf("Testing WFIT..."); + start =3D read_sysreg(cntvct_el0); + timeout =3D start + 200000; + wfit(timeout); + end =3D read_sysreg(cntvct_el0); + elapsed =3D end - start; + if (elapsed < 200000) { + ml_printf("FAILED: WFIT woke too early (%ld ticks)\n", elapsed); + return 1; + } + ml_printf("PASSED (elapsed %ld ticks)\n", elapsed); + + /* 4. Test WFET */ + ml_printf("Testing WFET..."); + start =3D read_sysreg(cntvct_el0); + timeout =3D start + 200000; + wfet(timeout); + end =3D read_sysreg(cntvct_el0); + elapsed =3D end - start; + if (elapsed < 200000) { + ml_printf("FAILED: WFET woke too early (%ld ticks)\n", elapsed); + return 1; + } + ml_printf("PASSED (elapsed %ld ticks)\n", elapsed); + + ml_printf("ALL WFX TESTS PASSED\n"); + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/= Makefile.softmmu-target index f7a7d2b800f..84342c52cd7 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -102,6 +102,8 @@ run-pauth-3: $(call skip-test, "RUN of pauth-3", "not built") endif =20 +wfx: CFLAGS +=3D -march=3Darmv8.7-a + ifneq ($(CROSS_CC_HAS_ARMV8_MTE),) QEMU_MTE_ENABLED_MACHINE=3D-M virt,mte=3Don -cpu max -display none QEMU_OPTS_WITH_MTE_ON =3D $(QEMU_MTE_ENABLED_MACHINE) $(QEMU_BASE_ARGS) -k= ernel --=20 2.47.3 From nobody Fri Mar 20 20:20:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 24 Feb 2026 04:10:19 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 7/8] tests/tcg/aarch64: fixes for WFX instructions system test Date: Tue, 24 Feb 2026 12:10:13 +0000 Message-ID: <20260224121014.279248-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260224121014.279248-1-alex.bennee@linaro.org> References: <20260224121014.279248-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771935144687158500 This required some iteration with the model to add bits it missed in the initial implementation. I ended up debugging and then prompting for the missing bits: - a basic gicv3 implementation - a couple of rounds of tweaking the config - mapping the GIC via page tables - fixing the compilation of the support library - extending the elapsed time check for WFE - light re-ordering of Makefile, setting correct machine opts Signed-off-by: Alex Benn=C3=A9e --- tests/tcg/aarch64/system/lib/gicv3.h | 56 +++++++++++++++++ tests/tcg/aarch64/system/lib/gicv3.c | 77 +++++++++++++++++++++++ tests/tcg/aarch64/system/wfx.c | 17 ++++- tests/tcg/aarch64/Makefile.softmmu-target | 13 +++- tests/tcg/aarch64/system/boot.S | 55 ++++++++++------ 5 files changed, 196 insertions(+), 22 deletions(-) create mode 100644 tests/tcg/aarch64/system/lib/gicv3.h create mode 100644 tests/tcg/aarch64/system/lib/gicv3.c diff --git a/tests/tcg/aarch64/system/lib/gicv3.h b/tests/tcg/aarch64/syste= m/lib/gicv3.h new file mode 100644 index 00000000000..9a1268937c6 --- /dev/null +++ b/tests/tcg/aarch64/system/lib/gicv3.h @@ -0,0 +1,56 @@ +/* + * GICv3 Helper Library + * + * Copyright (c) 2024 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef GICV3_H +#define GICV3_H + +#include + +/* Virt machine GICv3 base addresses */ +#define GICD_BASE 0x08000000 /* c.f. VIRT_GIC_DIST */ +#define GICR_BASE 0x080a0000 /* c.f. VIRT_GIC_REDIST */ + +/* Distributor registers */ +#define GICD_CTLR (GICD_BASE + 0x0000) +#define GICD_TYPER (GICD_BASE + 0x0004) +#define GICD_IIDR (GICD_BASE + 0x0008) + +/* Redistributor registers (per-CPU) */ +#define GICR_SGI_OFFSET 0x00010000 + +#define GICR_CTLR 0x0000 +#define GICR_WAKER 0x0014 +#define GICR_IGROUPR0 (GICR_SGI_OFFSET + 0x0080) +#define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100) +#define GICR_IPRIORITYR0 (GICR_SGI_OFFSET + 0x0400) + +/* GICD_CTLR bits */ +#define GICD_CTLR_ARE_NS (1U << 4) +#define GICD_CTLR_ENA_G1NS (1U << 1) +#define GICD_CTLR_ENA_G0 (1U << 0) + +/* GICR_WAKER bits */ +#define GICR_WAKER_ChildrenAsleep (1U << 2) +#define GICR_WAKER_ProcessorSleep (1U << 1) + +/** + * gicv3_init: + * + * Initialize GICv3 distributor and the redistributor for the current CPU. + */ +void gicv3_init(void); + +/** + * gicv3_enable_irq: + * @irq: The IRQ number to enable + * + * Enable the specified IRQ (SPI or PPI). + */ +void gicv3_enable_irq(unsigned int irq); + +#endif /* GICV3_H */ diff --git a/tests/tcg/aarch64/system/lib/gicv3.c b/tests/tcg/aarch64/syste= m/lib/gicv3.c new file mode 100644 index 00000000000..a09a0e430e6 --- /dev/null +++ b/tests/tcg/aarch64/system/lib/gicv3.c @@ -0,0 +1,77 @@ +/* + * GICv3 Helper Library Implementation + * + * Copyright (c) 2024 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "gicv3.h" + +#define write_sysreg(r, v) do { \ + uint64_t __val =3D (uint64_t)(v); \ + asm volatile("msr " #r ", %x0" \ + : : "rZ" (__val)); \ +} while (0) + +#define isb() asm volatile("isb" : : : "memory") + +static inline void write_reg(uintptr_t addr, uint32_t val) +{ + *(volatile uint32_t *)addr =3D val; +} + +static inline uint32_t read_reg(uintptr_t addr) +{ + return *(volatile uint32_t *)addr; +} + +void gicv3_init(void) +{ + uint32_t val; + + /* 1. Enable Distributor ARE and Group 1 NS */ + val =3D read_reg(GICD_CTLR); + val |=3D GICD_CTLR_ARE_NS | GICD_CTLR_ENA_G1NS; + write_reg(GICD_CTLR, val); + + /* 2. Wake up Redistributor 0 */ + /* Clear ProcessorSleep */ + val =3D read_reg(GICR_BASE + GICR_WAKER); + val &=3D ~GICR_WAKER_ProcessorSleep; + write_reg(GICR_BASE + GICR_WAKER, val); + + /* Wait for ChildrenAsleep to be cleared */ + while (read_reg(GICR_BASE + GICR_WAKER) & GICR_WAKER_ChildrenAsleep) { + /* spin */ + } + + /* 3. Enable CPU interface */ + /* Set Priority Mask to allow all interrupts */ + write_sysreg(ICC_PMR_EL1, 0xff); + /* Enable Group 1 Non-Secure interrupts */ + write_sysreg(ICC_IGRPEN1_EL1, 1); + isb(); +} + +void gicv3_enable_irq(unsigned int irq) +{ + if (irq < 32) { + /* PPI: use GICR_ISENABLER0 */ + uintptr_t addr; + + /* Set Group 1 */ + addr =3D GICR_BASE + GICR_IGROUPR0; + write_reg(addr, read_reg(addr) | (1U << irq)); + + /* Set priority (0xa0) */ + addr =3D GICR_BASE + GICR_IPRIORITYR0 + irq; + *(volatile uint8_t *)addr =3D 0xa0; + + /* Enable it */ + addr =3D GICR_BASE + GICR_ISENABLER0; + write_reg(addr, 1U << irq); + } else { + /* SPI: not implemented yet */ + } +} diff --git a/tests/tcg/aarch64/system/wfx.c b/tests/tcg/aarch64/system/wfx.c index 59436c381fd..567d9e59c70 100644 --- a/tests/tcg/aarch64/system/wfx.c +++ b/tests/tcg/aarch64/system/wfx.c @@ -8,6 +8,7 @@ =20 #include #include +#include "gicv3.h" =20 #define __stringify_1(x...) #x #define __stringify(x...) __stringify_1(x) @@ -31,6 +32,9 @@ #define wfit(reg) asm volatile("wfit %0" : : "r" (reg) : "memory") #define wfet(reg) asm volatile("wfet %0" : : "r" (reg) : "memory") =20 +#define enable_irq() asm volatile("msr daifclr, #2" : : : "memory") +#define disable_irq() asm volatile("msr daifset, #2" : : : "memory") + static void wait_ticks(uint64_t ticks) { uint64_t start =3D read_sysreg(cntvct_el0); @@ -44,6 +48,9 @@ int main(void) uint64_t start, end, elapsed; uint64_t timeout; =20 + gicv3_init(); + gicv3_enable_irq(27); /* Virtual Timer PPI */ + ml_printf("WFX Test\n"); =20 /* 1. Test WFI with timer interrupt */ @@ -58,8 +65,13 @@ int main(void) * We don't have a full interrupt handler, but WFI should wake up * when the interrupt is pending even if we have it masked at the CPU. * PSTATE.I is set by boot code. + * + * We unmask interrupts here to ensure the CPU can take the minimal + * exception handler defined in boot.S. */ + enable_irq(); wfi(); + disable_irq(); end =3D read_sysreg(cntvct_el0); elapsed =3D end - start; if (elapsed < 100000) { @@ -76,11 +88,12 @@ int main(void) wfe(); /* Should return immediately */ end =3D read_sysreg(cntvct_el0); elapsed =3D end - start; - if (elapsed > 1000) { /* Should be very fast */ + /* while this should be fast there is some overhead from TCG */ + if (elapsed > 20000) { ml_printf("FAILED: WFE slept despite SEV (%ld ticks)\n", elapsed); return 1; } - ml_printf("PASSED\n"); + ml_printf("PASSED (%ld ticks)\n", elapsed); =20 /* 3. Test WFIT */ ml_printf("Testing WFIT..."); diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/= Makefile.softmmu-target index 84342c52cd7..9a5b95de621 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -4,8 +4,9 @@ =20 AARCH64_SRC=3D$(SRC_PATH)/tests/tcg/aarch64 AARCH64_SYSTEM_SRC=3D$(AARCH64_SRC)/system +AARCH64_SYSTEM_LIB_SRC=3D$(AARCH64_SYSTEM_SRC)/lib =20 -VPATH+=3D$(AARCH64_SYSTEM_SRC) +VPATH+=3D$(AARCH64_SYSTEM_SRC) $(AARCH64_SYSTEM_LIB_SRC) =20 # These objects provide the basic boot code and helper functions for all t= ests CRT_OBJS=3Dboot.o @@ -24,7 +25,7 @@ LINK_SCRIPT=3D$(AARCH64_SYSTEM_SRC)/kernel.ld LDFLAGS=3D-Wl,-T$(LINK_SCRIPT) TESTS+=3D$(AARCH64_TESTS) $(MULTIARCH_TESTS) EXTRA_RUNS+=3D$(MULTIARCH_RUNS) -CFLAGS+=3D-nostdlib -ggdb -O0 $(MINILIB_INC) +CFLAGS+=3D-nostdlib -ggdb -O0 $(MINILIB_INC) -I$(AARCH64_SYSTEM_LIB_SRC) LDFLAGS+=3D-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc =20 config-cc.mak: Makefile @@ -102,7 +103,15 @@ run-pauth-3: $(call skip-test, "RUN of pauth-3", "not built") endif =20 +gicv3.o: gicv3.c gicv3.h + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + wfx: CFLAGS +=3D -march=3Darmv8.7-a +wfx: LDFLAGS +=3D gicv3.o +wfx: gicv3.o + +QEMU_GICV3_MACHINE=3D-M virt,gic-version=3D3 -cpu max -display none +run-wfx: QEMU_OPTS=3D$(QEMU_GICV3_MACHINE) $(QEMU_BASE_ARGS) -kernel =20 ifneq ($(CROSS_CC_HAS_ARMV8_MTE),) QEMU_MTE_ENABLED_MACHINE=3D-M virt,mte=3Don -cpu max -display none diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boo= t.S index 8bfa4e4efc7..6a71fc0da5a 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -60,7 +60,6 @@ curr_sp0_irq: curr_sp0_fiq: curr_sp0_serror: curr_spx_sync: -curr_spx_irq: curr_spx_fiq: curr_spx_serror: lower_a64_sync: @@ -248,29 +247,34 @@ at_testel: msr ttbr0_el1, x0 =20 /* - * Setup a flat address mapping page-tables. Stage one simply - * maps RAM to the first Gb. The stage2 tables have two 2mb - * translation block entries covering a series of adjacent - * 4k pages. + * Setup a flat address mapping page-tables. + * + * ttb (Level 1): + * - Entry 0 [0 - 1GB]: 1GB Device block (for GIC and other H/W) + * - Entry 1 [1GB - 2GB]: Table entry pointing to ttb_stage2 (for RAM) */ =20 - /* Stage 1 entry: indexed by IA[38:30] */ - adr x1, . /* phys address */ - bic x1, x1, #(1 << 30) - 1 /* 1GB alignment*/ - add x2, x0, x1, lsr #(30 - 3) /* offset in l1 page table */ + /* Entry 0: 1GB Device block mapping at 0x0 */ + ldr x1, =3D0x401 | (1 << 2) /* AF=3D1, block, AttrIndx=3DAttr1 (Device) = */ + str x1, [x0] =20 - /* point to stage 2 table [47:12] */ - adrp x0, ttb_stage2 - orr x1, x0, #3 /* ptr to stage 2 */ - str x1, [x2] + /* Entry 1: Table entry pointing to ttb_stage2 */ + adrp x1, ttb_stage2 + orr x1, x1, #3 /* ptr to table (type=3D3) */ + str x1, [x0, #8] =20 - /* Stage 2 entries: indexed by IA[29:21] */ + /* Stage 2 entries: indexed by IA[29:21] (within 1GB-2GB range) */ + adrp x0, ttb_stage2 + add x0, x0, :lo12:ttb_stage2 ldr x5, =3D(((1 << 9) - 1) << 21) =20 /* First block: .text/RO/execute enabled */ adr x1, . /* phys address */ bic x1, x1, #(1 << 21) - 1 /* 2mb block alignment */ - and x4, x1, x5 /* IA[29:21] */ + /* Note: we assume RAM is in the 1GB-2GB range, so IA[30] is 1 */ + mov x4, x1 + bic x4, x4, #(1 << 30) /* remove 1GB offset for L2 index */ + and x4, x4, x5 /* IA[29:21] */ add x2, x0, x4, lsr #(21 - 3) /* offset in l2 page table */ ldr x3, =3D0x401 /* attr(AF, block) */ orr x1, x1, x3 @@ -280,7 +284,9 @@ at_testel: adrp x1, .data add x1, x1, :lo12:.data bic x1, x1, #(1 << 21) - 1 /* 2mb block alignment */ - and x4, x1, x5 /* IA[29:21] */ + mov x4, x1 + bic x4, x4, #(1 << 30) /* remove 1GB offset for L2 index */ + and x4, x4, x5 /* IA[29:21] */ add x2, x0, x4, lsr #(21 - 3) /* offset in l2 page table */ ldr x3, =3D(3 << 53) | 0x401 /* attr(AF, NX, block) */ orr x1, x1, x3 @@ -290,7 +296,9 @@ at_testel: adrp x1, mte_page add x1, x1, :lo12:mte_page bic x1, x1, #(1 << 21) - 1 - and x4, x1, x5 + mov x4, x1 + bic x4, x4, #(1 << 30) /* remove 1GB offset for L2 index */ + and x4, x4, x5 add x2, x0, x4, lsr #(21 - 3) /* attr(AF, NX, block, AttrIndx=3DAttr1) */ ldr x3, =3D(3 << 53) | 0x401 | (1 << 2) @@ -317,7 +325,7 @@ at_testel: ldr x0, =3D (2 << 32) | 25 | (3 << 10) | (3 << 8) msr tcr_el1, x0 =20 - mov x0, #0xee /* Inner/outer cacheable WB */ + ldr x0, =3D0x04ee /* Attr1: Device-nGnRE, Attr0: Normal WB */ msr mair_el1, x0 isb =20 @@ -370,6 +378,17 @@ _exit: semihosting_call /* never returns */ =20 + /* + * IRQ handler + */ + .global curr_spx_irq +curr_spx_irq: + /* Minimal IRQ handler: just mask the timer and return */ + mrs x0, cntv_ctl_el0 + orr x0, x0, #2 /* IMASK=3D1 */ + msr cntv_ctl_el0, x0 + eret + /* * Helper Functions */ --=20 2.47.3 From nobody Fri Mar 20 20:20:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 24 Feb 2026 04:10:19 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 8/8] target/arm: fixes for WFx[T] support Date: Tue, 24 Feb 2026 12:10:14 +0000 Message-ID: <20260224121014.279248-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260224121014.279248-1-alex.bennee@linaro.org> References: <20260224121014.279248-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771935096299158500 These are the bits I needed to fix manually on top of what the model had done. - ensure the SEV instruction is enabled for aa64 - remove the FEATURE_M check for aa32 - add an exit block so WFE can fall through On the last change I see the DISAS_WFI does tcg_gen_exit_tb to ensure we check for interrupts. However for yield and wfe we should just be able to roll into the next instruction. We could probably rationalise DISAS cases for all of these into a common handling. Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/a64.decode | 3 +-- target/arm/tcg/translate-a64.c | 10 ++++++++++ target/arm/tcg/translate.c | 4 +--- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 01b1b3e38be..d5b65d79da1 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -237,8 +237,7 @@ ERETA 1101011 0100 11111 00001 m:1 11111 1111= 1 &reta # ERETAA, ERETAB YIELD 1101 0101 0000 0011 0010 0000 001 11111 WFE 1101 0101 0000 0011 0010 0000 010 11111 WFI 1101 0101 0000 0011 0010 0000 011 11111 - # We implement WFE to never block, so our SEV/SEVL are NOPs - # SEV 1101 0101 0000 0011 0010 0000 100 11111 + SEV 1101 0101 0000 0011 0010 0000 100 11111 # SEVL 1101 0101 0000 0011 0010 0000 101 11111 # Our DGL is a NOP because we don't merge memory accesses anyway. # DGL 1101 0101 0000 0011 0010 0000 110 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f76a00d1329..4714bedd01c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2032,6 +2032,14 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } =20 +static bool trans_SEV(DisasContext *s, arg_SEV *a) +{ +#ifndef CONFIG_USER_ONLY + gen_helper_sev(tcg_env); +#endif + return true; +} + static bool trans_WFE(DisasContext *s, arg_WFI *a) { /* @@ -10918,6 +10926,8 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) case DISAS_WFE: gen_a64_update_pc(dc, 4); gen_helper_wfe(tcg_env); + gen_goto_tb(dc, 1, 4); + /* tcg_gen_exit_tb(NULL, 0); */ break; case DISAS_YIELD: gen_a64_update_pc(dc, 4); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index f9d1b8897d2..78ba7d2fde5 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3248,9 +3248,7 @@ static bool trans_SEV(DisasContext *s, arg_SEV *a) * For system-mode M-profile, it sets the event register. */ #ifndef CONFIG_USER_ONLY - if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_helper_sev(tcg_env); - } + gen_helper_sev(tcg_env); #endif return true; } --=20 2.47.3