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bh=KLMVteDKeSztFnB7DlEdsXNoavsyA9g+dxs2AI28N50=; b=hRRaR6HPUC5NUDlSw3c3D+4qxbKAX8Pi8WnaqCXtqfGCxG+ADhI02Cq7f2OS54jwhE+/RsG2bVNSKB8xlNRJ2ADCEL9Ftkqp5R3gn+Yw4R7lzNgvfQ/A79zFa0zsbkMeSjOq3KW+KFwD6CLe6K61CHKfyByaxk5RlFjlc6MG8MHu5mVAwjeqVdao+rdsYvt9qzOoW57AM59j01ZnkZ/AZWv/j98guPkiXYvaZDTEVal7TTNfxOVQgdcYProejOY6sTY0APVBRltuH91uudbWXfRQhp5FiKeiSBBHBH2B95Y7cwgt6p8qlNIuEe6uV1qXRTNOjOFJfxbgbel7b3VmzQ== From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , Alistair Francis , Kevin Wolf , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: Jamin Lin , Troy Lee , Kane Chen Subject: [PATCH v3 06/15] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers Thread-Topic: [PATCH v3 06/15] hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU registers Thread-Index: AQHcpVqll9uqL8XBHEGA/qoh5piBTw== Date: Tue, 24 Feb 2026 06:56:05 +0000 Message-ID: <20260224065556.3847942-7-jamin_lin@aspeedtech.com> References: <20260224065556.3847942-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260224065556.3847942-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:111:f403:c405::5; envelope-from=jamin_lin@aspeedtech.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @aspeedtech.com) X-ZM-MESSAGEID: 1771916292907158500 Content-Type: text/plain; charset="utf-8" This patch implements TSP reset and power control logic in the SCU module for AST2700. It introduces support for the following behavior: 1. TSP Reset Trigger (via SCU 0x220): - TSP reset is triggered by writing 1 to bit 9 (RW1S) of SYS_RESET_CTRL_= 2. 2. TSP Reset State and Source Hold (via SCU 0x160): - Upon reset, bit 8 (RST_RB) is set to indicate the TSP is in reset. - Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an e= xternal source. - Bit 1 (RST) is a software-controlled bit used to request holding TSP i= n reset. - If an external reset source is present and bit 1 is set, bit 9 (RST_HO= LD_RB) will also be asserted to indicate the TSP is being held in reset. - If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly. 3. Hold Release and Power-on: - If RST_HOLD_RB is clear (0), TSP is powered on immediately after reset= is deasserted. - If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to TSP_C= TRL_0 to release the hold and power on TSP explicitly. - Writing ENABLE (bit 0) is a one-shot operation and will auto-clear aft= er execution. 4. Reset Status Clear (via SCU 0x224): - The reset status can be cleared by writing 1 to bit 9 (RW1C) of SYS_RS= T_CLR_2, which will deassert RST_SRC_RB and potentially trigger power-on if no = hold is active. 5. TSP Power Control Logic: - handle_ssp_tsp_on() clears RST_SRC_RB and RST_RB (if not held), and in= vokes arm_set_cpu_on_and_reset(cpuid) to power on the TSP core (CPUID 5). - handle_ssp_tsp_off() sets RST_RB and RST_SRC_RB; if RST is active, als= o asserts RST_HOLD_RB and invokes arm_set_cpu_off(cpuid). The default values are based on EVB (evaluation board) register dump observ= ations. TSP reset control shares the same helper functions and register bit layout = as SSP, with logic selected by cpuid and distinct external reset sources. Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 56f7e214b9..15c8b06487 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -147,6 +147,7 @@ =20 /* SSP TSP */ #define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120) +#define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160) #define AST2700_SSP_TSP_ENABLE BIT(0) #define AST2700_SSP_TSP_RST BIT(1) #define AST2700_SSP_TSP_RST_RB BIT(8) @@ -155,6 +156,9 @@ #define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200) #define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204) #define AST2700_SCU_SYS_RST_SSP BIT(30) +#define AST2700_SCU_SYS_RST_CTRL_2 TO_REG(0x220) +#define AST2700_SCU_SYS_RST_CLR_2 TO_REG(0x224) +#define AST2700_SCU_SYS_RST_TSP BIT(9) =20 #define AST2700_SCU_CLK_SEL_1 TO_REG(0x280) #define AST2700_SCU_HPLL_PARAM TO_REG(0x300) @@ -1002,7 +1006,10 @@ static void aspeed_ast2700_scu_write(void *opaque, h= waddr offset, =20 switch (reg) { case AST2700_SCU_SSP_CTRL_0: - cpuid =3D s->ssp_cpuid; + case AST2700_SCU_TSP_CTRL_0: + cpuid =3D (reg =3D=3D AST2700_SCU_SSP_CTRL_0) ? + s->ssp_cpuid : s->tsp_cpuid; + if (cpuid < 0) { return; } @@ -1058,6 +1065,28 @@ static void aspeed_ast2700_scu_write(void *opaque, h= waddr offset, } s->regs[AST2700_SCU_SYS_RST_CTRL_1] &=3D ~active; return; + case AST2700_SCU_SYS_RST_CTRL_2: + if (s->tsp_cpuid < 0) { + return; + } + data &=3D 0x00001fff; + if (data & AST2700_SCU_SYS_RST_TSP) { + handle_2700_ssp_tsp_off(s, s->tsp_cpuid, AST2700_SCU_TSP_CTRL_= 0); + } + s->regs[reg] |=3D data; + return; + case AST2700_SCU_SYS_RST_CLR_2: + if (s->tsp_cpuid < 0) { + return; + } + data &=3D 0x00001fff; + oldval =3D s->regs[AST2700_SCU_SYS_RST_CTRL_2]; + active =3D data & oldval; + if (active & AST2700_SCU_SYS_RST_TSP) { + handle_2700_ssp_tsp_on(s, s->tsp_cpuid, AST2700_SCU_TSP_CTRL_0= ); + } + s->regs[AST2700_SCU_SYS_RST_CTRL_2] &=3D ~active; + return; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n", @@ -1086,7 +1115,9 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST270= 0_SCU_NR_REGS] =3D { [AST2700_HW_STRAP1_SEC2] =3D 0x00000000, [AST2700_HW_STRAP1_SEC3] =3D 0x1000408F, [AST2700_SCU_SSP_CTRL_0] =3D 0x000007FE, + [AST2700_SCU_TSP_CTRL_0] =3D 0x000007FE, [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC, + [AST2700_SCU_SYS_RST_CTRL_2] =3D 0x00001FFF, [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f, [AST2700_SCU_HPLL_EXT_PARAM] =3D 0x8000004f, [AST2700_SCU_DPLL_PARAM] =3D 0x0080009f, @@ -1116,6 +1147,10 @@ static void aspeed_ast2700_scu_reset(DeviceState *de= v) if (s->ssp_cpuid > 0) { arm_set_cpu_off(s->ssp_cpuid); } + + if (s->tsp_cpuid > 0) { + arm_set_cpu_off(s->tsp_cpuid); + } } =20 static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *dat= a) --=20 2.43.0