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The 'x-' prefix indicates that the emulation is still in an "experimental" state as far as QEMU is concerned; the documentation describes what "experimental" means for the user and what parts are not yet implemented. We do not make 'gic-version=3Dmax' enable GICv5 here because: * the GICv5 architectural spec is still at the EAC level and could have minor changes between now and its final version; only users who specifically want to start working with the GICv5 should select it * QEMU's implementation here is still not fully featured, and selecting it instead of GICv3 will mean losing functionality such as MSIs * the GICv5 is not backwards compatible with the GICv3/GICv4 for system software, so silently "upgrading" an existing command line to GICv5 is just going to break existing guest kernels The last one in particular suggests that even when the emulation moves out of "experimental" status we will probably not want to change "max". Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- docs/system/arm/virt.rst | 19 +++++++++++++++++++ hw/arm/virt.c | 11 ++++++++--- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index f8148b5dcf..e38c567279 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -161,6 +161,25 @@ gic-version GICv3. This allows up to 512 CPUs. ``4`` GICv4. Requires ``virtualization`` to be ``on``; allows up to 317 CPUs. + ``x-5`` + GICv5 (experimental). This is an experimental emulation of the GICv5, + based on the EAC release of the GICv5 architecture specification. + Experimental means: + + - guest-visible behaviour may change when the final version of + the specification is released and QEMU implements it + - migration support is not yet implemented + - the GICv5 is not exposed to the guest via ACPI tables, only via DTB + - the way the interrupt controller is exposed to the guest and the + command line syntax for enabling it may change + + The current implementation supports only an EL1 guest (no EL2 or + EL3 and no Realm support), and does not implement the ITS (no + MSI support). + + Note that as the GICv5 is an Armv9 feature, enabling it will + automatically disable support for AArch32 at all exception levels + except for EL0 (userspace). ``host`` Use the same GIC version the host provides, when using KVM ``max`` diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 1c684b59b4..ca95cc9f73 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3195,6 +3195,9 @@ static char *virt_get_gic_version(Object *obj, Error = **errp) const char *val; =20 switch (vms->gic_version) { + case VIRT_GIC_VERSION_5: + val =3D "x-5"; + break; case VIRT_GIC_VERSION_4: val =3D "4"; break; @@ -3212,7 +3215,9 @@ static void virt_set_gic_version(Object *obj, const c= har *value, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - if (!strcmp(value, "4")) { + if (!strcmp(value, "x-5")) { + vms->gic_version =3D VIRT_GIC_VERSION_5; + } else if (!strcmp(value, "4")) { vms->gic_version =3D VIRT_GIC_VERSION_4; } else if (!strcmp(value, "3")) { vms->gic_version =3D VIRT_GIC_VERSION_3; @@ -3224,7 +3229,7 @@ static void virt_set_gic_version(Object *obj, const c= har *value, Error **errp) vms->gic_version =3D VIRT_GIC_VERSION_MAX; /* Will probe later */ } else { error_setg(errp, "Invalid gic-version value"); - error_append_hint(errp, "Valid values are 2, 3, 4, host, and max.\= n"); + error_append_hint(errp, "Valid values are 2, 3, 4, x-5, host, and = max.\n"); } } =20 @@ -3792,7 +3797,7 @@ static void virt_machine_class_init(ObjectClass *oc, = const void *data) virt_set_gic_version); object_class_property_set_description(oc, "gic-version", "Set GIC version. " - "Valid values are 2, 3, 4, host = and max"); + "Valid values are 2, 3, 4, x-5, = host and max"); =20 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_io= mmu); object_class_property_set_description(oc, "iommu", --=20 2.43.0