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GICv5 will be different to both. Refactor into create_gicv2() and create_gicv3(). Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/arm/virt.c | 137 ++++++++++++++++++++++++++++++-------------------- 1 file changed, 82 insertions(+), 55 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ec6e49099a..3d19eb0fee 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -863,26 +863,58 @@ static void gic_connect_ppis(VirtMachineState *vms) } } =20 -static void create_gic(VirtMachineState *vms, MemoryRegion *mem) +static void create_gicv2(VirtMachineState *vms, MemoryRegion *mem) +{ + MachineState *ms =3D MACHINE(vms); + /* We create a standalone GIC */ + SysBusDevice *gicbusdev; + unsigned int smp_cpus =3D ms->smp.cpus; + + if (kvm_enabled() && vms->virt) { + error_report("KVM EL2 is only supported with in-kernel GICv3"); + exit(1); + } + + vms->gic =3D qdev_new(gic_class_name()); + qdev_prop_set_uint32(vms->gic, "revision", 2); + qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); + /* + * Note that the num-irq property counts both internal and external + * interrupts; there are always 32 of the former (mandated by GIC spec= ). + */ + qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); + if (!kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); + qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", vms->= virt); + } + + gicbusdev =3D SYS_BUS_DEVICE(vms->gic); + sysbus_realize_and_unref(gicbusdev, &error_fatal); + sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); + sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); + if (vms->virt) { + sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); + sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); + } + + gic_connect_ppis(vms); + + fdt_add_gic_node(vms); +} + +static void create_gicv3(VirtMachineState *vms, MemoryRegion *mem) { MachineState *ms =3D MACHINE(vms); /* We create a standalone GIC */ SysBusDevice *gicbusdev; - const char *gictype; unsigned int smp_cpus =3D ms->smp.cpus; uint32_t nb_redist_regions =3D 0; int revision; - - if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { - gictype =3D gic_class_name(); - } else { - gictype =3D gicv3_class_name(); - } + QList *redist_region_count; + uint32_t redist0_capacity =3D virt_redist_capacity(vms, VIRT_GIC_REDIS= T); + uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); =20 switch (vms->gic_version) { - case VIRT_GIC_VERSION_2: - revision =3D 2; - break; case VIRT_GIC_VERSION_3: revision =3D 3; break; @@ -899,10 +931,11 @@ static void create_gic(VirtMachineState *vms, MemoryR= egion *mem) exit(1); } =20 - vms->gic =3D qdev_new(gictype); + vms->gic =3D qdev_new(gicv3_class_name()); qdev_prop_set_uint32(vms->gic, "revision", revision); qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); - /* Note that the num-irq property counts both internal and external + /* + * Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); @@ -910,40 +943,28 @@ static void create_gic(VirtMachineState *vms, MemoryR= egion *mem) qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); } =20 - if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { - QList *redist_region_count; - uint32_t redist0_capacity =3D virt_redist_capacity(vms, VIRT_GIC_R= EDIST); - uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); + nb_redist_regions =3D virt_gicv3_redist_region_count(vms); =20 - nb_redist_regions =3D virt_gicv3_redist_region_count(vms); + redist_region_count =3D qlist_new(); + qlist_append_int(redist_region_count, redist0_count); + if (nb_redist_regions =3D=3D 2) { + uint32_t redist1_capacity =3D + virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); =20 - redist_region_count =3D qlist_new(); - qlist_append_int(redist_region_count, redist0_count); - if (nb_redist_regions =3D=3D 2) { - uint32_t redist1_capacity =3D - virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); + qlist_append_int(redist_region_count, + MIN(smp_cpus - redist0_count, redist1_capacity)); + } + qdev_prop_set_array(vms->gic, "redist-region-count", redist_region_cou= nt); =20 - qlist_append_int(redist_region_count, - MIN(smp_cpus - redist0_count, redist1_capacity)); - } - qdev_prop_set_array(vms->gic, "redist-region-count", - redist_region_count); - - if (!kvm_irqchip_in_kernel()) { - if (vms->tcg_its) { - object_property_set_link(OBJECT(vms->gic), "sysmem", - OBJECT(mem), &error_fatal); - qdev_prop_set_bit(vms->gic, "has-lpi", true); - } - } else if (vms->virt) { - qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id", - ARCH_GIC_MAINT_IRQ); - } - } else { - if (!kvm_irqchip_in_kernel()) { - qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", - vms->virt); + if (!kvm_irqchip_in_kernel()) { + if (vms->tcg_its) { + object_property_set_link(OBJECT(vms->gic), "sysmem", OBJECT(me= m), + &error_fatal); + qdev_prop_set_bit(vms->gic, "has-lpi", true); } + } else if (vms->virt) { + qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id", + ARCH_GIC_MAINT_IRQ); } =20 if (gicv3_nmi_present(vms)) { @@ -953,18 +974,9 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) gicbusdev =3D SYS_BUS_DEVICE(vms->gic); sysbus_realize_and_unref(gicbusdev, &error_fatal); sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); - if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { - sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); - if (nb_redist_regions =3D=3D 2) { - sysbus_mmio_map(gicbusdev, 2, - vms->memmap[VIRT_HIGH_GIC_REDIST2].base); - } - } else { - sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); - if (vms->virt) { - sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); - sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); - } + sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); + if (nb_redist_regions =3D=3D 2) { + sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].b= ase); } =20 gic_connect_ppis(vms); @@ -972,6 +984,21 @@ static void create_gic(VirtMachineState *vms, MemoryRe= gion *mem) fdt_add_gic_node(vms); } =20 +static void create_gic(VirtMachineState *vms, MemoryRegion *mem) +{ + switch (vms->gic_version) { + case VIRT_GIC_VERSION_2: + create_gicv2(vms, mem); + break; + case VIRT_GIC_VERSION_3: + case VIRT_GIC_VERSION_4: + create_gicv3(vms, mem); + break; + default: + g_assert_not_reached(); + } +} + static void create_msi_controller(VirtMachineState *vms) { switch (vms->msi_controller) { --=20 2.43.0