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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483a9b21ceasm200155625e9.0.2026.02.23.09.02.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 09:02:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771866179; x=1772470979; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dBwNvGbCOD54Qlf9QuiSd9BdBjRvsnVDp48/gZ6uiLM=; b=pwXlsR79QEYIBIQUZ0lY5VeZoVYy6/UlHIaTQxyyowiyiwiafTd/Mx3GCDGPMIoKvv xTsuYNL61HSRLhIj9e2Cn+bkwynNTTghgGxDAZyIg1kzxGa2BCGq52EsAPm50NkCX4R/ zErqfIINkLdVs3xRKoHRWZH0I1BJ7TlPNhDNV0NhjDqBTZQ/Tvixb3bVXTe1N50i8nSx /udrb+LijrGlCTb4fSTg0FbgJxGpXAzTdC1xcQEJkrVfyQTan3co5tKK0Bj73+CEOTt3 Fet4QwTM69AhJmKgVqRX25qTvlahu8zQ1IvfOT/XDO3LOBJ3EvMzfm/OVTtv8Giv1/6W VxeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771866179; x=1772470979; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=dBwNvGbCOD54Qlf9QuiSd9BdBjRvsnVDp48/gZ6uiLM=; b=FpVKGAQVkgK94LQbwNA4LhL4trwhh3BF+emJc6mitkW0vLQYVB9+u7SSu2bMTCiGav FFt6hpMdGnhrMj9moZl45bAPPkQO2NFFu1IfXjDCVi/OE76TY8e/7jiPnJSwksa5+DHn fEExInIKOnHOV+R40nVXweqs8MdE9Br9h3gq0qXmitxRFZu11eqaJMXEaY4kUj4TlwFk +vq7bs/L8YFxTBRfySrnjflNSMYjnEogFBYTbdrP4cU7Is2YFw3BBkAVqkjsUb50zxon Eju0VM5IUKASYBcNw3CWDm2fYGdBKSdgwQJ0UnsRyu+QfPxZu5ojhT8A1tChYhMc5iKt STaQ== X-Forwarded-Encrypted: i=1; AJvYcCUArSKbNkkWpC2ewBh8THTS7QS0RkXp6acfyH1b/0fJhZYYL+2zx7hRDusf3RrFTbrgMVDbiJubnmb6@nongnu.org X-Gm-Message-State: AOJu0YyxnyQoW1A5xXIIoyRWPKzzJ5wD+bOWGuSwK1O7gbGNlqfnP2LB 7YP+ZcW7Sh/MGOOHuYmQpN8kppwT1otwUH9B6DapQDjdTX6yyG6lkSJaapaZVbLzLhU= X-Gm-Gg: AZuq6aKMUnYWqZUqBeAQqIj0Wag1A//2DAZiWBcA8AfcY0hIyCudNqdamdXyU6kx7ub KAtgWbfzqKRgDbvORhCx26OrO5lyRZg+0QAN/B+BKZqvZ5OnDxrvHrZIgeiTtsfWkY21ecwvGpQ Q6iCdhh6ZxT779ABHqg7pE/RRB27Vj9C7MTYLdzjQ1Jd0NPr7AoDxj9rFNm9QLKYFT2WsQU/j9s 85HcAm8mO+MHSp6LEOQpln02pXFnrxlFa01S38Saw83eeXtBsx9xmDR3vczL80GzAyIQTvoitST KEjZI/Mim4eKcMmhlNXrXYaNLYeLFR+Rft5+aGpAbsq5WvpYRMyoGlV88h2ql2sHqW79gLe21Z5 H0bCSbprIhqnfqizkT6FKcmi3GVF7WAcHc0mQDFaqDhhYay27+ckiafLZaJU1VGOleRs2zMVar1 tN+PJI7a5ubhqsJRQrqHNLx32sCdygsVY3IXRT2CEhOELsSzEe8hLxVcRORdloeu+jwA/bXhT3u eF/eX/KehvNndKj+QvXvnBKIOYPZR4= X-Received: by 2002:a05:600c:a00d:b0:480:690e:f14a with SMTP id 5b1f17b1804b1-483a95bf2f3mr162437875e9.14.1771866178908; Mon, 23 Feb 2026 09:02:58 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 39/65] target/arm: GICv5 cpuif: Implement PPI priority registers Date: Mon, 23 Feb 2026 17:01:46 +0000 Message-ID: <20260223170212.441276-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223170212.441276-1-peter.maydell@linaro.org> References: <20260223170212.441276-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_FILL_THIS_FORM_SHORT=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771866815700158500 Content-Type: text/plain; charset="utf-8" Implement the GICv5 registers which hold the priority of the PPIs. Each 64-bit register has the priority fields for 8 PPIs, so there are 16 registers in total. This would be a lot of duplication if we wrote it out statically in the array, so instead create each register via a loop in define_gicv5_cpuif_regs(). Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 2 ++ target/arm/tcg/gicv5-cpuif.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 915a225f8e..b97f659352 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -608,6 +608,8 @@ typedef struct CPUArchState { uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; uint64_t ppi_pend[GICV5_NUM_PPIS / 64]; uint64_t ppi_enable[GICV5_NUM_PPIS / 64]; + /* The PRIO regs have 1 byte per PPI, so 8 PPIs to a register */ + uint64_t ppi_priority[GICV5_NUM_PPIS / 8]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index c54e784dc4..60b495dd8f 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -225,6 +225,12 @@ static void gic_ppi_enable_write(CPUARMState *env, con= st ARMCPRegInfo *ri, raw_write(env, ri, value); } =20 +static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *r= i, + uint64_t value) +{ + raw_write(env, ri, value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -382,5 +388,22 @@ void define_gicv5_cpuif_regs(ARMCPU *cpu) { if (cpu_isar_feature(aa64_gcie, cpu)) { define_arm_cp_regs(cpu, gicv5_cpuif_reginfo); + + /* + * There are 16 ICC_PPI_PRIORITYR_EL1 regs, so define them + * programmatically rather than listing them all statically. + */ + for (int i =3D 0; i < 16; i++) { + g_autofree char *name =3D g_strdup_printf("ICC_PPI_PRIORITYR%d= _EL1", i); + ARMCPRegInfo ppi_prio =3D { + .name =3D name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, + .crm =3D 14 + (i >> 3), .opc2 =3D i & 7, + .access =3D PL1_RW, .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pri= ority[i]), + .writefn =3D gic_ppi_priority_write, .raw_writefn =3D raw_= write, + }; + define_one_arm_cp_reg(cpu, &ppi_prio); + } } } --=20 2.43.0