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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483a9b21ceasm200155625e9.0.2026.02.23.09.02.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 09:02:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771866177; x=1772470977; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=d/expR217T5l2ZpgIxw9igXVO7ZIf/mmczK8CZEhS9Q=; b=o2lWedMp5lMZpGjfZiKeFAMyr1kg+DTWcmp2R9F7sw27aEUXGUnAw9mCujtyAq5weX URv+YNSKCRoPDUkZIrh1XZiGqinTASul7Q4XoGDdr/i4YFBYG+1iV1QIfm+2+NXIZWtI wn719pv+nD6Bae8Bx6zn221fpeUXxDLVnJEVpPj8xzs5He7uNGpNJ2clcM6r9Y+fhV7i SbETqLbqJhpWev4qm42prIC6oK9j2x4G79oXru0UBNJzWzcCpVUzMOKx9ZIbP5HnGsuL zvRhRc5A8hQBU64NDp+O2ohMDANTqTqSGX8aYF/I8LpKI8ZqFrZ7zbdKpR+Dt3dtvOA4 aYmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771866177; x=1772470977; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=d/expR217T5l2ZpgIxw9igXVO7ZIf/mmczK8CZEhS9Q=; b=RQ4SwYOihbF/TxWbeBF3D0EK9oxKmw8Ok1yrUBmHpAxLb4qShdPL5rHTfXiHE3Y6sh JJ+t4XNI0m3FmxFxhA9lD86tE8F8Li6jmgFui014DZ/g4EknNcrYfMfDydlaKl//bI1V tEHEZkTiQ2jmAIiBHzo+loNZ+mNVraxe2KPXVtH9uOzRDUleRULDxHiMb3K1tq6MgAOw /254TBI2yYAnxcLOSKpAaxHzGNM0ZsnrrPLVjjXdnABYM8U/y/lqUuR/pX80BPuRQUJk kFfhomQe3ktT7ADgdlb4GmBhJOKfqDIJ1EOeJmGyOGtUzf2kAZ8y+l+kJV6XXDDkj0Jt Fcig== X-Forwarded-Encrypted: i=1; AJvYcCXW+sByiVCI7n2uqPhnC9mL60IFGUCU6jVFrMX1jwsePo8CD9u10Px4gOlixha/f9OzE6MYpLobULVr@nongnu.org X-Gm-Message-State: AOJu0YyyzM0iAZbHq00nNE0KOLKRkF1Eib+IGovuzf610VAG0/IWDdTL DIr/+QIO6VJv3tYjN4PezgMiOUJDrtGoNjUuS/hq+pOVopBelMnqoHLBt/sixQ4aQnM= X-Gm-Gg: AZuq6aKYiLMjbuFd7WE494h47MQ9qfm1mgR1vWhMiDNX+n4hzllvp1xpgH/LX6PrkZD WaDImFa4KjWiBpo7rlx1j8+pNhxtUzeAORmjAX931zz6gUZ+DB5idOeqUskT9UVb1x4eSGuPBZn ifo/cTCEt2Aq0JCVHJtjYGOAVUCvnLtvJyq23M+3rIgL3juPjBeiYYstvcE2HN6jaWuA27/Cgvz Huu9nXvrv/9U5LpftjFoagaNj/k1+pCUMONYWcjBcWJ2EVndqjQLlghrptr89PnEnytoTCBbY4y BPctQ8amHKLKvz/fIujc9omhVeoQXTyHLtlyow8rar6MYuuW/JnaJq/XTWbz55RchzQQzMZhh6F cODLimfaSzDwRK0BPJnGQYvZ78RrmTg25Ue023WnVGSs/lm67rke6Lmzesb1OWKv53LKkLsrbFv HuppQNbJvvAl5KSw5UpaS3lYhTGk9hJaHtOUqZlIqwD69x0UXxdJL9bU1JdpIREswKlbNmsKPP1 XL+GXS1d0pP6d7+S9vzmL0fedS2+V8= X-Received: by 2002:a05:600c:6217:b0:471:14af:c715 with SMTP id 5b1f17b1804b1-483a95eb550mr137670155e9.3.1771866177201; Mon, 23 Feb 2026 09:02:57 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 38/65] target/arm: GICv5 cpuif: Implement PPI enable register Date: Mon, 23 Feb 2026 17:01:45 +0000 Message-ID: <20260223170212.441276-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223170212.441276-1-peter.maydell@linaro.org> References: <20260223170212.441276-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771866717163158500 Content-Type: text/plain; charset="utf-8" Implement the GICv5 register which holds the enable state of PPIs: ICC_PPI_ENABLER_EL1. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 980abda3ca..915a225f8e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -607,6 +607,7 @@ typedef struct CPUArchState { uint64_t ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; uint64_t ppi_pend[GICV5_NUM_PPIS / 64]; + uint64_t ppi_enable[GICV5_NUM_PPIS / 64]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 4647fd40ba..c54e784dc4 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -219,6 +219,12 @@ static void gic_ppi_spend_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, raw_write(env, ri, old | value); } =20 +static void gic_ppi_enable_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -334,6 +340,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), .resetvalue =3D PPI_HMR1_RESET, }, + { .name =3D "ICC_PPI_ENABLER0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 6, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_enable[0]), + .writefn =3D gic_ppi_enable_write, + }, + { .name =3D "ICC_PPI_ENABLER1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 10, .opc2 =3D 7, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_enable[1]), + .writefn =3D gic_ppi_enable_write, + }, { .name =3D "ICC_PPI_CPENDR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 4, .access =3D PL1_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO= _RAW, --=20 2.43.0