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The pending state is read-only for PPIs where the handling mode is Edge. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/cpu.h | 1 + target/arm/tcg/gicv5-cpuif.c | 44 ++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4574f7005d..980abda3ca 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -606,6 +606,7 @@ typedef struct CPUArchState { /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register= */ uint64_t ppi_active[GICV5_NUM_PPIS / 64]; uint64_t ppi_hm[GICV5_NUM_PPIS / 64]; + uint64_t ppi_pend[GICV5_NUM_PPIS / 64]; } gicv5_cpuif; =20 struct { diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 6fbc962131..4647fd40ba 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -199,6 +199,26 @@ static void gic_ppi_sactive_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, raw_write(env, ri, old | value); } =20 +static void gic_ppi_cpend_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t old =3D raw_read(env, ri); + /* If ICC_PPI_HMR_EL1[n].HM is 1, PEND bits are RO */ + uint64_t hm =3D env->gicv5_cpuif.ppi_hm[ri->opc2 & 1]; + value &=3D ~hm; + raw_write(env, ri, old & ~value); +} + +static void gic_ppi_spend_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t old =3D raw_read(env, ri); + /* If ICC_PPI_HMR_EL1[n].HM is 1, PEND bits are RO */ + uint64_t hm =3D env->gicv5_cpuif.ppi_hm[ri->opc2 & 1]; + value &=3D ~hm; + raw_write(env, ri, old | value); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -314,6 +334,30 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_hm[1]), .resetvalue =3D PPI_HMR1_RESET, }, + { .name =3D "ICC_PPI_CPENDR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO= _RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), + .writefn =3D gic_ppi_cpend_write, + }, + { .name =3D "ICC_PPI_CPENDR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 5, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO= _RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), + .writefn =3D gic_ppi_cpend_write, + }, + { .name =3D "ICC_PPI_SPENDR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 6, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pend[0]), + .writefn =3D gic_ppi_spend_write, + }, + { .name =3D "ICC_PPI_SPENDR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 13, .opc2 =3D 7, + .access =3D PL1_RW, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]), + .writefn =3D gic_ppi_spend_write, + }, }; =20 void define_gicv5_cpuif_regs(ARMCPU *cpu) --=20 2.43.0