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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483a9b21ceasm200155625e9.0.2026.02.23.09.02.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 09:02:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771866137; x=1772470937; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QC2jCmUmDa22pq2M5e1IUAC/xLyvzU6A+/CopHKbGoc=; b=r+jNM1/qTLbNKGTBa1+KkH5GxpFsJRaVb6+AKqUzF1tDdeegUVkPgHyDGLHyVhKjyF CKvuOTJYjmsjLZ/SlKSwwLmje1E7bdyNdUK/axWINDiIzKQEV91POGAgYZXAdz2g4dDQ K8lTsvH8jOMHSpCROlPO7H3sHRjwX+9cZWXmByTBkttxmlzIZ5PSBeYB8T5BRcz6eFJE O3th+LeyaoAPR27Dg4N2sW1RaQ8nJUXhId0Pc5q3JrdFh+PP0KnjrcmSte6CvMfgM4Cd ciEQP+XREEsTYj698PMlYiDYooiRtbT84GLcAHEbdbejgBhnAVi4BbGnG8NuSsi+PA92 IvSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771866137; x=1772470937; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=QC2jCmUmDa22pq2M5e1IUAC/xLyvzU6A+/CopHKbGoc=; b=U8CjFi3d/he0RjIRTEz54zz2H9TTx8UZmjL/LYKYRVMGshTktMmIa3jqRv4BtwZBl3 8T/xG1zYTGON82gTXdV9X+CJAq60wwGYBSlYfDFKYfuEQPAA1UEDt6/Rv/1O1BmwUKLw bGZfd56zMO69WJ6ldK2/YAzMM5L/qpKVAzCeODrUp5Z/6kHVOAkloNhP3BVM0jYlQora J+CDiyT3Q9FM16e7SDFNegQsNLGW5DPlvuV2DLSD2LgIitC1EPGo92K1oKMmo5BR6lmS KFCthJ6bnsgk/WE2mFSQgGRmNwXo+U8h4+5phL9tcsAJZsNWr7v7XvIy24Bf54WCe7bD d2vA== X-Forwarded-Encrypted: i=1; AJvYcCUHtkhb80Ahq9f31w6HJTvx9qI6lsOozTbfMqYJI1XLlRwLP/djx7Fnkvn0GUzgnnudTnP6zwow5Wco@nongnu.org X-Gm-Message-State: AOJu0YyQfn3EuLufMlrfZIno+ND4gcNMpRlGT7mXRivzgfxSaZ3e0rpd 5AJMgqUFessLnv+DJGaqsYK8h7sftUzqxH5u2BgOVbRKgavBBnY3s1hY0s+IsLqNdad9dyGbqr7 e/tvhLhE= X-Gm-Gg: AZuq6aKxj0pzX3y5g9yLedbbg8vF0HXuIOGR/AGYZx7vV/133psC/SVsi6ddBj6OV0A I9OuzRlUw2e7OX481rq3aj8DrAzOwOFcjDZCkBBjVbsl4YR7q4payAhalf7xZTJ9+TBEbmi3ugk ix341r9visLYygUllD3oWSMz9a0dcfNweMlo1PDGYDy1HCy+plcP5MdAPmzRtw8kAHmXUWXqVXP CJgoG0tGfq3xJ4vfI5vHVPF8tXoPx+8jUzrT5lcI2or5Eapk5TiWsfDRbs3zoa1dAczrVgS3yu+ JlVVftTHd5eCLilv7qM4hgjRQQSykA2ndPBl+cKMW3iT5lh0EBWA3whl33pMA7+HHHB/kl8yXnV puZAqJCgd4QXWdWWZW91aAj8gyzjs/nUIPAESOR97TrE6Oa2jpz7cqjhtEjbz9SxI7Ljot2wUSK 0cU+uaxrn20mBEnNf5fEwt8YLhTxekwTsbBtyZLwUSPfrcNUe0Hd9yfNTLGZzO9i//tbAaex/BZ c39S2q/oVMlT46ZR8cd03HqhjOe3R0= X-Received: by 2002:a05:600c:8b27:b0:480:69ae:f0e9 with SMTP id 5b1f17b1804b1-483a95eb3bamr185842405e9.16.1771866136485; Mon, 23 Feb 2026 09:02:16 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/65] hw/intc: Skeleton of GICv5 IRS classes Date: Mon, 23 Feb 2026 17:01:09 +0000 Message-ID: <20260223170212.441276-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223170212.441276-1-peter.maydell@linaro.org> References: <20260223170212.441276-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771866234265158500 Content-Type: text/plain; charset="utf-8" This commit adds the skeleton of the classes for the GICv5 IRS (Interrupt Routing Service). Since the IRS is the main (and only non-optional) part of the GICv5 outside the CPU, we call it simply "GICv5", in line with how we've handled the GICv3. Since we're definitely going to need to have support for KVM VMs where we present the guest with a GICv5, we use the same split between an abstract "common" and a concrete specific-to-TCG child class that we have for the various GICv3 components. This avoids having to refactor out the base class later. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/Kconfig | 4 +++ hw/intc/arm_gicv5.c | 39 ++++++++++++++++++++++++++++++ hw/intc/arm_gicv5_common.c | 31 ++++++++++++++++++++++++ hw/intc/meson.build | 4 +++ include/hw/intc/arm_gicv5.h | 32 ++++++++++++++++++++++++ include/hw/intc/arm_gicv5_common.h | 31 ++++++++++++++++++++++++ 6 files changed, 141 insertions(+) create mode 100644 hw/intc/arm_gicv5.c create mode 100644 hw/intc/arm_gicv5_common.c create mode 100644 include/hw/intc/arm_gicv5.h create mode 100644 include/hw/intc/arm_gicv5_common.h diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 9f456d7e43..a3241fc1eb 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -35,6 +35,10 @@ config ARM_GIC_KVM bool depends on ARM_GIC && KVM =20 +config ARM_GICV5 + bool + select MSI_NONBROKEN + config XICS bool =20 diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c new file mode 100644 index 0000000000..f9dab710d3 --- /dev/null +++ b/hw/intc/arm_gicv5.c @@ -0,0 +1,39 @@ +/* + * ARM GICv5 emulation: Interrupt Routing Service (IRS) + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/intc/arm_gicv5.h" + +OBJECT_DEFINE_TYPE(GICv5, gicv5, ARM_GICV5, ARM_GICV5_COMMON) + +static void gicv5_reset_hold(Object *obj, ResetType type) +{ + GICv5 *s =3D ARM_GICV5(obj); + GICv5Class *c =3D ARM_GICV5_GET_CLASS(s); + + if (c->parent_phases.hold) { + c->parent_phases.hold(obj, type); + } +} + +static void gicv5_init(Object *obj) +{ +} + +static void gicv5_finalize(Object *obj) +{ +} + +static void gicv5_class_init(ObjectClass *oc, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(oc); + GICv5Class *gc =3D ARM_GICV5_CLASS(oc); + + resettable_class_set_parent_phases(rc, NULL, gicv5_reset_hold, NULL, + &gc->parent_phases); +} diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c new file mode 100644 index 0000000000..b0194f7f26 --- /dev/null +++ b/hw/intc/arm_gicv5_common.c @@ -0,0 +1,31 @@ +/* + * Common base class for GICv5 IRS + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/intc/arm_gicv5_common.h" + +OBJECT_DEFINE_ABSTRACT_TYPE(GICv5Common, gicv5_common, ARM_GICV5_COMMON, S= YS_BUS_DEVICE) + +static void gicv5_common_reset_hold(Object *obj, ResetType type) +{ +} + +static void gicv5_common_init(Object *obj) +{ +} + +static void gicv5_common_finalize(Object *obj) +{ +} + +static void gicv5_common_class_init(ObjectClass *oc, const void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(oc); + + rc->phases.hold =3D gicv5_common_reset_hold; +} diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 96742df090..e4ddc5107f 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -12,6 +12,10 @@ system_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files( 'arm_gicv3_its.c', 'arm_gicv3_redist.c', )) +system_ss.add(when: 'CONFIG_ARM_GICV5', if_true: files( + 'arm_gicv5_common.c', + 'arm_gicv5.c', +)) system_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-= a10-pic.c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c')) system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_intc.c')) diff --git a/include/hw/intc/arm_gicv5.h b/include/hw/intc/arm_gicv5.h new file mode 100644 index 0000000000..3cd9652f6f --- /dev/null +++ b/include/hw/intc/arm_gicv5.h @@ -0,0 +1,32 @@ +/* + * ARM GICv5 emulation: Interrupt Routing Service (IRS) + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_INTC_ARM_GICV5_H +#define HW_INTC_ARM_GICV5_H + +#include "qom/object.h" +#include "hw/core/sysbus.h" +#include "hw/intc/arm_gicv5_common.h" + +#define TYPE_ARM_GICV5 "arm-gicv5" + +OBJECT_DECLARE_TYPE(GICv5, GICv5Class, ARM_GICV5) + +/* + * This class is for TCG-specific state for the GICv5. + */ +struct GICv5 { + GICv5Common parent_obj; +}; + +struct GICv5Class { + GICv5CommonClass parent_class; + ResettablePhases parent_phases; +}; + +#endif diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h new file mode 100644 index 0000000000..d2243c7660 --- /dev/null +++ b/include/hw/intc/arm_gicv5_common.h @@ -0,0 +1,31 @@ +/* + * Common base class for GICv5 IRS + * + * Copyright (c) 2025 Linaro Limited + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_INTC_ARM_GICV5_COMMON_H +#define HW_INTC_ARM_GICV5_COMMON_H + +#include "qom/object.h" +#include "hw/core/sysbus.h" + +#define TYPE_ARM_GICV5_COMMON "arm-gicv5-common" + +OBJECT_DECLARE_TYPE(GICv5Common, GICv5CommonClass, ARM_GICV5_COMMON) + +/* + * This class is for common state that will eventually be shared + * between TCG and KVM implementations of the GICv5. + */ +struct GICv5Common { + SysBusDevice parent_obj; +}; + +struct GICv5CommonClass { + SysBusDeviceClass parent_class; +}; + +#endif --=20 2.43.0