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The way these work is that the guest writes the ID of the interrupt it wants to configure to IRS_SPI_SELR, and then it can read and write the trigger mode of that SPI via IRS_SPI_CFGR and the domain via IRS_SPI_DOMAINR. IRS_SPI_STATUSR has a bit to indicate whether the SPI is valid, and the usual IDLE bit to allow for non-instantaneous updates (which QEMU doesn't do). Since the only domain which can configure the domain of an SPI is EL3 and our initial implementation is NS-only, technically the DOMAINR handling is unused code. However it is straightforward, being almost the same as the CFGR handling, and we'll need it later on. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 68 ++++++++++++++++++++++++++++++ hw/intc/arm_gicv5_common.c | 9 ++++ include/hw/intc/arm_gicv5_common.h | 1 + 3 files changed, 78 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 51b25775c4..9f4d44f975 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -310,6 +310,22 @@ FIELD(ICSR, HM, 5, 1) FIELD(ICSR, PRIORITY, 11, 5) FIELD(ICSR, IAFFID, 32, 16) =20 +static GICv5SPIState *spi_for_selr(GICv5Common *cs, GICv5Domain domain) +{ + /* + * If the IRS_SPI_SELR value specifies an SPI that can be managed in + * this domain, return a pointer to its GICv5SPIState; otherwise + * return NULL. + */ + uint32_t id =3D FIELD_EX32(cs->irs_spi_selr[domain], IRS_SPI_SELR, ID); + GICv5SPIState *spi =3D gicv5_raw_spi_state(cs, id); + + if (spi && (domain =3D=3D GICV5_ID_EL3 || domain =3D=3D spi->domain)) { + return spi; + } + return NULL; +} + static MemTxAttrs irs_txattrs(GICv5Common *cs, GICv5Domain domain) { /* @@ -970,6 +986,38 @@ static bool config_readl(GICv5 *s, GICv5Domain domain,= hwaddr offset, case A_IRS_IST_CFGR: *data =3D cs->irs_ist_cfgr[domain]; return true; + + case A_IRS_SPI_STATUSR: + /* + * QEMU writes to IRS_SPI_{CFGR,DOMAINR,SELR,VMR} take effect + * instantaneously, so the guest can never see the IDLE bit as 0. + */ + v =3D FIELD_DP32(v, IRS_SPI_STATUSR, V, + spi_for_selr(cs, domain) !=3D NULL); + v =3D FIELD_DP32(v, IRS_SPI_STATUSR, IDLE, 1); + *data =3D v; + return true; + + case A_IRS_SPI_CFGR: + { + GICv5SPIState *spi =3D spi_for_selr(cs, domain); + + if (spi) { + v =3D FIELD_DP32(v, IRS_SPI_CFGR, TM, spi->tm); + } + *data =3D v; + return true; + } + case A_IRS_SPI_DOMAINR: + if (domain =3D=3D GICV5_ID_EL3) { + /* This is RAZ/WI except for the EL3 domain */ + GICv5SPIState *spi =3D spi_for_selr(cs, domain); + if (spi) { + v =3D FIELD_DP32(v, IRS_SPI_DOMAINR, DOMAIN, spi->domain); + } + } + *data =3D v; + return true; } return false; } @@ -1000,6 +1048,26 @@ static bool config_writel(GICv5 *s, GICv5Domain doma= in, hwaddr offset, case A_IRS_MAP_L2_ISTR: irs_map_l2_istr_write(s, domain, data); return true; + case A_IRS_SPI_SELR: + cs->irs_spi_selr[domain] =3D data; + return true; + case A_IRS_SPI_CFGR: + { + GICv5SPIState *spi =3D spi_for_selr(cs, domain); + if (spi) { + spi->tm =3D FIELD_EX32(data, IRS_SPI_CFGR, TM); + } + return true; + } + case A_IRS_SPI_DOMAINR: + if (domain =3D=3D GICV5_ID_EL3) { + /* this is RAZ/WI except for the EL3 domain */ + GICv5SPIState *spi =3D spi_for_selr(cs, domain); + if (spi) { + spi->domain =3D FIELD_EX32(data, IRS_SPI_DOMAINR, DOMAIN); + } + } + return true; } return false; } diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c index 8cca3a9764..e0d954f3c6 100644 --- a/hw/intc/arm_gicv5_common.c +++ b/hw/intc/arm_gicv5_common.c @@ -94,6 +94,15 @@ static void gicv5_common_reset_hold(Object *obj, ResetTy= pe type) cs->spi[i].domain =3D mp_domain; } } + + for (int i =3D 0; i < NUM_GICV5_DOMAINS; i++) { + /* + * We reset irs_spi_selr to an invalid value so that our reset + * value for IRS_SPI_STATUSR.V is correctly 0. The guest + * can never read IRS_SPI_SELR directly. + */ + cs->irs_spi_selr[i] =3D cs->spi_base + cs->spi_irs_range; + } } =20 static void gicv5_common_init(Object *obj) diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index 1a1d360c68..5490fdaf8b 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -84,6 +84,7 @@ struct GICv5Common { =20 uint64_t irs_ist_baser[NUM_GICV5_DOMAINS]; uint32_t irs_ist_cfgr[NUM_GICV5_DOMAINS]; + uint32_t irs_spi_selr[NUM_GICV5_DOMAINS]; =20 /* * Pointer to an array of state information for the SPIs. --=20 2.43.0