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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483a9b21ceasm200155625e9.0.2026.02.23.09.02.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 09:02:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771866162; x=1772470962; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JwcHn/CjQkHfmGibiCn3O/oR20qiscSiOE7DixcXUno=; b=lUaBDTDqUrWwC0ckv1WCsTRChyfWaIblI2vrbWiz2PdUdP419gKsPb3FjdtZKSgm+N pRMsOwC0wBULgjaQ6hkVARDcGrqev4AcIAno+oDfsZRHMjiXLorebPYRpMX/nNeJayED tE1irGwSEKSN9t8OotP61Q0lKHQJDmDJn93/Jhs2Kj6QVkrXgnaufMCAZ37ghIZEyH3p dYb/V1l3e8v9v4Dfg3YhkuOCp6E9BM0SzLBa889bhc5g/LRxf08m8tzxE1kPW+xrSMPw fxkbW7meoxfOfx+8ioCTnvtbZhCTgsxQBubKZcjnnc5pBFJDWZU0LMZk1Lr77h1PWDzD qdJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771866162; x=1772470962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=JwcHn/CjQkHfmGibiCn3O/oR20qiscSiOE7DixcXUno=; b=eGWQR3cZ2vwb2Z/j859vTk1pCJDImcgI2c/2KxP9uLVa9CviwdXdRy6M7J9Z8hfv80 vfoXxy76mLuwfAm1upcrgrntKSpHR0cURwq4Ah7ESWn8sLWqy8ikUqVXSJDngAJLt+Dq JzFIaEdxhldO/BrBAvvcvkonrfeXsER3AsE1Q8fnNOwHAsQiF8x/m2KB2P9kBIIAMZmf CZbP2E/maTW8Xl6fqqr5KrtYUJx2Wt7lYx47c1rtq+sFU7/oZ5tw1TJaTBghjyQUQjOL /MzNKq/wNSkU7/rH50tQKAMPlwaDMyBNXALQN8gHZdalJK42j+J4hq/+NhpVTIXSd6NT YE8g== X-Forwarded-Encrypted: i=1; AJvYcCVfV0154MIOqS+QxtE52z6vdWZoWN3UGax4WjAuxyZwOw1mRwMjp/EhWhowoJcr5YkhOHkZpNDosBIV@nongnu.org X-Gm-Message-State: AOJu0YwGytjlG+DCFycsnNCK/813OlmV/Ck0dQ027kWPod8xWYhr+Z2n SEeO4XtDvMRauCvcIf31zlzcErLhRYyHrpmxt5TOGe7J9McsCsM1LFgt0LR9LiZsNHQ= X-Gm-Gg: AZuq6aJ8/FHz7sM+nTXE1zrW6T2WMJSnt5zsIzE/JKloTOPD2wf84goXr6wmHZyf6W+ QH59QoD77eBBIFNOMUloeN/xkEsrNJ79qnmwjIadUxcBKpFSURvO6Z9t+ZqrviVpCMuGY2VRcbY 67RKPYLN7N5fJ+3JqyCaFaN9D9TzYDAZwoI61kxf4/qdnHemnyFI8UlPjlpYEgTZVX+I87YT4wz kpdlAmJtdkvX6aJSGOHg2SBt82kzZ7k/y66FJ2sAK445Ltb4KGg8TIiz2NTggiCvCbg50ZCuznq 6vclPQl+bhpqWunqrimE+m552wyqx8/iti5yd+MryciLnOxghIbDfM5xOSaPYmP0DI9+GouFUCO MOLM/fzqYLccedLQXTkBpsy3Bmb1ojGCidlABHuAbJ3PsubWKcdftUgZLZYbjqfUSzOffUgS3yg rIJhlqaROqjGoFdTUapseiCV5ljKk8rVVe5NBy+y4bRK2W8CMGEwjeh4EeJtJEHZxdom4SRtPjc ml33CwedClbMNnYoAuLfGLExZE9Lgw= X-Received: by 2002:a05:600c:3147:b0:477:6374:6347 with SMTP id 5b1f17b1804b1-483a962e3e2mr138417725e9.22.1771866161175; Mon, 23 Feb 2026 09:02:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 23/65] hw/intc/arm_gicv5: Make gicv5_set_* update SPI state Date: Mon, 23 Feb 2026 17:01:30 +0000 Message-ID: <20260223170212.441276-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223170212.441276-1-peter.maydell@linaro.org> References: <20260223170212.441276-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771866654888158500 Content-Type: text/plain; charset="utf-8" The GIC CD* insns that update interrupt state also work for SPIs. Instead of ignoring the GICV5_SPI type in gicv5_set_priority() and friends, update the state in our SPI state array. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv5.c | 59 ++++++++++++++++++++++++++++++ include/hw/intc/arm_gicv5_common.h | 40 ++++++++++++++++++++ 2 files changed, 99 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 3c6ef17573..4d99200122 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -478,6 +478,18 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, "priority of a virtual interrupt\n"); return; } + if (type =3D=3D GICV5_SPI) { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to s= et " + "priority of unreachable SPI %d\n", id); + return; + } + + spi->priority =3D priority; + return; + } if (type !=3D GICV5_LPI) { qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_priority: tried to set " "priority of bad interrupt type %d\n", type); @@ -508,6 +520,18 @@ void gicv5_set_enabled(GICv5Common *cs, uint32_t id, "enable state of a virtual interrupt\n"); return; } + if (type =3D=3D GICV5_SPI) { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to se= t " + "enable state of unreachable SPI %d\n", id); + return; + } + + spi->enabled =3D true; + return; + } if (type !=3D GICV5_LPI) { qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_enabled: tried to set " "enable state of bad interrupt type %d\n", type); @@ -538,6 +562,18 @@ void gicv5_set_pending(GICv5Common *cs, uint32_t id, "pending state of a virtual interrupt\n"); return; } + if (type =3D=3D GICV5_SPI) { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to se= t " + "pending state of unreachable SPI %d\n", id); + return; + } + + spi->pending =3D true; + return; + } if (type !=3D GICV5_LPI) { qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_pending: tried to set " "pending state of bad interrupt type %d\n", type); @@ -568,6 +604,17 @@ void gicv5_set_handling(GICv5Common *cs, uint32_t id, "handling mode of a virtual interrupt\n"); return; } + if (type =3D=3D GICV5_SPI) { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to s= et " + "priority of unreachable SPI %d\n", id); + } + + spi->hm =3D handling; + return; + } if (type !=3D GICV5_LPI) { qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_handling: tried to set " "handling mode of bad interrupt type %d\n", type); @@ -607,6 +654,18 @@ void gicv5_set_target(GICv5Common *cs, uint32_t id, ui= nt32_t iaffid, * IRM=3D1 the same as IRM=3D0. */ } + if (type =3D=3D GICV5_SPI) { + GICv5SPIState *spi =3D gicv5_spi_state(cs, id, domain); + + if (!spi) { + qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set= " + "target of unreachable SPI %d\n", id); + return; + } + + spi->iaffid =3D iaffid; + return; + } if (type !=3D GICV5_LPI) { qemu_log_mask(LOG_GUEST_ERROR, "gicv5_set_target: tried to set " "target of bad interrupt type %d\n", type); diff --git a/include/hw/intc/arm_gicv5_common.h b/include/hw/intc/arm_gicv5= _common.h index c29eab2951..1a1d360c68 100644 --- a/include/hw/intc/arm_gicv5_common.h +++ b/include/hw/intc/arm_gicv5_common.h @@ -191,4 +191,44 @@ static inline bool gicv5_domain_implemented(GICv5Commo= n *cs, GICv5Domain domain) */ const char *gicv5_class_name(void); =20 +/** + * gicv5_raw_spi_state + * @cs: GIC object + * @id: INTID of SPI to look up + * + * Return pointer to the GICv5SPIState for this SPI, or NULL if the + * interrupt ID is out of range. This does not do a check that the + * SPI is assigned to the right domain: generally you should call it + * via some other wrapper that performs an appropriate further check. + */ +static inline GICv5SPIState *gicv5_raw_spi_state(GICv5Common *cs, uint32_t= id) +{ + if (id < cs->spi_base || id >=3D cs->spi_base + cs->spi_irs_range) { + return NULL; + } + + return cs->spi + (id - cs->spi_base); +} + +/** + * gicv5_spi_state: + * @cs: GIC object + * @id: INTID of SPI to look up + * @domain: domain to check + * + * Return pointer to the GICv5SPIState for this SPI, or NULL if the + * interrupt is unreachable (which can be because the INTID is out + * of range, or because the SPI is configured for a different domain). + */ +static inline GICv5SPIState *gicv5_spi_state(GICv5Common *cs, uint32_t id, + GICv5Domain domain) +{ + GICv5SPIState *spi =3D gicv5_raw_spi_state(cs, id); + + if (!spi || spi->domain !=3D domain) { + return NULL; + } + return spi; +} + #endif --=20 2.43.0