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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483a9b21ceasm200155625e9.0.2026.02.23.09.02.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 09:02:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771866159; x=1772470959; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=FzYN9ygidJdhGyDwIINOqZeaIIMy2JouxjcXfZjOhMI=; b=HvI3vFygYfFA0/R1Z2ZTccUtH/6Y+NLQHq6xONzzkMQfRBThv2p4TJ6MhOHdEVNSu4 H27rGofG2EjDABHbeMLhuy2dzwXDvoZZvVFn6phrf5lC8bHkq2H6OHWxbUC5iIZGmuoK 8Zcv6LYk5G3eVxhOHnLlxuimo+e3XyM2sUVciUrLVgCObNHkA1o+/a3DxEunGNs9YH9c u3NdOXrcjji7b+IelJ7JcdPJlTeIfZNDGU9fy5IfDrgTw8X/Ib0hTtgvEennCkZbvUXT hElO5ZTbC/nk0tQlion5GDg4J8nC5cI9tCgY25owWqkGEjIucHtJW52L/LssmoOEinlM Aaug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771866159; x=1772470959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=FzYN9ygidJdhGyDwIINOqZeaIIMy2JouxjcXfZjOhMI=; b=Ya7u6pblhv7p8LwKOsiB7DDRieV99ozyn6bMgXkBFwwCbo5qbpVn3KJcQL4u8KRp+X gKkiw1DnzAS27/ebv51zpNdf7j7VMnQnCDBYowu/Z6Wi3AIFiXr6hHW3s/9wp8OAJfsC g8nIXRbz1skex8q8O3QkHfVW1vbwL21V5ZemPIzCoxmJMK4H+929S1QCXl49jcm3eUnE 2j03jmXuSHpV2FXfgTgvXACnsN9qENWR/jyzoGGGGkCUd1UOB3B8S3X8ahJZHiOznDBj 2g74SAxAI225GPkek9QsI3KZuphZK3aQ9HZnioe/aQMgPMJShJnUL2c7erqhGWqagqW+ i3+g== X-Forwarded-Encrypted: i=1; AJvYcCUMQUG233aUO6o48wjyjuBtYhVwcmykMmmphmgZzhqXqEWXIfewQt9xaCZGWriJkR9IikNUPiM5QjxR@nongnu.org X-Gm-Message-State: AOJu0YyFPc678Wu1Mo0IMGTYo3ekhke4BH2UfD85p6aw+3bS4hj1qe8Y Z3udeWvq03gHJBqYrZqaWS4LWISqwV0zscgb/NoO+HF4+wnPqqBhsjPXhG2ZK0gAI28= X-Gm-Gg: AZuq6aKH/UnW6E4J/cX1fVldL1blE/5pqx4brURpHGd5pLt1h4TQJS5EylLha1JMFSs zW+bqcrd2eU50uecCP9M484uLUp6RI6s0KCy3S7QnSSU8oJviYy60T3TbQScCdCbwKmUBy8peLr QhLE/td9KTJNExgXURU/JJAPCWxjMpARm+3Sh5vNzUyCl5049rIeyeMa60HdDs6XJhsJgzpDQch jUsNmsb4nMJxnuiOAfy6RRqK/vgYrzfhCqafPux24g6/mJBaIKNPPZqy+UlRRWiUBM0tU25KN+1 0+8V/cKjMnsngaU3ynDy6WYl9NuVRzVivdDzX/pbXi2pBMRu7A857Q1lZNPdRB05S5CNvf56KSu 2pkPTodq6HA0+ntLDImyeDv0rD5/x24sH500FHZWF6b1pQ8gXyqLRZdETkCYKZ9ttO68ZQQ7InN 3qWjoQ27KsdvF16X6a4cGBqIxPcdfGLG9nG/aRgsJgg1+agh7gSDOQQ/JNN1KGfH2uMNaw57D/6 TvNYOIAj9Ub95gVXL8cL5pcjJEERFA= X-Received: by 2002:a05:600c:6990:b0:483:6a8d:b2f9 with SMTP id 5b1f17b1804b1-483a95aa328mr156841225e9.5.1771866159369; Mon, 23 Feb 2026 09:02:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 21/65] target/arm: GICv5 cpuif: Implement GIC CD* insns for setting config Date: Mon, 23 Feb 2026 17:01:28 +0000 Message-ID: <20260223170212.441276-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223170212.441276-1-peter.maydell@linaro.org> References: <20260223170212.441276-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771866614636158500 Content-Type: text/plain; charset="utf-8" Implement the GIC CDDIS, GIC CDEN, GIC CDAFF, GIC CDPEND and GIC CDHM system instructions. These are all simple wrappers around the equivalent gicv5_set_* functions, like GIC CDPRI. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- target/arm/tcg/gicv5-cpuif.c | 108 +++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c index 072b38e785..c426e045d9 100644 --- a/target/arm/tcg/gicv5-cpuif.c +++ b/target/arm/tcg/gicv5-cpuif.c @@ -16,6 +16,25 @@ FIELD(GIC_CDPRI, ID, 0, 24) FIELD(GIC_CDPRI, TYPE, 29, 3) FIELD(GIC_CDPRI, PRIORITY, 35, 5) =20 +FIELD(GIC_CDDIS, ID, 0, 24) +FIELD(GIC_CDDIS, TYPE, 29, 3) + +FIELD(GIC_CDEN, ID, 0, 24) +FIELD(GIC_CDEN, TYPE, 29, 3) + +FIELD(GIC_CDAFF, ID, 0, 24) +FIELD(GIC_CDAFF, IRM, 28, 1) +FIELD(GIC_CDAFF, TYPE, 29, 3) +FIELD(GIC_CDAFF, IAFFID, 32, 16) + +FIELD(GIC_CDPEND, ID, 0, 24) +FIELD(GIC_CDPEND, TYPE, 29, 3) +FIELD(GIC_CDPEND, PENDING, 32, 1) + +FIELD(GIC_CDHM, ID, 0, 24) +FIELD(GIC_CDHM, TYPE, 29, 3) +FIELD(GIC_CDHM, HM, 32, 1) + static GICv5Common *gicv5_get_gic(CPUARMState *env) { return env->gicv5state; @@ -51,6 +70,30 @@ static GICv5Domain gicv5_current_phys_domain(CPUARMState= *env) return gicv5_logical_domain(env); } =20 +static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDDIS, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDDIS, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_enabled(gic, id, false, domain, type, virtual); +} + +static void gic_cden_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDEN, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDEN, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_enabled(gic, id, true, domain, type, virtual); +} + static void gic_cdpri_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -64,6 +107,46 @@ static void gic_cdpri_write(CPUARMState *env, const ARM= CPRegInfo *ri, gicv5_set_priority(gic, id, priority, domain, type, virtual); } =20 +static void gic_cdaff_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + uint32_t iaffid =3D FIELD_EX64(value, GIC_CDAFF, IAFFID); + GICv5RoutingMode irm =3D FIELD_EX64(value, GIC_CDAFF, IRM); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDAFF, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDAFF, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_target(gic, id, iaffid, irm, domain, type, virtual); +} + +static void gic_cdpend_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + bool pending =3D FIELD_EX64(value, GIC_CDPEND, PENDING); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDPEND, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDPEND, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_pending(gic, id, pending, domain, type, virtual); +} + +static void gic_cdhm_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + GICv5Common *gic =3D gicv5_get_gic(env); + GICv5HandlingMode hm =3D FIELD_EX64(value, GIC_CDHM, HM); + GICv5IntType type =3D FIELD_EX64(value, GIC_CDAFF, TYPE); + uint32_t id =3D FIELD_EX64(value, GIC_CDAFF, ID); + bool virtual =3D false; + GICv5Domain domain =3D gicv5_current_phys_domain(env); + + gicv5_set_handling(gic, id, hm, domain, type, virtual); +} + static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { /* * Barrier: wait until the effects of a cpuif system register @@ -86,11 +169,36 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NOP, }, + { .name =3D "GIC_CDDIS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cddis_write, + }, + { .name =3D "GIC_CDEN", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cden_write, + }, { .name =3D "GIC_CDPRI", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 2, .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, .writefn =3D gic_cdpri_write, }, + { .name =3D "GIC_CDAFF", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdaff_write, + }, + { .name =3D "GIC_CDPEND", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 4, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdpend_write, + }, + { .name =3D "GIC_CDHM", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 12, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .writefn =3D gic_cdhm_write, + }, }; =20 void define_gicv5_cpuif_regs(ARMCPU *cpu) --=20 2.43.0