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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483a9b21ceasm200155625e9.0.2026.02.23.09.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Feb 2026 09:02:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771866158; x=1772470958; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Pxugm0oWVUcgkpDMORCz85xFJuuEUVhItUG4r6MiPs0=; b=dEzfcDi8EPrNZGt1pK/smxvIwn7w+4jNuj3P7otqjonLrRWlZp98NSY9NgT5soKMMT kIewJ9eVU5Fh/bpqoYQ15ywlXxfTbq/iq9OoZWAVDmIK1+vFWebpL99VXV5HMgGyqMFs 21Neee8HtKeAo2ITDuQ6Jk2uu327plLyBANKt24H/fnxSLrU8rWLI0NwA8mae6yNefPX r5znTxVwtzavhivah68mYNpw1h+nT8Cuvyz2yTgPhzVqhzl06fcAnpoRhn/kF1tWukwQ gDYofSa6iK0TFQUZCL8FuKLAyULB/CiM18iiZ7FqmCsosdUq5o5CtHblw6uc4PoKERbp gmlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771866158; x=1772470958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Pxugm0oWVUcgkpDMORCz85xFJuuEUVhItUG4r6MiPs0=; b=AswhJJcX12O7nx05d+/cigho0fV1r7hhVx/QAwgcwSMRB1+BvpzStKe58dIyLej6Vl 1+t5uy9v+MeTB/4k7O49jetMed9ucbFTGJ9YktAaEKO0RzNjVD+aX3DTbE3NIcr8qHtN V2SkXQ+Ond2lk5VPFmRRp5M3oCdtl8/toexBMtRqyNSNI3W+gQbwn4Ct7Y+1J9Cf2MyJ XK9McvL3VTpG9g8NgCuMkRBlWYanM46M5vfdJ2j/i8XP8HAsB8QRk6mDEmzHniJbIuSj 7jpJPXBq9CBX3bWQw7zLCkYdLwXMsZopAwGnJIkvkXR6qd0U7Vib2PmHW6OyE8I3VAAf EC7Q== X-Forwarded-Encrypted: i=1; AJvYcCUdLsnpNQqJnNVA4H7rJYJ2mbpnqnzu3hZmVMZyTvWk3mePrDddOPnAw99bXcBOObOaUpoYW1o0D92i@nongnu.org X-Gm-Message-State: AOJu0YyQgqiKSBVgF8+G37lVQyoufRzBzO+bywseBWrdd8hrPPGDLz1U Q2kBNmuILiX+VjQZHHUMoUtTN80vJrQt7oTj4HpzCkZ5lBOSDdp8PHHczUtX6yu9deUTqT0j147 a8OI7 X-Gm-Gg: AZuq6aLf2coCc4YTWyWtbKO6PtukingoPiN8PFOiVJ6Z5CRdMIAL+YEx7ZwxO/cIaqt JsVGAMky9i8j9HeXBGZpdqPulkoDLA9H4NiG8NZbzittIaKHXdrw71HM/iLnkDPYy5uIgvfkx8Q S9IIQ26hgHqA0kOkIAW7i5EG3AvoQVjQUfv3NCBateoWpeT4Kg3Cd38YhMubkinBbhN+oWTE8B/ EE7tSp7cSg01ojNgpiTkIHvEYG1Ipto8lYW9rnyDwyp3RK605x92ykTd+sTu83c7Z3zT+2gVyqY ULjpEVEM7oTMPrQMi4wd+aQ61rDfxETfkhVzlW9UTY1Lc7c49jxF2D2op8QKn2fYXG5pr7MYeJW V05QmzJIeAlKwQXVUowvAlWVmIDKGgS2zaGMHxjnCMn4PpgnSS13Nl5acE4oDLU7+OErOhulZ1V AtOnn/lDn3UDGNlcjiI9wYmjGHeV80u1XpUny6V80fHNZMiLVvN1SYBRbcYXOmRKbELdQ67IBfg c4PeJ5GTDexq35eQeS0lGHJAT/tVvM= X-Received: by 2002:a05:600c:3115:b0:47a:814c:eea1 with SMTP id 5b1f17b1804b1-483a961602dmr194302305e9.35.1771866157552; Mon, 23 Feb 2026 09:02:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 19/65] hw/intc/arm_gicv5: Implement IRS_MAP_L2_ISTR Date: Mon, 23 Feb 2026 17:01:26 +0000 Message-ID: <20260223170212.441276-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260223170212.441276-1-peter.maydell@linaro.org> References: <20260223170212.441276-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771866512021158500 Content-Type: text/plain; charset="utf-8" The IRS register IRS_MAP_L2_ISTR is used by software to tell the IRS that it has updated the address in an L1 IST entry to point to an L2 IST. The sequence of events here is: * software writes to L1_ISTE.L2_ADDR for some L1 ISTE which is not valid (i.e. where L1_ISTE.VALID is 0); it leaves VALID at 0 * software writes to IRS_MAP_L2_ISTR with some INTID that is inside the range for this L1 ISTE * the IRS sets IRS_IST_STATUSR.IDLE to 0 * the IRS takes note of this information * the IRS writes to the L1_ISTE to set VALID=3D1 * the IRS sets IRS_IST_STATUSR.IDLE to 1 to indicate that the update is complete For QEMU, we're strictly synchronous, so (as with IRS_IST_BASER updates) we don't need to model the IDLE transitions and can have IRS_IST_STATUSR always return IDLE=3D1. We also don't currently cache anything for ISTE lookups, so we don't need to invalidate or update anything when software makes the L2 valid. Signed-off-by: Peter Maydell Reviewed-by: Jonathan Cameron --- hw/intc/arm_gicv5.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 8572823edc..af27fb7e63 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -492,6 +492,44 @@ void gicv5_set_priority(GICv5Common *cs, uint32_t id, put_l2_iste(cs, cfg, &h); } =20 +static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t v= alue) +{ + GICv5Common *cs =3D ARM_GICV5_COMMON(s); + GICv5ISTConfig *cfg =3D &s->phys_lpi_config[domain]; + uint32_t intid =3D FIELD_EX32(value, IRS_MAP_L2_ISTR, ID); + hwaddr l1_addr; + uint64_t l1_iste; + MemTxResult res; + + if (!FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID) || + !cfg->structure) { + /* WI if no IST set up or it is not 2-level */ + return; + } + + /* Find the relevant L1 ISTE and set its VALID bit */ + l1_addr =3D l1_iste_addr(cs, cfg, intid); + + l1_iste =3D address_space_ldq_le(&cs->dma_as, l1_addr, cfg->txattrs, &= res); + if (res !=3D MEMTX_OK) { + goto txfail; + } + + l1_iste =3D FIELD_DP64(l1_iste, L1_ISTE, VALID, 1); + + address_space_stq_le(&cs->dma_as, l1_addr, l1_iste, cfg->txattrs, &res= ); + if (res !=3D MEMTX_OK) { + goto txfail; + } + return; + +txfail: + /* Reportable with EC=3D0x0 if sw error reporting implemented */ + qemu_log_mask(LOG_GUEST_ERROR, "L1 ISTE update failed for ID 0x%x at " + "physical address 0x" HWADDR_FMT_plx "\n", intid, l1_add= r); +} + + static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t val= ue) { GICv5Common *cs =3D ARM_GICV5_COMMON(s); @@ -675,6 +713,9 @@ static bool config_writel(GICv5 *s, GICv5Domain domain,= hwaddr offset, cs->irs_ist_cfgr[domain] =3D data; } return true; + case A_IRS_MAP_L2_ISTR: + irs_map_l2_istr_write(s, domain, data); + return true; } return false; } --=20 2.43.0