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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.87.114; envelope-from=mohamed@unpredictable.fr; helo=outbound.qs.icloud.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.798, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.79, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1771783447797154100 Content-Type: text/plain; charset="utf-8" Optimise vmexits by save/restoring less state in those cases instead of the= full state. Signed-off-by: Mohamed Mediouni Reviewed-by: Bernhard Beschow Tested-by: Bernhard Beschow --- target/i386/whpx/whpx-all.c | 202 +++++++++++++++++++----------------- 1 file changed, 104 insertions(+), 98 deletions(-) diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index c09d9affef..ab583e922d 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -422,118 +422,124 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLev= el level) } =20 assert(idx =3D=3D WHvX64RegisterLdtr); - vcxt.values[idx++].Segment =3D whpx_seg_q2h(&env->ldt, 0, 0); - - assert(idx =3D=3D WHvX64RegisterTr); - vcxt.values[idx++].Segment =3D whpx_seg_q2h(&env->tr, 0, 0); - - assert(idx =3D=3D WHvX64RegisterIdtr); - vcxt.values[idx].Table.Base =3D env->idt.base; - vcxt.values[idx].Table.Limit =3D env->idt.limit; - idx +=3D 1; - - assert(idx =3D=3D WHvX64RegisterGdtr); - vcxt.values[idx].Table.Base =3D env->gdt.base; - vcxt.values[idx].Table.Limit =3D env->gdt.limit; - idx +=3D 1; - - /* CR0, 2, 3, 4, 8 */ - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr0); - vcxt.values[idx++].Reg64 =3D env->cr[0]; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr2); - vcxt.values[idx++].Reg64 =3D env->cr[2]; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr3); - vcxt.values[idx++].Reg64 =3D env->cr[3]; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr4); - vcxt.values[idx++].Reg64 =3D env->cr[4]; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr8); - vcxt.values[idx++].Reg64 =3D vcpu->tpr; - - /* 8 Debug Registers - Skipped */ - /* - * Extended control registers needs to be handled separately depending - * on whether xsave is supported/enabled or not. + * Skip those registers for synchronisation after MMIO accesses + * as they're not going to be modified in that case. */ - whpx_set_xcrs(cpu); - - /* 16 XMM registers */ - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterXmm0); - idx_next =3D idx + 16; - for (i =3D 0; i < sizeof(env->xmm_regs) / sizeof(ZMMReg); i +=3D 1, id= x +=3D 1) { - vcxt.values[idx].Reg128.Low64 =3D env->xmm_regs[i].ZMM_Q(0); - vcxt.values[idx].Reg128.High64 =3D env->xmm_regs[i].ZMM_Q(1); - } - idx =3D idx_next; - - /* 8 FP registers */ - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterFpMmx0); - for (i =3D 0; i < 8; i +=3D 1, idx +=3D 1) { - vcxt.values[idx].Fp.AsUINT128.Low64 =3D env->fpregs[i].mmx.MMX_Q(0= ); - /* vcxt.values[idx].Fp.AsUINT128.High64 =3D - env->fpregs[i].mmx.MMX_Q(1); - */ - } + if (level > WHPX_LEVEL_FAST_RUNTIME_STATE) { + vcxt.values[idx++].Segment =3D whpx_seg_q2h(&env->ldt, 0, 0); + + assert(idx =3D=3D WHvX64RegisterTr); + vcxt.values[idx++].Segment =3D whpx_seg_q2h(&env->tr, 0, 0); + + assert(idx =3D=3D WHvX64RegisterIdtr); + vcxt.values[idx].Table.Base =3D env->idt.base; + vcxt.values[idx].Table.Limit =3D env->idt.limit; + idx +=3D 1; + + assert(idx =3D=3D WHvX64RegisterGdtr); + vcxt.values[idx].Table.Base =3D env->gdt.base; + vcxt.values[idx].Table.Limit =3D env->gdt.limit; + idx +=3D 1; + + /* CR0, 2, 3, 4, 8 */ + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr0); + vcxt.values[idx++].Reg64 =3D env->cr[0]; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr2); + vcxt.values[idx++].Reg64 =3D env->cr[2]; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr3); + vcxt.values[idx++].Reg64 =3D env->cr[3]; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr4); + vcxt.values[idx++].Reg64 =3D env->cr[4]; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr8); + vcxt.values[idx++].Reg64 =3D vcpu->tpr; + + /* 8 Debug Registers - Skipped */ =20 - /* FP control status register */ - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterFpControlStatus); - vcxt.values[idx].FpControlStatus.FpControl =3D env->fpuc; - vcxt.values[idx].FpControlStatus.FpStatus =3D - (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; - vcxt.values[idx].FpControlStatus.FpTag =3D 0; - for (i =3D 0; i < 8; ++i) { - vcxt.values[idx].FpControlStatus.FpTag |=3D (!env->fptags[i]) << i; - } - vcxt.values[idx].FpControlStatus.Reserved =3D 0; - vcxt.values[idx].FpControlStatus.LastFpOp =3D env->fpop; - vcxt.values[idx].FpControlStatus.LastFpRip =3D env->fpip; - idx +=3D 1; - - /* XMM control status register */ - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterXmmControlStatus); - vcxt.values[idx].XmmControlStatus.LastFpRdp =3D 0; - vcxt.values[idx].XmmControlStatus.XmmStatusControl =3D env->mxcsr; - vcxt.values[idx].XmmControlStatus.XmmStatusControlMask =3D 0x0000ffff; - idx +=3D 1; + /* + * Extended control registers needs to be handled separately depen= ding + * on whether xsave is supported/enabled or not. + */ + whpx_set_xcrs(cpu); + + /* 16 XMM registers */ + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterXmm0); + idx_next =3D idx + 16; + for (i =3D 0; i < sizeof(env->xmm_regs) / sizeof(ZMMReg); i +=3D 1= , idx +=3D 1) { + vcxt.values[idx].Reg128.Low64 =3D env->xmm_regs[i].ZMM_Q(0); + vcxt.values[idx].Reg128.High64 =3D env->xmm_regs[i].ZMM_Q(1); + } + idx =3D idx_next; + + /* 8 FP registers */ + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterFpMmx0); + for (i =3D 0; i < 8; i +=3D 1, idx +=3D 1) { + vcxt.values[idx].Fp.AsUINT128.Low64 =3D env->fpregs[i].mmx.MMX= _Q(0); + /* vcxt.values[idx].Fp.AsUINT128.High64 =3D + env->fpregs[i].mmx.MMX_Q(1); + */ + } =20 - /* MSRs */ - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterEfer); - vcxt.values[idx++].Reg64 =3D env->efer; + /* FP control status register */ + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterFpControlStat= us); + vcxt.values[idx].FpControlStatus.FpControl =3D env->fpuc; + vcxt.values[idx].FpControlStatus.FpStatus =3D + (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; + vcxt.values[idx].FpControlStatus.FpTag =3D 0; + for (i =3D 0; i < 8; ++i) { + vcxt.values[idx].FpControlStatus.FpTag |=3D (!env->fptags[i]) = << i; + } + vcxt.values[idx].FpControlStatus.Reserved =3D 0; + vcxt.values[idx].FpControlStatus.LastFpOp =3D env->fpop; + vcxt.values[idx].FpControlStatus.LastFpRip =3D env->fpip; + idx +=3D 1; + + /* XMM control status register */ + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterXmmControlSta= tus); + vcxt.values[idx].XmmControlStatus.LastFpRdp =3D 0; + vcxt.values[idx].XmmControlStatus.XmmStatusControl =3D env->mxcsr; + vcxt.values[idx].XmmControlStatus.XmmStatusControlMask =3D 0x0000f= fff; + idx +=3D 1; + + /* MSRs */ + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterEfer); + vcxt.values[idx++].Reg64 =3D env->efer; #ifdef TARGET_X86_64 - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterKernelGsBase); - vcxt.values[idx++].Reg64 =3D env->kernelgsbase; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterKernelGsBase); + vcxt.values[idx++].Reg64 =3D env->kernelgsbase; #endif =20 - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterApicBase); - vcxt.values[idx++].Reg64 =3D vcpu->apic_base; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterApicBase); + vcxt.values[idx++].Reg64 =3D vcpu->apic_base; =20 - /* WHvX64RegisterPat - Skipped */ + /* WHvX64RegisterPat - Skipped */ =20 - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterSysenterCs); - vcxt.values[idx++].Reg64 =3D env->sysenter_cs; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterSysenterEip); - vcxt.values[idx++].Reg64 =3D env->sysenter_eip; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterSysenterEsp); - vcxt.values[idx++].Reg64 =3D env->sysenter_esp; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterStar); - vcxt.values[idx++].Reg64 =3D env->star; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterSysenterCs); + vcxt.values[idx++].Reg64 =3D env->sysenter_cs; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterSysenterEip); + vcxt.values[idx++].Reg64 =3D env->sysenter_eip; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterSysenterEsp); + vcxt.values[idx++].Reg64 =3D env->sysenter_esp; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterStar); + vcxt.values[idx++].Reg64 =3D env->star; #ifdef TARGET_X86_64 - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterLstar); - vcxt.values[idx++].Reg64 =3D env->lstar; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCstar); - vcxt.values[idx++].Reg64 =3D env->cstar; - assert(whpx_register_names[idx] =3D=3D WHvX64RegisterSfmask); - vcxt.values[idx++].Reg64 =3D env->fmask; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterLstar); + vcxt.values[idx++].Reg64 =3D env->lstar; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCstar); + vcxt.values[idx++].Reg64 =3D env->cstar; + assert(whpx_register_names[idx] =3D=3D WHvX64RegisterSfmask); + vcxt.values[idx++].Reg64 =3D env->fmask; #endif =20 - /* Interrupt / Event Registers - Skipped */ + /* Interrupt / Event Registers - Skipped */ =20 - assert(idx =3D=3D RTL_NUMBER_OF(whpx_register_names)); + assert(idx =3D=3D RTL_NUMBER_OF(whpx_register_names)); + } =20 hr =3D whp_dispatch.WHvSetVirtualProcessorRegisters( whpx->partition, cpu->cpu_index, whpx_register_names, - RTL_NUMBER_OF(whpx_register_names), + idx, &vcxt.values[0]); =20 if (FAILED(hr)) { @@ -613,7 +619,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel l= evel) hr); } =20 - if (whpx_irqchip_in_kernel()) { + if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && whpx_irqchip_in_kernel())= { /* * Fetch the TPR value from the emulated APIC. It may get overwrit= ten * below with the value from CR8 returned by @@ -670,7 +676,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel l= evel) env->cr[4] =3D vcxt.values[idx++].Reg64; assert(whpx_register_names[idx] =3D=3D WHvX64RegisterCr8); tpr =3D vcxt.values[idx++].Reg64; - if (tpr !=3D vcpu->tpr) { + if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && tpr !=3D vcpu->tpr) { vcpu->tpr =3D tpr; cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr)); } @@ -756,7 +762,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel l= evel) =20 assert(idx =3D=3D RTL_NUMBER_OF(whpx_register_names)); =20 - if (whpx_irqchip_in_kernel()) { + if (level > WHPX_LEVEL_FAST_RUNTIME_STATE && whpx_irqchip_in_kernel())= { whpx_apic_get(x86_cpu->apic_state); } =20 --=20 2.50.1 (Apple Git-155)