From nobody Sun Apr 12 02:50:55 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177174880567983.76605912221783; Sun, 22 Feb 2026 00:26:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vu4mr-0000z5-2f; Sun, 22 Feb 2026 03:25:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vu4mp-0000yU-NE; Sun, 22 Feb 2026 03:25:55 -0500 Received: from sgoci-sdnproxy-4.icoremail.net ([129.150.39.64]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vu4mk-0005aI-58; Sun, 22 Feb 2026 03:25:55 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwAXbdCHvZpp1BB3AA--.4276S2; Sun, 22 Feb 2026 16:25:43 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwB3z+x9vZpp+HAcAA--.49763S5; Sun, 22 Feb 2026 16:25:42 +0800 (CST) From: Tao Tang To: Fabiano Rosas , Laurent Vivier , Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , Chao Liu , Tao Tang Subject: [RFC 2/2] tests/qtest: Add qtest-attrs-test to verify memory access with attr Date: Sun, 22 Feb 2026 16:25:29 +0800 Message-Id: <20260222082529.491384-3-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260222082529.491384-1-tangtao1634@phytium.com.cn> References: <20260222082529.491384-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwB3z+x9vZpp+HAcAA--.49763S5 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQAOBWmaIJsAKwAAsp Authentication-Results: hzbj-icmmx-6; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvAXoWfZw17Wr13Cr4fJrykCr18AFb_yoW8tr48Zo WftF42g3W2yr47ur9xtrZrAr42gwsYkFs3CF4xXr4xXFyxCF42ka15AFZxJ3s0y34kG3sr GFZrK3WSyrsrtrn3n29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3UbIjqfuFe4nvWSU8nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UU UUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.150.39.64; envelope-from=tangtao1634@phytium.com.cn; helo=sgoci-sdnproxy-4.icoremail.net X-Spam_score_int: 8 X-Spam_score: 0.8 X-Spam_bar: / X-Spam_report: (0.8 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_PH_SUBJ_META=2.699 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1771748812307158500 Content-Type: text/plain; charset="utf-8" Add a new test case `qtest-attrs-test` to validate the newly introduced `*_secure` and `*_space` qtest commands. The test covers: - ARM (virt machine): Verifies access to all four ARM security spaces (Secure, NonSecure, Root, Realm). - x86 (pc machine): Verifies access to the SMM AddressSpace. Signed-off-by: Tao Tang --- tests/qtest/meson.build | 4 +- tests/qtest/qtest-attrs-test.c | 669 +++++++++++++++++++++++++++++++++ 2 files changed, 672 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/qtest-attrs-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 25fdbc7980..a53c90474a 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -115,6 +115,7 @@ qtests_i386 =3D \ 'drive_del-test', 'cpu-plug-test', 'migration-test', + 'qtest-attrs-test', ] =20 if dbus_display and config_all_devices.has_key('CONFIG_VGA') @@ -272,7 +273,8 @@ qtests_aarch64 =3D \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', - 'migration-test'] + 'migration-test', + 'qtest-attrs-test'] =20 qtests_s390x =3D \ qtests_filter + \ diff --git a/tests/qtest/qtest-attrs-test.c b/tests/qtest/qtest-attrs-test.c new file mode 100644 index 0000000000..69daced706 --- /dev/null +++ b/tests/qtest/qtest-attrs-test.c @@ -0,0 +1,669 @@ +/* + * QTest for memory access with transaction attributes + * + * This test verifies if the qtest *_secure and *_space commands work corr= ectly. + * + * Two architectures are covered: + * + * - ARM (virt machine, cortex-a57, secure=3Don): + * *_secure uses the ARM Secure AddressSpace (ARMASIdx_S =3D 1). + * *_space uses all four ARM security spaces (Secure/NonSecure/Root/Re= alm). + * secure=3Don is required so that the ARM Secure address space is ini= tialised; + * + * - x86 (pc machine, TCG): + * *_secure uses the SMM AddressSpace (X86ASIdx_SMM =3D 1). + * On TCG, cpu_address_space_init() always creates X86ASIdx_SMM as a + * container that is an alias of all system memory, so no special mach= ine + * flags are needed -- the SMM AS exists unconditionally under TCG. + * *_space commands are ARM-specific and have no x86 equivalents. + * + * Copyright (c) 2026 Phytium Technology + * + * Author: + * Tao Tang + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "libqtest-single.h" +#include "hw/arm/arm-security.h" + + +/* + * Define test addresses for ARM and x86. + * + * Default RAM size is 128 MiB for all architectures including "virt" mach= ine in + * ARM and "pc" machine in x86. + * We define a 4 KiB size offset above the RAM base, both in ARM and x86, = as the + * test address. + */ +#define TEST_ADDR_OFFSET 0x1000ULL +#define TEST_ARM_BASE 0x40000000ULL +#define TEST_X86_BASE 0x0ULL + +#define TEST_ADDR_ARM (TEST_ARM_BASE + TEST_ADDR_OFFSET) +#define TEST_ADDR_X86 (TEST_X86_BASE + TEST_ADDR_OFFSET) + +#define ARM_MACHINE_ARGS "-machine virt,secure=3Don -cpu cortex-a57" + +/* ARM *_secure tests */ + +static void test_arm_writeb_readb_secure(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + /* secure=3D0: NonSecure access */ + qtest_writeb_secure(qts, TEST_ADDR_ARM, 0x55, 0); + val =3D qtest_readb_secure(qts, TEST_ADDR_ARM, 0); + g_assert_cmpuint(val, =3D=3D, 0x55); + + /* secure=3D1: Secure access (ARM Secure AS) */ + qtest_writeb_secure(qts, TEST_ADDR_ARM, 0xAA, 1); + val =3D qtest_readb_secure(qts, TEST_ADDR_ARM, 1); + g_assert_cmpuint(val, =3D=3D, 0xAA); + + qtest_quit(qts); +} + +static void test_arm_writew_readw_secure(void) +{ + QTestState *qts; + uint16_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writew_secure(qts, TEST_ADDR_ARM, 0x1234, 0); + val =3D qtest_readw_secure(qts, TEST_ADDR_ARM, 0); + g_assert_cmpuint(val, =3D=3D, 0x1234); + + qtest_writew_secure(qts, TEST_ADDR_ARM, 0x1234, 1); + val =3D qtest_readw_secure(qts, TEST_ADDR_ARM, 1); + g_assert_cmpuint(val, =3D=3D, 0x1234); + + qtest_quit(qts); +} + +static void test_arm_writel_readl_secure(void) +{ + QTestState *qts; + uint32_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writel_secure(qts, TEST_ADDR_ARM, 0xDEADBEEF, 0); + val =3D qtest_readl_secure(qts, TEST_ADDR_ARM, 0); + g_assert_cmpuint(val, =3D=3D, 0xDEADBEEF); + + qtest_writel_secure(qts, TEST_ADDR_ARM, 0xDEADBEEF, 1); + val =3D qtest_readl_secure(qts, TEST_ADDR_ARM, 1); + g_assert_cmpuint(val, =3D=3D, 0xDEADBEEF); + + qtest_quit(qts); +} + +static void test_arm_writeq_readq_secure(void) +{ + QTestState *qts; + uint64_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writeq_secure(qts, TEST_ADDR_ARM, 0x123456789ABCDEF0ULL, 0); + val =3D qtest_readq_secure(qts, TEST_ADDR_ARM, 0); + g_assert_cmpuint(val, =3D=3D, 0x123456789ABCDEF0ULL); + + qtest_writeq_secure(qts, TEST_ADDR_ARM, 0x123456789ABCDEF0ULL, 1); + val =3D qtest_readq_secure(qts, TEST_ADDR_ARM, 1); + g_assert_cmpuint(val, =3D=3D, 0x123456789ABCDEF0ULL); + + qtest_quit(qts); +} + +static void test_arm_memwrite_memread_secure(void) +{ + QTestState *qts; + uint8_t wbuf[16] =3D { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF }; + uint8_t rbuf[16]; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memwrite_secure(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), 0); + qtest_memread_secure(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), 0); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_secure(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), 1); + qtest_memread_secure(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), 1); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_quit(qts); +} + +static void test_arm_memset_secure(void) +{ + QTestState *qts; + uint8_t rbuf[16]; + size_t i; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memset_secure(qts, TEST_ADDR_ARM, 0x42, sizeof(rbuf), 0); + qtest_memread_secure(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), 0); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x42); + } + + qtest_memset_secure(qts, TEST_ADDR_ARM, 0x42, sizeof(rbuf), 1); + qtest_memread_secure(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), 1); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x42); + } + + qtest_quit(qts); +} + +/* ARM *_space tests (ARM-specific: Secure/NonSecure/Root/Realm) */ + +static void test_arm_writeb_readb_space(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + /* NonSecure space (secure=3D0) */ + qtest_writeb_space(qts, TEST_ADDR_ARM, 0x11, ARMSS_NonSecure); + val =3D qtest_readb_space(qts, TEST_ADDR_ARM, ARMSS_NonSecure); + g_assert_cmpuint(val, =3D=3D, 0x11); + + /* Realm space (secure=3D0) */ + qtest_writeb_space(qts, TEST_ADDR_ARM, 0x33, ARMSS_Realm); + val =3D qtest_readb_space(qts, TEST_ADDR_ARM, ARMSS_Realm); + g_assert_cmpuint(val, =3D=3D, 0x33); + + /* Secure space (secure=3D1) */ + qtest_writeb_space(qts, TEST_ADDR_ARM, 0x22, ARMSS_Secure); + val =3D qtest_readb_space(qts, TEST_ADDR_ARM, ARMSS_Secure); + g_assert_cmpuint(val, =3D=3D, 0x22); + + /* Root space (secure=3D1) */ + qtest_writeb_space(qts, TEST_ADDR_ARM, 0x44, ARMSS_Root); + val =3D qtest_readb_space(qts, TEST_ADDR_ARM, ARMSS_Root); + g_assert_cmpuint(val, =3D=3D, 0x44); + + qtest_quit(qts); +} + +static void test_arm_writew_readw_space(void) +{ + QTestState *qts; + uint16_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writew_space(qts, TEST_ADDR_ARM + 0x10, 0x1122, ARMSS_NonSecure); + val =3D qtest_readw_space(qts, TEST_ADDR_ARM + 0x10, ARMSS_NonSecure); + g_assert_cmpuint(val, =3D=3D, 0x1122); + + qtest_writew_space(qts, TEST_ADDR_ARM + 0x20, 0x3344, ARMSS_Realm); + val =3D qtest_readw_space(qts, TEST_ADDR_ARM + 0x20, ARMSS_Realm); + g_assert_cmpuint(val, =3D=3D, 0x3344); + + qtest_writew_space(qts, TEST_ADDR_ARM + 0x30, 0x5566, ARMSS_Secure); + val =3D qtest_readw_space(qts, TEST_ADDR_ARM + 0x30, ARMSS_Secure); + g_assert_cmpuint(val, =3D=3D, 0x5566); + + qtest_writew_space(qts, TEST_ADDR_ARM + 0x40, 0x7788, ARMSS_Root); + val =3D qtest_readw_space(qts, TEST_ADDR_ARM + 0x40, ARMSS_Root); + g_assert_cmpuint(val, =3D=3D, 0x7788); + + qtest_quit(qts); +} + +static void test_arm_writel_readl_space(void) +{ + QTestState *qts; + uint32_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writel_space(qts, TEST_ADDR_ARM + 0x50, 0x11223344, ARMSS_NonSec= ure); + val =3D qtest_readl_space(qts, TEST_ADDR_ARM + 0x50, ARMSS_NonSecure); + g_assert_cmpuint(val, =3D=3D, 0x11223344); + + qtest_writel_space(qts, TEST_ADDR_ARM + 0x60, 0x55667788, ARMSS_Realm); + val =3D qtest_readl_space(qts, TEST_ADDR_ARM + 0x60, ARMSS_Realm); + g_assert_cmpuint(val, =3D=3D, 0x55667788); + + qtest_writel_space(qts, TEST_ADDR_ARM + 0x70, 0x99AABBCC, ARMSS_Secure= ); + val =3D qtest_readl_space(qts, TEST_ADDR_ARM + 0x70, ARMSS_Secure); + g_assert_cmpuint(val, =3D=3D, 0x99AABBCC); + + qtest_writel_space(qts, TEST_ADDR_ARM + 0x80, 0xDDEEFF00, ARMSS_Root); + val =3D qtest_readl_space(qts, TEST_ADDR_ARM + 0x80, ARMSS_Root); + g_assert_cmpuint(val, =3D=3D, 0xDDEEFF00); + + qtest_quit(qts); +} + +static void test_arm_writeq_readq_space(void) +{ + QTestState *qts; + uint64_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writeq_space(qts, TEST_ADDR_ARM + 0x90, 0x1122334455667788ULL, + ARMSS_NonSecure); + val =3D qtest_readq_space(qts, TEST_ADDR_ARM + 0x90, ARMSS_NonSecure); + g_assert_cmpuint(val, =3D=3D, 0x1122334455667788ULL); + + qtest_writeq_space(qts, TEST_ADDR_ARM + 0xA0, 0x99AABBCCDDEEFF00ULL, + ARMSS_Realm); + val =3D qtest_readq_space(qts, TEST_ADDR_ARM + 0xA0, ARMSS_Realm); + g_assert_cmpuint(val, =3D=3D, 0x99AABBCCDDEEFF00ULL); + + qtest_writeq_space(qts, TEST_ADDR_ARM + 0xB0, 0x0123456789ABCDEFULL, + ARMSS_Secure); + val =3D qtest_readq_space(qts, TEST_ADDR_ARM + 0xB0, ARMSS_Secure); + g_assert_cmpuint(val, =3D=3D, 0x0123456789ABCDEFULL); + + qtest_writeq_space(qts, TEST_ADDR_ARM + 0xC0, 0xFEDCBA9876543210ULL, + ARMSS_Root); + val =3D qtest_readq_space(qts, TEST_ADDR_ARM + 0xC0, ARMSS_Root); + g_assert_cmpuint(val, =3D=3D, 0xFEDCBA9876543210ULL); + + qtest_quit(qts); +} + +static void test_arm_memwrite_memread_space(void) +{ + QTestState *qts; + uint8_t wbuf[8] =3D { 0xA1, 0xB2, 0xC3, 0xD4, 0xE5, 0xF6, 0x07, 0x18 }; + uint8_t rbuf[8]; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memwrite_space(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), ARMSS_Non= Secure); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_NonS= ecure); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_space(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), ARMSS_Rea= lm); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Real= m); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + + qtest_memwrite_space(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), ARMSS_Sec= ure); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Secu= re); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_space(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), ARMSS_Roo= t); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Root= ); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_quit(qts); +} + +static void test_arm_memset_space(void) +{ + QTestState *qts; + uint8_t rbuf[8]; + size_t i; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memset_space(qts, TEST_ADDR_ARM, 0x99, sizeof(rbuf), ARMSS_NonSe= cure); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_NonS= ecure); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x99); + } + + qtest_memset_space(qts, TEST_ADDR_ARM, 0x99, sizeof(rbuf), ARMSS_Realm= ); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Real= m); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x99); + } + + qtest_memset_space(qts, TEST_ADDR_ARM, 0x99, sizeof(rbuf), ARMSS_Secur= e); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Secu= re); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x99); + } + + qtest_memset_space(qts, TEST_ADDR_ARM, 0x99, sizeof(rbuf), ARMSS_Root); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Root= ); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x99); + } + + qtest_quit(qts); +} + +/* Test new *_secure / *_space API in libqtest-single.h */ +static void test_arm_single_secure(void) +{ + uint8_t val; + uint8_t wbuf[4] =3D { 0x10, 0x20, 0x30, 0x40 }; + uint8_t rbuf[4]; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qtest_start(ARM_MACHINE_ARGS); + + writeb_secure(TEST_ADDR_ARM, 0x5A, 0); + val =3D readb_secure(TEST_ADDR_ARM, 0); + g_assert_cmpuint(val, =3D=3D, 0x5A); + + memwrite_secure(TEST_ADDR_ARM + 0x80, wbuf, sizeof(wbuf), 0); + memread_secure(TEST_ADDR_ARM + 0x80, rbuf, sizeof(rbuf), 0); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_end(); +} + +static void test_arm_single_space(void) +{ + uint32_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qtest_start(ARM_MACHINE_ARGS); + + writel_space(TEST_ADDR_ARM + 0x400, 0xA5A5A5A5, ARMSS_NonSecure); + val =3D readl_space(TEST_ADDR_ARM + 0x400, ARMSS_NonSecure); + g_assert_cmpuint(val, =3D=3D, 0xA5A5A5A5); + + writel_space(TEST_ADDR_ARM + 0x404, 0x1A2B3C4D, ARMSS_Realm); + val =3D readl_space(TEST_ADDR_ARM + 0x404, ARMSS_Realm); + g_assert_cmpuint(val, =3D=3D, 0x1A2B3C4D); + + writel_space(TEST_ADDR_ARM + 0x408, 0x55667788, ARMSS_Secure); + val =3D readl_space(TEST_ADDR_ARM + 0x408, ARMSS_Secure); + g_assert_cmpuint(val, =3D=3D, 0x55667788); + + writel_space(TEST_ADDR_ARM + 0x40C, 0xCCDDEEFF, ARMSS_Root); + val =3D readl_space(TEST_ADDR_ARM + 0x40C, ARMSS_Root); + g_assert_cmpuint(val, =3D=3D, 0xCCDDEEFF); + + qtest_end(); +} + +#define X86_MACHINE_ARGS "-machine pc -accel tcg" + +/* x86 *_secure tests */ +static void test_x86_writeb_readb_secure(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + /* secure=3D0: normal memory access (X86ASIdx_MEM) */ + qtest_writeb_secure(qts, TEST_ADDR_X86, 0x55, 0); + val =3D qtest_readb_secure(qts, TEST_ADDR_X86, 0); + g_assert_cmpuint(val, =3D=3D, 0x55); + + /* secure=3D1: SMM address space (X86ASIdx_SMM) */ + qtest_writeb_secure(qts, TEST_ADDR_X86, 0xAA, 1); + val =3D qtest_readb_secure(qts, TEST_ADDR_X86, 1); + g_assert_cmpuint(val, =3D=3D, 0xAA); + + qtest_quit(qts); +} + +static void test_x86_writew_readw_secure(void) +{ + QTestState *qts; + uint16_t val; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_writew_secure(qts, TEST_ADDR_X86, 0x1234, 0); + val =3D qtest_readw_secure(qts, TEST_ADDR_X86, 0); + g_assert_cmpuint(val, =3D=3D, 0x1234); + + qtest_writew_secure(qts, TEST_ADDR_X86, 0x5678, 1); + val =3D qtest_readw_secure(qts, TEST_ADDR_X86, 1); + g_assert_cmpuint(val, =3D=3D, 0x5678); + + qtest_quit(qts); +} + +static void test_x86_writel_readl_secure(void) +{ + QTestState *qts; + uint32_t val; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_writel_secure(qts, TEST_ADDR_X86, 0xDEADBEEF, 0); + val =3D qtest_readl_secure(qts, TEST_ADDR_X86, 0); + g_assert_cmpuint(val, =3D=3D, 0xDEADBEEF); + + qtest_writel_secure(qts, TEST_ADDR_X86, 0xCAFEBABE, 1); + val =3D qtest_readl_secure(qts, TEST_ADDR_X86, 1); + g_assert_cmpuint(val, =3D=3D, 0xCAFEBABE); + + qtest_quit(qts); +} + +static void test_x86_writeq_readq_secure(void) +{ + QTestState *qts; + uint64_t val; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_writeq_secure(qts, TEST_ADDR_X86, 0x123456789ABCDEF0ULL, 0); + val =3D qtest_readq_secure(qts, TEST_ADDR_X86, 0); + g_assert_cmpuint(val, =3D=3D, 0x123456789ABCDEF0ULL); + + qtest_writeq_secure(qts, TEST_ADDR_X86, 0xFEDCBA9876543210ULL, 1); + val =3D qtest_readq_secure(qts, TEST_ADDR_X86, 1); + g_assert_cmpuint(val, =3D=3D, 0xFEDCBA9876543210ULL); + + qtest_quit(qts); +} + +static void test_x86_memwrite_memread_secure(void) +{ + QTestState *qts; + uint8_t wbuf[16] =3D { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF }; + uint8_t rbuf[16]; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_memwrite_secure(qts, TEST_ADDR_X86, wbuf, sizeof(wbuf), 0); + qtest_memread_secure(qts, TEST_ADDR_X86, rbuf, sizeof(rbuf), 0); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_secure(qts, TEST_ADDR_X86 + 0x100, wbuf, sizeof(wbuf), = 1); + qtest_memread_secure(qts, TEST_ADDR_X86 + 0x100, rbuf, sizeof(rbuf), 1= ); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_quit(qts); +} + +static void test_x86_memset_secure(void) +{ + QTestState *qts; + uint8_t rbuf[16]; + size_t i; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_memset_secure(qts, TEST_ADDR_X86, 0x42, sizeof(rbuf), 0); + qtest_memread_secure(qts, TEST_ADDR_X86, rbuf, sizeof(rbuf), 0); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x42); + } + + qtest_memset_secure(qts, TEST_ADDR_X86 + 0x100, 0xBE, sizeof(rbuf), 1); + qtest_memread_secure(qts, TEST_ADDR_X86 + 0x100, rbuf, sizeof(rbuf), 1= ); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0xBE); + } + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + /* ARM *_secure tests (secure/non-secure, requires secure=3Don) */ + qtest_add_func("/qtest/arm/secure/writeb_readb", + test_arm_writeb_readb_secure); + qtest_add_func("/qtest/arm/secure/writew_readw", + test_arm_writew_readw_secure); + qtest_add_func("/qtest/arm/secure/writel_readl", + test_arm_writel_readl_secure); + qtest_add_func("/qtest/arm/secure/writeq_readq", + test_arm_writeq_readq_secure); + qtest_add_func("/qtest/arm/secure/memwrite_memread", + test_arm_memwrite_memread_secure); + qtest_add_func("/qtest/arm/secure/memset", + test_arm_memset_secure); + + /* ARM *_space tests (Secure/NonSecure/Root/Realm, requires secure=3Do= n) */ + qtest_add_func("/qtest/arm/space/writeb_readb", + test_arm_writeb_readb_space); + qtest_add_func("/qtest/arm/space/writew_readw", + test_arm_writew_readw_space); + qtest_add_func("/qtest/arm/space/writel_readl", + test_arm_writel_readl_space); + qtest_add_func("/qtest/arm/space/writeq_readq", + test_arm_writeq_readq_space); + qtest_add_func("/qtest/arm/space/memwrite_memread", + test_arm_memwrite_memread_space); + qtest_add_func("/qtest/arm/space/memset", + test_arm_memset_space); + qtest_add_func("/qtest/arm/secure/single_shortcuts", + test_arm_single_secure); + qtest_add_func("/qtest/arm/space/single_shortcuts", + test_arm_single_space); + + /* x86 *_secure tests (SMM address space, X86ASIdx_SMM =3D 1) */ + qtest_add_func("/qtest/x86/secure/writeb_readb", + test_x86_writeb_readb_secure); + qtest_add_func("/qtest/x86/secure/writew_readw", + test_x86_writew_readw_secure); + qtest_add_func("/qtest/x86/secure/writel_readl", + test_x86_writel_readl_secure); + qtest_add_func("/qtest/x86/secure/writeq_readq", + test_x86_writeq_readq_secure); + qtest_add_func("/qtest/x86/secure/memwrite_memread", + test_x86_memwrite_memread_secure); + qtest_add_func("/qtest/x86/secure/memset", + test_x86_memset_secure); + + return g_test_run(); +} --=20 2.34.1