From nobody Sun Apr 12 02:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771748805679149.29853832479853; Sun, 22 Feb 2026 00:26:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vu4mt-00010I-Ra; Sun, 22 Feb 2026 03:25:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vu4mq-0000yq-AA; Sun, 22 Feb 2026 03:25:56 -0500 Received: from sgoci-sdnproxy-4.icoremail.net ([129.150.39.64]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vu4mk-0005aH-3K; Sun, 22 Feb 2026 03:25:56 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwDnPNCHvZppzxB3AA--.4403S2; Sun, 22 Feb 2026 16:25:43 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwB3z+x9vZpp+HAcAA--.49763S4; Sun, 22 Feb 2026 16:25:40 +0800 (CST) From: Tao Tang To: Fabiano Rosas , Laurent Vivier , Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , Chao Liu , Tao Tang Subject: [RFC 1/2] tests/qtest: Support for memory access with secure/space attr Date: Sun, 22 Feb 2026 16:25:28 +0800 Message-Id: <20260222082529.491384-2-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260222082529.491384-1-tangtao1634@phytium.com.cn> References: <20260222082529.491384-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwB3z+x9vZpp+HAcAA--.49763S4 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQAOBWmaIJsAKQAAsr Authentication-Results: hzbj-icmmx-6; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvAXoWfZw13WFWxZF1xJF1xKry3Arb_yoW5tryfCo WSgF1qv3srJw47ur9a9r9rtr17W395uryxZr4Fyr15Ka4xur47uay3tF43Xr1qkF1rGr9r WF4kXF18Wr42y3s3n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3UbIjqfuFe4nvWSU8nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UU UUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.150.39.64; envelope-from=tangtao1634@phytium.com.cn; helo=sgoci-sdnproxy-4.icoremail.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1771748812396158500 Content-Type: text/plain; charset="utf-8" Introduce `*_secure` and `*_space` commands to the qtest protocol and libqtest API. This allows testing devices that behave differently based on security state (e.g., ARM TrustZone/CCA or x86 SMM). - `*_secure` commands specify the SECURE parameter (0 or 1) and are compatible with x86 and ARM. - `*_space` commands specify the ARM security space (0-3) and are ARM-specific. Signed-off-by: Tao Tang --- system/qtest.c | 482 ++++++++++++++++++++++++++++++++++ tests/qtest/libqtest-single.h | 133 ++++++++++ tests/qtest/libqtest.c | 249 ++++++++++++++++++ tests/qtest/libqtest.h | 281 ++++++++++++++++++++ 4 files changed, 1145 insertions(+) diff --git a/system/qtest.c b/system/qtest.c index e42b83ce67..2140aaac99 100644 --- a/system/qtest.c +++ b/system/qtest.c @@ -217,6 +217,60 @@ static void *qtest_server_send_opaque; * B64_DATA is an arbitrarily long base64 encoded string. * If the sizes do not match, the data will be truncated. * + * Memory access with MemTxAttrs: + * """""""""""""""""""""""""""""" + * + * The following commands allow specifying memory transaction attributes, + * which is useful for testing devices that behave differently based on + * security state (e.g., ARM TrustZone/CCA or System Management Mode in x8= 6). + * + * Two variants are available: + * + * 1. ``*_secure`` commands: Available on x86 and ARM. + * Only specifies the SECURE parameter (0 or 1). + * When SECURE=3D1, uses the secure AddressSpace. The asidx argument to + * cpu_get_address_space() can only be 1 on x86 (SMM mode, X86ASIdx_SMM) a= nd + * ARM (Secure state, ARMASIdx_S); all other targets always use 0 for the = asidx + * parameter. When issuing ``*_secure`` commands, we assert that the secure + * AddressSpace must exist. + * + * 2. ``*_space`` commands: ARM-specific. + * Only specifies the SPACE parameter (0-3). + * SECURE is auto-derived: secure=3D1 for Secure(0)/Root(2), secure=3D0 for + * NonSecure(1)/Realm(3), following ARM's arm_space_is_secure() semantics. + * + * Secure variants with .secure attribute (x86/ARM): + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * .. code-block:: none + * + * > writeb_secure ADDR VALUE SECURE + * < OK + * > readb_secure ADDR SECURE + * < OK VALUE + * > read_secure ADDR SIZE SECURE + * < OK DATA + * > write_secure ADDR SIZE DATA SECURE + * < OK + * > memset_secure ADDR SIZE VALUE SECURE + * < OK + * + * Space variants with .space attribute (ARM-specific): + * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + * + * .. code-block:: none + * + * > writeb_space ADDR VALUE SPACE + * < OK + * > readb_space ADDR SPACE + * < OK VALUE + * > read_space ADDR SIZE SPACE + * < OK DATA + * > write_space ADDR SIZE DATA SPACE + * < OK + * > memset_space ADDR SIZE VALUE SPACE + * < OK + * * IRQ management: * """"""""""""""" * @@ -668,6 +722,434 @@ static void qtest_process_command(CharFrontend *chr, = gchar **words) g_free(data); } =20 + qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "writeb_secure") =3D=3D 0 || + strcmp(words[0], "writew_secure") =3D=3D 0 || + strcmp(words[0], "writel_secure") =3D=3D 0 || + strcmp(words[0], "writeq_secure") =3D=3D 0) { + /* + * *_secure commands: x86/ARM compatible. + * Only specifies SECURE parameter. + */ + uint64_t addr, value, secure; + MemTxAttrs attrs; + AddressSpace *as; + int ret; + + g_assert(words[1] && words[2] && words[3]); + ret =3D qemu_strtou64(words[1], NULL, 0, &addr); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[2], NULL, 0, &value); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[3], NULL, 0, &secure); + g_assert(ret =3D=3D 0); + + attrs.secure =3D secure & 1; + + if (attrs.secure) { + as =3D cpu_get_address_space(first_cpu, 1); + /* Secure AddressSpace must be available when issuing secure c= ommands */ + g_assert(as); + } else { + as =3D first_cpu->as; + } + + if (words[0][5] =3D=3D 'b') { + uint8_t data =3D value; + address_space_write(as, addr, attrs, &data, 1); + } else if (words[0][5] =3D=3D 'w') { + uint16_t data =3D value; + tswap16s(&data); + address_space_write(as, addr, attrs, &data, 2); + } else if (words[0][5] =3D=3D 'l') { + uint32_t data =3D value; + tswap32s(&data); + address_space_write(as, addr, attrs, &data, 4); + } else if (words[0][5] =3D=3D 'q') { + uint64_t data =3D value; + tswap64s(&data); + address_space_write(as, addr, attrs, &data, 8); + } + qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "readb_secure") =3D=3D 0 || + strcmp(words[0], "readw_secure") =3D=3D 0 || + strcmp(words[0], "readl_secure") =3D=3D 0 || + strcmp(words[0], "readq_secure") =3D=3D 0) { + uint64_t addr, secure; + uint64_t value =3D UINT64_C(-1); + MemTxAttrs attrs; + AddressSpace *as; + int ret; + + g_assert(words[1] && words[2]); + ret =3D qemu_strtou64(words[1], NULL, 0, &addr); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[2], NULL, 0, &secure); + g_assert(ret =3D=3D 0); + + attrs.secure =3D secure & 1; + + if (attrs.secure) { + as =3D cpu_get_address_space(first_cpu, 1); + g_assert(as); + } else { + as =3D first_cpu->as; + } + + if (words[0][4] =3D=3D 'b') { + uint8_t data; + address_space_read(as, addr, attrs, &data, 1); + value =3D data; + } else if (words[0][4] =3D=3D 'w') { + uint16_t data; + address_space_read(as, addr, attrs, &data, 2); + value =3D tswap16(data); + } else if (words[0][4] =3D=3D 'l') { + uint32_t data; + address_space_read(as, addr, attrs, &data, 4); + value =3D tswap32(data); + } else if (words[0][4] =3D=3D 'q') { + address_space_read(as, addr, attrs, &value, 8); + tswap64s(&value); + } + qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value); + } else if (strcmp(words[0], "read_secure") =3D=3D 0) { + g_autoptr(GString) enc =3D NULL; + uint64_t addr, len, secure; + uint8_t *data; + MemTxAttrs attrs; + AddressSpace *as; + int ret; + + g_assert(words[1] && words[2] && words[3]); + ret =3D qemu_strtou64(words[1], NULL, 0, &addr); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[2], NULL, 0, &len); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[3], NULL, 0, &secure); + g_assert(ret =3D=3D 0); + g_assert(len); + + attrs.secure =3D secure & 1; + + if (attrs.secure) { + as =3D cpu_get_address_space(first_cpu, 1); + g_assert(as); + } else { + as =3D first_cpu->as; + } + + data =3D g_malloc(len); + address_space_read(as, addr, attrs, data, len); + + enc =3D qemu_hexdump_line(NULL, data, len, 0, 0); + qtest_sendf(chr, "OK 0x%s\n", enc->str); + g_free(data); + } else if (strcmp(words[0], "write_secure") =3D=3D 0) { + uint64_t addr, len, i, secure; + uint8_t *data; + size_t data_len; + MemTxAttrs attrs; + AddressSpace *as; + int ret; + + g_assert(words[1] && words[2] && words[3] && words[4]); + ret =3D qemu_strtou64(words[1], NULL, 0, &addr); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[2], NULL, 0, &len); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[4], NULL, 0, &secure); + g_assert(ret =3D=3D 0); + + data_len =3D strlen(words[3]); + if (data_len < 3) { + qtest_send(chr, "ERR invalid argument size\n"); + return; + } + + attrs.secure =3D secure & 1; + + if (attrs.secure) { + as =3D cpu_get_address_space(first_cpu, 1); + g_assert(as); + } else { + as =3D first_cpu->as; + } + + data =3D g_malloc(len); + for (i =3D 0; i < len; i++) { + if ((i * 2 + 4) <=3D data_len) { + data[i] =3D hex2nib(words[3][i * 2 + 2]) << 4; + data[i] |=3D hex2nib(words[3][i * 2 + 3]); + } else { + data[i] =3D 0; + } + } + address_space_write(as, addr, attrs, data, len); + g_free(data); + + qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "memset_secure") =3D=3D 0) { + uint64_t addr, len, secure; + uint8_t *data; + unsigned long pattern; + MemTxAttrs attrs; + AddressSpace *as; + int ret; + + g_assert(words[1] && words[2] && words[3] && words[4]); + ret =3D qemu_strtou64(words[1], NULL, 0, &addr); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[2], NULL, 0, &len); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtoul(words[3], NULL, 0, &pattern); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[4], NULL, 0, &secure); + g_assert(ret =3D=3D 0); + + attrs.secure =3D secure & 1; + + if (attrs.secure) { + as =3D cpu_get_address_space(first_cpu, 1); + g_assert(as); + } else { + as =3D first_cpu->as; + } + + if (len) { + data =3D g_malloc(len); + memset(data, pattern, len); + address_space_write(as, addr, attrs, data, len); + g_free(data); + } + + qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "writeb_space") =3D=3D 0 || + strcmp(words[0], "writew_space") =3D=3D 0 || + strcmp(words[0], "writel_space") =3D=3D 0 || + strcmp(words[0], "writeq_space") =3D=3D 0) { + /* *_space commands: ARM-specific. */ + uint64_t addr, value, space; + MemTxAttrs attrs; + AddressSpace *as; + int ret; + + if (!target_arm() && !target_aarch64()) { + qtest_send(chr, "ERR *_space commands are ARM-specific\n"); + return; + } + + g_assert(words[1] && words[2] && words[3]); + ret =3D qemu_strtou64(words[1], NULL, 0, &addr); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[2], NULL, 0, &value); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[3], NULL, 0, &space); + g_assert(ret =3D=3D 0); + + attrs.space =3D space & 3; + attrs.secure =3D (attrs.space =3D=3D 0 || attrs.space =3D=3D 2) ? = 1 : 0; + + if (attrs.secure) { + as =3D cpu_get_address_space(first_cpu, 1); + g_assert(as); + } else { + as =3D first_cpu->as; + } + + if (words[0][5] =3D=3D 'b') { + uint8_t data =3D value; + address_space_write(as, addr, attrs, &data, 1); + } else if (words[0][5] =3D=3D 'w') { + uint16_t data =3D value; + tswap16s(&data); + address_space_write(as, addr, attrs, &data, 2); + } else if (words[0][5] =3D=3D 'l') { + uint32_t data =3D value; + tswap32s(&data); + address_space_write(as, addr, attrs, &data, 4); + } else if (words[0][5] =3D=3D 'q') { + uint64_t data =3D value; + tswap64s(&data); + address_space_write(as, addr, attrs, &data, 8); + } + qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "readb_space") =3D=3D 0 || + strcmp(words[0], "readw_space") =3D=3D 0 || + strcmp(words[0], "readl_space") =3D=3D 0 || + strcmp(words[0], "readq_space") =3D=3D 0) { + uint64_t addr, space; + uint64_t value =3D UINT64_C(-1); + MemTxAttrs attrs; + AddressSpace *as; + int ret; + + if (!target_arm() && !target_aarch64()) { + qtest_send(chr, "ERR *_space commands are ARM-specific\n"); + return; + } + + g_assert(words[1] && words[2]); + ret =3D qemu_strtou64(words[1], NULL, 0, &addr); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[2], NULL, 0, &space); + g_assert(ret =3D=3D 0); + + attrs.space =3D space & 3; + attrs.secure =3D (attrs.space =3D=3D 0 || attrs.space =3D=3D 2) ? = 1 : 0; + + if (attrs.secure) { + as =3D cpu_get_address_space(first_cpu, 1); + g_assert(as); + } else { + as =3D first_cpu->as; + } + + if (words[0][4] =3D=3D 'b') { + uint8_t data; + address_space_read(as, addr, attrs, &data, 1); + value =3D data; + } else if (words[0][4] =3D=3D 'w') { + uint16_t data; + address_space_read(as, addr, attrs, &data, 2); + value =3D tswap16(data); + } else if (words[0][4] =3D=3D 'l') { + uint32_t data; + address_space_read(as, addr, attrs, &data, 4); + value =3D tswap32(data); + } else if (words[0][4] =3D=3D 'q') { + address_space_read(as, addr, attrs, &value, 8); + tswap64s(&value); + } + qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value); + } else if (strcmp(words[0], "read_space") =3D=3D 0) { + g_autoptr(GString) enc =3D NULL; + uint64_t addr, len, space; + uint8_t *data; + MemTxAttrs attrs; + AddressSpace *as; + int ret; + + if (!target_arm() && !target_aarch64()) { + qtest_send(chr, "ERR *_space commands are ARM-specific\n"); + return; + } + + g_assert(words[1] && words[2] && words[3]); + ret =3D qemu_strtou64(words[1], NULL, 0, &addr); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[2], NULL, 0, &len); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[3], NULL, 0, &space); + g_assert(ret =3D=3D 0); + g_assert(len); + + attrs.space =3D space & 3; + attrs.secure =3D (attrs.space =3D=3D 0 || attrs.space =3D=3D 2) ? = 1 : 0; + + if (attrs.secure) { + as =3D cpu_get_address_space(first_cpu, 1); + g_assert(as); + } else { + as =3D first_cpu->as; + } + + data =3D g_malloc(len); + address_space_read(as, addr, attrs, data, len); + + enc =3D qemu_hexdump_line(NULL, data, len, 0, 0); + qtest_sendf(chr, "OK 0x%s\n", enc->str); + g_free(data); + } else if (strcmp(words[0], "write_space") =3D=3D 0) { + uint64_t addr, len, i, space; + uint8_t *data; + size_t data_len; + MemTxAttrs attrs; + AddressSpace *as; + int ret; + + if (!target_arm() && !target_aarch64()) { + qtest_send(chr, "ERR *_space commands are ARM-specific\n"); + return; + } + + g_assert(words[1] && words[2] && words[3] && words[4]); + ret =3D qemu_strtou64(words[1], NULL, 0, &addr); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[2], NULL, 0, &len); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[4], NULL, 0, &space); + g_assert(ret =3D=3D 0); + + data_len =3D strlen(words[3]); + if (data_len < 3) { + qtest_send(chr, "ERR invalid argument size\n"); + return; + } + + attrs.space =3D space & 3; + attrs.secure =3D (attrs.space =3D=3D 0 || attrs.space =3D=3D 2) ? = 1 : 0; + + if (attrs.secure) { + as =3D cpu_get_address_space(first_cpu, 1); + g_assert(as); + } else { + as =3D first_cpu->as; + } + + data =3D g_malloc(len); + for (i =3D 0; i < len; i++) { + if ((i * 2 + 4) <=3D data_len) { + data[i] =3D hex2nib(words[3][i * 2 + 2]) << 4; + data[i] |=3D hex2nib(words[3][i * 2 + 3]); + } else { + data[i] =3D 0; + } + } + address_space_write(as, addr, attrs, data, len); + g_free(data); + + qtest_send(chr, "OK\n"); + } else if (strcmp(words[0], "memset_space") =3D=3D 0) { + uint64_t addr, len, space; + uint8_t *data; + unsigned long pattern; + MemTxAttrs attrs; + AddressSpace *as; + int ret; + + if (!target_arm() && !target_aarch64()) { + qtest_send(chr, "ERR *_space commands are ARM-specific\n"); + return; + } + + g_assert(words[1] && words[2] && words[3] && words[4]); + ret =3D qemu_strtou64(words[1], NULL, 0, &addr); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[2], NULL, 0, &len); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtoul(words[3], NULL, 0, &pattern); + g_assert(ret =3D=3D 0); + ret =3D qemu_strtou64(words[4], NULL, 0, &space); + g_assert(ret =3D=3D 0); + + attrs.space =3D space & 3; + attrs.secure =3D (attrs.space =3D=3D 0 || attrs.space =3D=3D 2) ? = 1 : 0; + + if (attrs.secure) { + as =3D cpu_get_address_space(first_cpu, 1); + g_assert(as); + } else { + as =3D first_cpu->as; + } + + if (len) { + data =3D g_malloc(len); + memset(data, pattern, len); + address_space_write(as, addr, attrs, data, len); + g_free(data); + } + qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "b64write") =3D=3D 0) { uint64_t addr, len; diff --git a/tests/qtest/libqtest-single.h b/tests/qtest/libqtest-single.h index 851724cbcb..d7c89154e3 100644 --- a/tests/qtest/libqtest-single.h +++ b/tests/qtest/libqtest-single.h @@ -291,6 +291,139 @@ static inline void memwrite(uint64_t addr, const void= *data, size_t size) qtest_memwrite(global_qtest, addr, data, size); } =20 +/* + * *_secure commands: only available with x86/ARM. + */ + +static inline void writeb_secure(uint64_t addr, uint8_t value, + unsigned secure) +{ + qtest_writeb_secure(global_qtest, addr, value, secure); +} + +static inline void writew_secure(uint64_t addr, uint16_t value, + unsigned secure) +{ + qtest_writew_secure(global_qtest, addr, value, secure); +} + +static inline void writel_secure(uint64_t addr, uint32_t value, + unsigned secure) +{ + qtest_writel_secure(global_qtest, addr, value, secure); +} + +static inline void writeq_secure(uint64_t addr, uint64_t value, + unsigned secure) +{ + qtest_writeq_secure(global_qtest, addr, value, secure); +} + +static inline uint8_t readb_secure(uint64_t addr, unsigned secure) +{ + return qtest_readb_secure(global_qtest, addr, secure); +} + +static inline uint16_t readw_secure(uint64_t addr, unsigned secure) +{ + return qtest_readw_secure(global_qtest, addr, secure); +} + +static inline uint32_t readl_secure(uint64_t addr, unsigned secure) +{ + return qtest_readl_secure(global_qtest, addr, secure); +} + +static inline uint64_t readq_secure(uint64_t addr, unsigned secure) +{ + return qtest_readq_secure(global_qtest, addr, secure); +} + +static inline void memread_secure(uint64_t addr, void *data, size_t size, + unsigned secure) +{ + qtest_memread_secure(global_qtest, addr, data, size, secure); +} + +static inline void memwrite_secure(uint64_t addr, const void *data, + size_t size, unsigned secure) +{ + qtest_memwrite_secure(global_qtest, addr, data, size, secure); +} + +static inline void memset_secure(uint64_t addr, uint8_t pattern, + size_t size, unsigned secure) +{ + qtest_memset_secure(global_qtest, addr, pattern, size, secure); +} + +/** + * *_space commands: ARM-specific. + * Only specifies SPACE parameter, SECURE is auto-derived using + * arm_space_is_secure-like semantics. + */ +static inline void writeb_space(uint64_t addr, uint8_t value, + unsigned space) +{ + qtest_writeb_space(global_qtest, addr, value, space); +} + +static inline void writew_space(uint64_t addr, uint16_t value, + unsigned space) +{ + qtest_writew_space(global_qtest, addr, value, space); +} + +static inline void writel_space(uint64_t addr, uint32_t value, + unsigned space) +{ + qtest_writel_space(global_qtest, addr, value, space); +} + +static inline void writeq_space(uint64_t addr, uint64_t value, + unsigned space) +{ + qtest_writeq_space(global_qtest, addr, value, space); +} + +static inline uint8_t readb_space(uint64_t addr, unsigned space) +{ + return qtest_readb_space(global_qtest, addr, space); +} + +static inline uint16_t readw_space(uint64_t addr, unsigned space) +{ + return qtest_readw_space(global_qtest, addr, space); +} + +static inline uint32_t readl_space(uint64_t addr, unsigned space) +{ + return qtest_readl_space(global_qtest, addr, space); +} + +static inline uint64_t readq_space(uint64_t addr, unsigned space) +{ + return qtest_readq_space(global_qtest, addr, space); +} + +static inline void memread_space(uint64_t addr, void *data, size_t size, + unsigned space) +{ + qtest_memread_space(global_qtest, addr, data, size, space); +} + +static inline void memwrite_space(uint64_t addr, const void *data, + size_t size, unsigned space) +{ + qtest_memwrite_space(global_qtest, addr, data, size, space); +} + +static inline void memset_space(uint64_t addr, uint8_t pattern, + size_t size, unsigned space) +{ + qtest_memset_space(global_qtest, addr, pattern, size, space); +} + /** * clock_step_next: * diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 794d870085..308428829b 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1447,6 +1447,255 @@ void qtest_memset(QTestState *s, uint64_t addr, uin= t8_t pattern, size_t size) qtest_rsp(s); } =20 +/** + * qtest_*_secure commands: only available with x86/ARM. + */ +static void qtest_write_secure(QTestState *s, const char *cmd, uint64_t ad= dr, + uint64_t value, unsigned secure) +{ + qtest_sendf(s, "%s 0x%" PRIx64 " 0x%" PRIx64 " %u\n", + cmd, addr, value, secure); + qtest_rsp(s); +} + +static uint64_t qtest_read_secure(QTestState *s, const char *cmd, + uint64_t addr, unsigned secure) +{ + gchar **args; + int ret; + uint64_t value; + + qtest_sendf(s, "%s 0x%" PRIx64 " %u\n", cmd, addr, secure); + args =3D qtest_rsp_args(s, 2); + ret =3D qemu_strtou64(args[1], NULL, 0, &value); + g_assert(!ret); + g_strfreev(args); + + return value; +} + +void qtest_writeb_secure(QTestState *s, uint64_t addr, uint8_t value, + unsigned secure) +{ + qtest_write_secure(s, "writeb_secure", addr, value, secure); +} + +void qtest_writew_secure(QTestState *s, uint64_t addr, uint16_t value, + unsigned secure) +{ + qtest_write_secure(s, "writew_secure", addr, value, secure); +} + +void qtest_writel_secure(QTestState *s, uint64_t addr, uint32_t value, + unsigned secure) +{ + qtest_write_secure(s, "writel_secure", addr, value, secure); +} + +void qtest_writeq_secure(QTestState *s, uint64_t addr, uint64_t value, + unsigned secure) +{ + qtest_write_secure(s, "writeq_secure", addr, value, secure); +} + +uint8_t qtest_readb_secure(QTestState *s, uint64_t addr, unsigned secure) +{ + return qtest_read_secure(s, "readb_secure", addr, secure); +} + +uint16_t qtest_readw_secure(QTestState *s, uint64_t addr, unsigned secure) +{ + return qtest_read_secure(s, "readw_secure", addr, secure); +} + +uint32_t qtest_readl_secure(QTestState *s, uint64_t addr, unsigned secure) +{ + return qtest_read_secure(s, "readl_secure", addr, secure); +} + +uint64_t qtest_readq_secure(QTestState *s, uint64_t addr, unsigned secure) +{ + return qtest_read_secure(s, "readq_secure", addr, secure); +} + +void qtest_memread_secure(QTestState *s, uint64_t addr, void *data, + size_t size, unsigned secure) +{ + uint8_t *ptr =3D data; + gchar **args; + size_t i; + + if (!size) { + return; + } + + qtest_sendf(s, "read_secure 0x%" PRIx64 " 0x%zx %u\n", addr, size, sec= ure); + args =3D qtest_rsp_args(s, 2); + + for (i =3D 0; i < size; i++) { + ptr[i] =3D hex2nib(args[1][2 + (i * 2)]) << 4; + ptr[i] |=3D hex2nib(args[1][2 + (i * 2) + 1]); + } + + g_strfreev(args); +} + +void qtest_memwrite_secure(QTestState *s, uint64_t addr, const void *data, + size_t size, unsigned secure) +{ + const uint8_t *ptr =3D data; + size_t i; + char *enc; + + if (!size) { + return; + } + + enc =3D g_malloc(2 * size + 1); + + for (i =3D 0; i < size; i++) { + sprintf(&enc[i * 2], "%02x", ptr[i]); + } + + qtest_sendf(s, "write_secure 0x%" PRIx64 " 0x%zx 0x%s %u\n", + addr, size, enc, secure); + qtest_rsp(s); + g_free(enc); +} + +void qtest_memset_secure(QTestState *s, uint64_t addr, uint8_t pattern, + size_t size, unsigned secure) +{ + qtest_sendf(s, "memset_secure 0x%" PRIx64 " 0x%zx 0x%02x %u\n", + addr, size, pattern, secure); + qtest_rsp(s); +} + +/** + * *_space commands: ARM-specific + */ + +static void qtest_write_space(QTestState *s, const char *cmd, + uint64_t addr, uint64_t value, unsigned spac= e) +{ + qtest_sendf(s, "%s 0x%" PRIx64 " 0x%" PRIx64 " %u\n", + cmd, addr, value, space); + qtest_rsp(s); +} + +static uint64_t qtest_read_space(QTestState *s, const char *cmd, + uint64_t addr, unsigned space) +{ + gchar **args; + int ret; + uint64_t value; + + qtest_sendf(s, "%s 0x%" PRIx64 " %u\n", cmd, addr, space); + args =3D qtest_rsp_args(s, 2); + ret =3D qemu_strtou64(args[1], NULL, 0, &value); + g_assert(!ret); + g_strfreev(args); + + return value; +} + +void qtest_writeb_space(QTestState *s, uint64_t addr, uint8_t value, + unsigned space) +{ + qtest_write_space(s, "writeb_space", addr, value, space); +} + +void qtest_writew_space(QTestState *s, uint64_t addr, uint16_t value, + unsigned space) +{ + qtest_write_space(s, "writew_space", addr, value, space); +} + +void qtest_writel_space(QTestState *s, uint64_t addr, uint32_t value, + unsigned space) +{ + qtest_write_space(s, "writel_space", addr, value, space); +} + +void qtest_writeq_space(QTestState *s, uint64_t addr, uint64_t value, + unsigned space) +{ + qtest_write_space(s, "writeq_space", addr, value, space); +} + +uint8_t qtest_readb_space(QTestState *s, uint64_t addr, unsigned space) +{ + return qtest_read_space(s, "readb_space", addr, space); +} + +uint16_t qtest_readw_space(QTestState *s, uint64_t addr, unsigned space) +{ + return qtest_read_space(s, "readw_space", addr, space); +} + +uint32_t qtest_readl_space(QTestState *s, uint64_t addr, unsigned space) +{ + return qtest_read_space(s, "readl_space", addr, space); +} + +uint64_t qtest_readq_space(QTestState *s, uint64_t addr, unsigned space) +{ + return qtest_read_space(s, "readq_space", addr, space); +} + +void qtest_memread_space(QTestState *s, uint64_t addr, void *data, + size_t size, unsigned space) +{ + uint8_t *ptr =3D data; + gchar **args; + size_t i; + + if (!size) { + return; + } + + qtest_sendf(s, "read_space 0x%" PRIx64 " 0x%zx %u\n", addr, size, spac= e); + args =3D qtest_rsp_args(s, 2); + + for (i =3D 0; i < size; i++) { + ptr[i] =3D hex2nib(args[1][2 + (i * 2)]) << 4; + ptr[i] |=3D hex2nib(args[1][2 + (i * 2) + 1]); + } + + g_strfreev(args); +} + +void qtest_memwrite_space(QTestState *s, uint64_t addr, const void *data, + size_t size, unsigned space) +{ + const uint8_t *ptr =3D data; + size_t i; + char *enc; + + if (!size) { + return; + } + + enc =3D g_malloc(2 * size + 1); + + for (i =3D 0; i < size; i++) { + sprintf(&enc[i * 2], "%02x", ptr[i]); + } + + qtest_sendf(s, "write_space 0x%" PRIx64 " 0x%zx 0x%s %u\n", + addr, size, enc, space); + qtest_rsp(s); + g_free(enc); +} + +void qtest_memset_space(QTestState *s, uint64_t addr, uint8_t pattern, + size_t size, unsigned space) +{ + qtest_sendf(s, "memset_space 0x%" PRIx64 " 0x%zx 0x%02x %u\n", + addr, size, pattern, space); + qtest_rsp(s); +} + QDict *qtest_vqmp_assert_failure_ref(QTestState *qts, const char *fmt, va_list args) { diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index 9c118c89ca..57d6be7ca8 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -705,6 +705,287 @@ void qtest_bufwrite(QTestState *s, uint64_t addr, */ void qtest_memset(QTestState *s, uint64_t addr, uint8_t patt, size_t size); =20 +/* + * qtest_*_secure commands: only available with x86/ARM. + */ + +/** + * qtest_writeb_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @secure: 1 for secure access, 0 for non-secure. + * + * Writes an 8-bit value to memory with secure attribute (x86/ARM). + */ +void qtest_writeb_secure(QTestState *s, uint64_t addr, uint8_t value, + unsigned secure); + +/** + * qtest_writew_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @secure: 1 for secure access, 0 for non-secure. + * + * Writes a 16-bit value to memory with secure attribute (x86/ARM). + */ +void qtest_writew_secure(QTestState *s, uint64_t addr, uint16_t value, + unsigned secure); + +/** + * qtest_writel_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @secure: 1 for secure access, 0 for non-secure. + * + * Writes a 32-bit value to memory with secure attribute (x86/ARM). + */ +void qtest_writel_secure(QTestState *s, uint64_t addr, uint32_t value, + unsigned secure); + +/** + * qtest_writeq_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @secure: 1 for secure access, 0 for non-secure. + * + * Writes a 64-bit value to memory with secure attribute (x86/ARM). + */ +void qtest_writeq_secure(QTestState *s, uint64_t addr, uint64_t value, + unsigned secure); + +/** + * qtest_readb_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @secure: 1 for secure access, 0 for non-secure. + * + * Reads an 8-bit value from memory with secure attribute (x86/ARM). + * + * Returns: Value read. + */ +uint8_t qtest_readb_secure(QTestState *s, uint64_t addr, unsigned secure); + +/** + * qtest_readw_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @secure: 1 for secure access, 0 for non-secure. + * + * Reads a 16-bit value from memory with secure attribute (x86/ARM). + * + * Returns: Value read. + */ +uint16_t qtest_readw_secure(QTestState *s, uint64_t addr, unsigned secure); + +/** + * qtest_readl_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @secure: 1 for secure access, 0 for non-secure. + * + * Reads a 32-bit value from memory with secure attribute (x86/ARM). + * + * Returns: Value read. + */ +uint32_t qtest_readl_secure(QTestState *s, uint64_t addr, unsigned secure); + +/** + * qtest_readq_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @secure: 1 for secure access, 0 for non-secure. + * + * Reads a 64-bit value from memory with secure attribute (x86/ARM). + * + * Returns: Value read. + */ +uint64_t qtest_readq_secure(QTestState *s, uint64_t addr, unsigned secure); + +/** + * qtest_memread_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @data: Pointer to where memory contents will be stored. + * @size: Number of bytes to read. + * @secure: 1 for secure access, 0 for non-secure. + * + * Read guest memory into a buffer with secure attribute (x86/ARM). + */ +void qtest_memread_secure(QTestState *s, uint64_t addr, void *data, + size_t size, unsigned secure); + +/** + * qtest_memwrite_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @data: Pointer to the bytes that will be written to guest memory. + * @size: Number of bytes to write. + * @secure: 1 for secure access, 0 for non-secure. + * + * Write a buffer to guest memory with secure attribute (x86/ARM). + */ +void qtest_memwrite_secure(QTestState *s, uint64_t addr, const void *data, + size_t size, unsigned secure); + +/** + * qtest_memset_secure: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @patt: Byte pattern to fill the guest memory region with. + * @size: Number of bytes to write. + * @secure: 1 for secure access, 0 for non-secure. + * + * Write a pattern to guest memory with secure attribute (x86/ARM). + */ +void qtest_memset_secure(QTestState *s, uint64_t addr, uint8_t patt, + size_t size, unsigned secure); + + +/* + * qtest_*_space commands: ARM-specific. + * Only specifies SPACE parameter, SECURE is auto-derived using + * arm_space_is_secure-like semantics. + */ + +/** + * qtest_writeb_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Writes an 8-bit value to memory with ARM security space (ARM-specific). + */ +void qtest_writeb_space(QTestState *s, uint64_t addr, uint8_t value, + unsigned space); + +/** + * qtest_writew_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Writes a 16-bit value to memory with ARM security space (ARM-specific). + */ +void qtest_writew_space(QTestState *s, uint64_t addr, uint16_t value, + unsigned space); + +/** + * qtest_writel_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Writes a 32-bit value to memory with ARM security space (ARM-specific). + */ +void qtest_writel_space(QTestState *s, uint64_t addr, uint32_t value, + unsigned space); + +/** + * qtest_writeq_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @value: Value being written. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Writes a 64-bit value to memory with ARM security space (ARM-specific). + */ +void qtest_writeq_space(QTestState *s, uint64_t addr, uint64_t value, + unsigned space); + +/** + * qtest_readb_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Reads an 8-bit value from memory with ARM security space (ARM-specific). + * + * Returns: Value read. + */ +uint8_t qtest_readb_space(QTestState *s, uint64_t addr, unsigned space); + +/** + * qtest_readw_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Reads a 16-bit value from memory with ARM security space (ARM-specific). + * + * Returns: Value read. + */ +uint16_t qtest_readw_space(QTestState *s, uint64_t addr, unsigned space); + +/** + * qtest_readl_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Reads a 32-bit value from memory with ARM security space (ARM-specific). + * + * Returns: Value read. + */ +uint32_t qtest_readl_space(QTestState *s, uint64_t addr, unsigned space); + +/** + * qtest_readq_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Reads a 64-bit value from memory with ARM security space (ARM-specific). + * + * Returns: Value read. + */ +uint64_t qtest_readq_space(QTestState *s, uint64_t addr, unsigned space); + +/** + * qtest_memread_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to read from. + * @data: Pointer to where memory contents will be stored. + * @size: Number of bytes to read. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Read guest memory into a buffer with ARM security space (ARM-specific). + */ +void qtest_memread_space(QTestState *s, uint64_t addr, void *data, + size_t size, unsigned space); + +/** + * qtest_memwrite_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @data: Pointer to the bytes that will be written to guest memory. + * @size: Number of bytes to write. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Write a buffer to guest memory with ARM security space (ARM-specific). + */ +void qtest_memwrite_space(QTestState *s, uint64_t addr, const void *data, + size_t size, unsigned space); + +/** + * qtest_memset_space: + * @s: #QTestState instance to operate on. + * @addr: Guest address to write to. + * @patt: Byte pattern to fill the guest memory region with. + * @size: Number of bytes to write. + * @space: Security space (0=3DSecure, 1=3DNonSecure, 2=3DRoot, 3=3DRealm). + * + * Write a pattern to guest memory with ARM security space (ARM-specific). + */ +void qtest_memset_space(QTestState *s, uint64_t addr, uint8_t patt, + size_t size, unsigned space); + /** * qtest_clock_step_next: * @s: #QTestState instance to operate on. --=20 2.34.1 From nobody Sun Apr 12 02:50:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177174880567983.76605912221783; Sun, 22 Feb 2026 00:26:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vu4mr-0000z5-2f; Sun, 22 Feb 2026 03:25:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vu4mp-0000yU-NE; Sun, 22 Feb 2026 03:25:55 -0500 Received: from sgoci-sdnproxy-4.icoremail.net ([129.150.39.64]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vu4mk-0005aI-58; Sun, 22 Feb 2026 03:25:55 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwAXbdCHvZpp1BB3AA--.4276S2; Sun, 22 Feb 2026 16:25:43 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwB3z+x9vZpp+HAcAA--.49763S5; Sun, 22 Feb 2026 16:25:42 +0800 (CST) From: Tao Tang To: Fabiano Rosas , Laurent Vivier , Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , Chao Liu , Tao Tang Subject: [RFC 2/2] tests/qtest: Add qtest-attrs-test to verify memory access with attr Date: Sun, 22 Feb 2026 16:25:29 +0800 Message-Id: <20260222082529.491384-3-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260222082529.491384-1-tangtao1634@phytium.com.cn> References: <20260222082529.491384-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwB3z+x9vZpp+HAcAA--.49763S5 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQAOBWmaIJsAKwAAsp Authentication-Results: hzbj-icmmx-6; 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charset="utf-8" Add a new test case `qtest-attrs-test` to validate the newly introduced `*_secure` and `*_space` qtest commands. The test covers: - ARM (virt machine): Verifies access to all four ARM security spaces (Secure, NonSecure, Root, Realm). - x86 (pc machine): Verifies access to the SMM AddressSpace. Signed-off-by: Tao Tang --- tests/qtest/meson.build | 4 +- tests/qtest/qtest-attrs-test.c | 669 +++++++++++++++++++++++++++++++++ 2 files changed, 672 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/qtest-attrs-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 25fdbc7980..a53c90474a 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -115,6 +115,7 @@ qtests_i386 =3D \ 'drive_del-test', 'cpu-plug-test', 'migration-test', + 'qtest-attrs-test', ] =20 if dbus_display and config_all_devices.has_key('CONFIG_VGA') @@ -272,7 +273,8 @@ qtests_aarch64 =3D \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', - 'migration-test'] + 'migration-test', + 'qtest-attrs-test'] =20 qtests_s390x =3D \ qtests_filter + \ diff --git a/tests/qtest/qtest-attrs-test.c b/tests/qtest/qtest-attrs-test.c new file mode 100644 index 0000000000..69daced706 --- /dev/null +++ b/tests/qtest/qtest-attrs-test.c @@ -0,0 +1,669 @@ +/* + * QTest for memory access with transaction attributes + * + * This test verifies if the qtest *_secure and *_space commands work corr= ectly. + * + * Two architectures are covered: + * + * - ARM (virt machine, cortex-a57, secure=3Don): + * *_secure uses the ARM Secure AddressSpace (ARMASIdx_S =3D 1). + * *_space uses all four ARM security spaces (Secure/NonSecure/Root/Re= alm). + * secure=3Don is required so that the ARM Secure address space is ini= tialised; + * + * - x86 (pc machine, TCG): + * *_secure uses the SMM AddressSpace (X86ASIdx_SMM =3D 1). + * On TCG, cpu_address_space_init() always creates X86ASIdx_SMM as a + * container that is an alias of all system memory, so no special mach= ine + * flags are needed -- the SMM AS exists unconditionally under TCG. + * *_space commands are ARM-specific and have no x86 equivalents. + * + * Copyright (c) 2026 Phytium Technology + * + * Author: + * Tao Tang + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "libqtest-single.h" +#include "hw/arm/arm-security.h" + + +/* + * Define test addresses for ARM and x86. + * + * Default RAM size is 128 MiB for all architectures including "virt" mach= ine in + * ARM and "pc" machine in x86. + * We define a 4 KiB size offset above the RAM base, both in ARM and x86, = as the + * test address. + */ +#define TEST_ADDR_OFFSET 0x1000ULL +#define TEST_ARM_BASE 0x40000000ULL +#define TEST_X86_BASE 0x0ULL + +#define TEST_ADDR_ARM (TEST_ARM_BASE + TEST_ADDR_OFFSET) +#define TEST_ADDR_X86 (TEST_X86_BASE + TEST_ADDR_OFFSET) + +#define ARM_MACHINE_ARGS "-machine virt,secure=3Don -cpu cortex-a57" + +/* ARM *_secure tests */ + +static void test_arm_writeb_readb_secure(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + /* secure=3D0: NonSecure access */ + qtest_writeb_secure(qts, TEST_ADDR_ARM, 0x55, 0); + val =3D qtest_readb_secure(qts, TEST_ADDR_ARM, 0); + g_assert_cmpuint(val, =3D=3D, 0x55); + + /* secure=3D1: Secure access (ARM Secure AS) */ + qtest_writeb_secure(qts, TEST_ADDR_ARM, 0xAA, 1); + val =3D qtest_readb_secure(qts, TEST_ADDR_ARM, 1); + g_assert_cmpuint(val, =3D=3D, 0xAA); + + qtest_quit(qts); +} + +static void test_arm_writew_readw_secure(void) +{ + QTestState *qts; + uint16_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writew_secure(qts, TEST_ADDR_ARM, 0x1234, 0); + val =3D qtest_readw_secure(qts, TEST_ADDR_ARM, 0); + g_assert_cmpuint(val, =3D=3D, 0x1234); + + qtest_writew_secure(qts, TEST_ADDR_ARM, 0x1234, 1); + val =3D qtest_readw_secure(qts, TEST_ADDR_ARM, 1); + g_assert_cmpuint(val, =3D=3D, 0x1234); + + qtest_quit(qts); +} + +static void test_arm_writel_readl_secure(void) +{ + QTestState *qts; + uint32_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writel_secure(qts, TEST_ADDR_ARM, 0xDEADBEEF, 0); + val =3D qtest_readl_secure(qts, TEST_ADDR_ARM, 0); + g_assert_cmpuint(val, =3D=3D, 0xDEADBEEF); + + qtest_writel_secure(qts, TEST_ADDR_ARM, 0xDEADBEEF, 1); + val =3D qtest_readl_secure(qts, TEST_ADDR_ARM, 1); + g_assert_cmpuint(val, =3D=3D, 0xDEADBEEF); + + qtest_quit(qts); +} + +static void test_arm_writeq_readq_secure(void) +{ + QTestState *qts; + uint64_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writeq_secure(qts, TEST_ADDR_ARM, 0x123456789ABCDEF0ULL, 0); + val =3D qtest_readq_secure(qts, TEST_ADDR_ARM, 0); + g_assert_cmpuint(val, =3D=3D, 0x123456789ABCDEF0ULL); + + qtest_writeq_secure(qts, TEST_ADDR_ARM, 0x123456789ABCDEF0ULL, 1); + val =3D qtest_readq_secure(qts, TEST_ADDR_ARM, 1); + g_assert_cmpuint(val, =3D=3D, 0x123456789ABCDEF0ULL); + + qtest_quit(qts); +} + +static void test_arm_memwrite_memread_secure(void) +{ + QTestState *qts; + uint8_t wbuf[16] =3D { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF }; + uint8_t rbuf[16]; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memwrite_secure(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), 0); + qtest_memread_secure(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), 0); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_secure(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), 1); + qtest_memread_secure(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), 1); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_quit(qts); +} + +static void test_arm_memset_secure(void) +{ + QTestState *qts; + uint8_t rbuf[16]; + size_t i; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memset_secure(qts, TEST_ADDR_ARM, 0x42, sizeof(rbuf), 0); + qtest_memread_secure(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), 0); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x42); + } + + qtest_memset_secure(qts, TEST_ADDR_ARM, 0x42, sizeof(rbuf), 1); + qtest_memread_secure(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), 1); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x42); + } + + qtest_quit(qts); +} + +/* ARM *_space tests (ARM-specific: Secure/NonSecure/Root/Realm) */ + +static void test_arm_writeb_readb_space(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + /* NonSecure space (secure=3D0) */ + qtest_writeb_space(qts, TEST_ADDR_ARM, 0x11, ARMSS_NonSecure); + val =3D qtest_readb_space(qts, TEST_ADDR_ARM, ARMSS_NonSecure); + g_assert_cmpuint(val, =3D=3D, 0x11); + + /* Realm space (secure=3D0) */ + qtest_writeb_space(qts, TEST_ADDR_ARM, 0x33, ARMSS_Realm); + val =3D qtest_readb_space(qts, TEST_ADDR_ARM, ARMSS_Realm); + g_assert_cmpuint(val, =3D=3D, 0x33); + + /* Secure space (secure=3D1) */ + qtest_writeb_space(qts, TEST_ADDR_ARM, 0x22, ARMSS_Secure); + val =3D qtest_readb_space(qts, TEST_ADDR_ARM, ARMSS_Secure); + g_assert_cmpuint(val, =3D=3D, 0x22); + + /* Root space (secure=3D1) */ + qtest_writeb_space(qts, TEST_ADDR_ARM, 0x44, ARMSS_Root); + val =3D qtest_readb_space(qts, TEST_ADDR_ARM, ARMSS_Root); + g_assert_cmpuint(val, =3D=3D, 0x44); + + qtest_quit(qts); +} + +static void test_arm_writew_readw_space(void) +{ + QTestState *qts; + uint16_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writew_space(qts, TEST_ADDR_ARM + 0x10, 0x1122, ARMSS_NonSecure); + val =3D qtest_readw_space(qts, TEST_ADDR_ARM + 0x10, ARMSS_NonSecure); + g_assert_cmpuint(val, =3D=3D, 0x1122); + + qtest_writew_space(qts, TEST_ADDR_ARM + 0x20, 0x3344, ARMSS_Realm); + val =3D qtest_readw_space(qts, TEST_ADDR_ARM + 0x20, ARMSS_Realm); + g_assert_cmpuint(val, =3D=3D, 0x3344); + + qtest_writew_space(qts, TEST_ADDR_ARM + 0x30, 0x5566, ARMSS_Secure); + val =3D qtest_readw_space(qts, TEST_ADDR_ARM + 0x30, ARMSS_Secure); + g_assert_cmpuint(val, =3D=3D, 0x5566); + + qtest_writew_space(qts, TEST_ADDR_ARM + 0x40, 0x7788, ARMSS_Root); + val =3D qtest_readw_space(qts, TEST_ADDR_ARM + 0x40, ARMSS_Root); + g_assert_cmpuint(val, =3D=3D, 0x7788); + + qtest_quit(qts); +} + +static void test_arm_writel_readl_space(void) +{ + QTestState *qts; + uint32_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writel_space(qts, TEST_ADDR_ARM + 0x50, 0x11223344, ARMSS_NonSec= ure); + val =3D qtest_readl_space(qts, TEST_ADDR_ARM + 0x50, ARMSS_NonSecure); + g_assert_cmpuint(val, =3D=3D, 0x11223344); + + qtest_writel_space(qts, TEST_ADDR_ARM + 0x60, 0x55667788, ARMSS_Realm); + val =3D qtest_readl_space(qts, TEST_ADDR_ARM + 0x60, ARMSS_Realm); + g_assert_cmpuint(val, =3D=3D, 0x55667788); + + qtest_writel_space(qts, TEST_ADDR_ARM + 0x70, 0x99AABBCC, ARMSS_Secure= ); + val =3D qtest_readl_space(qts, TEST_ADDR_ARM + 0x70, ARMSS_Secure); + g_assert_cmpuint(val, =3D=3D, 0x99AABBCC); + + qtest_writel_space(qts, TEST_ADDR_ARM + 0x80, 0xDDEEFF00, ARMSS_Root); + val =3D qtest_readl_space(qts, TEST_ADDR_ARM + 0x80, ARMSS_Root); + g_assert_cmpuint(val, =3D=3D, 0xDDEEFF00); + + qtest_quit(qts); +} + +static void test_arm_writeq_readq_space(void) +{ + QTestState *qts; + uint64_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writeq_space(qts, TEST_ADDR_ARM + 0x90, 0x1122334455667788ULL, + ARMSS_NonSecure); + val =3D qtest_readq_space(qts, TEST_ADDR_ARM + 0x90, ARMSS_NonSecure); + g_assert_cmpuint(val, =3D=3D, 0x1122334455667788ULL); + + qtest_writeq_space(qts, TEST_ADDR_ARM + 0xA0, 0x99AABBCCDDEEFF00ULL, + ARMSS_Realm); + val =3D qtest_readq_space(qts, TEST_ADDR_ARM + 0xA0, ARMSS_Realm); + g_assert_cmpuint(val, =3D=3D, 0x99AABBCCDDEEFF00ULL); + + qtest_writeq_space(qts, TEST_ADDR_ARM + 0xB0, 0x0123456789ABCDEFULL, + ARMSS_Secure); + val =3D qtest_readq_space(qts, TEST_ADDR_ARM + 0xB0, ARMSS_Secure); + g_assert_cmpuint(val, =3D=3D, 0x0123456789ABCDEFULL); + + qtest_writeq_space(qts, TEST_ADDR_ARM + 0xC0, 0xFEDCBA9876543210ULL, + ARMSS_Root); + val =3D qtest_readq_space(qts, TEST_ADDR_ARM + 0xC0, ARMSS_Root); + g_assert_cmpuint(val, =3D=3D, 0xFEDCBA9876543210ULL); + + qtest_quit(qts); +} + +static void test_arm_memwrite_memread_space(void) +{ + QTestState *qts; + uint8_t wbuf[8] =3D { 0xA1, 0xB2, 0xC3, 0xD4, 0xE5, 0xF6, 0x07, 0x18 }; + uint8_t rbuf[8]; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memwrite_space(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), ARMSS_Non= Secure); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_NonS= ecure); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_space(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), ARMSS_Rea= lm); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Real= m); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + + qtest_memwrite_space(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), ARMSS_Sec= ure); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Secu= re); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_space(qts, TEST_ADDR_ARM, wbuf, sizeof(wbuf), ARMSS_Roo= t); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Root= ); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_quit(qts); +} + +static void test_arm_memset_space(void) +{ + QTestState *qts; + uint8_t rbuf[8]; + size_t i; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memset_space(qts, TEST_ADDR_ARM, 0x99, sizeof(rbuf), ARMSS_NonSe= cure); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_NonS= ecure); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x99); + } + + qtest_memset_space(qts, TEST_ADDR_ARM, 0x99, sizeof(rbuf), ARMSS_Realm= ); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Real= m); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x99); + } + + qtest_memset_space(qts, TEST_ADDR_ARM, 0x99, sizeof(rbuf), ARMSS_Secur= e); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Secu= re); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x99); + } + + qtest_memset_space(qts, TEST_ADDR_ARM, 0x99, sizeof(rbuf), ARMSS_Root); + qtest_memread_space(qts, TEST_ADDR_ARM, rbuf, sizeof(rbuf), ARMSS_Root= ); + + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x99); + } + + qtest_quit(qts); +} + +/* Test new *_secure / *_space API in libqtest-single.h */ +static void test_arm_single_secure(void) +{ + uint8_t val; + uint8_t wbuf[4] =3D { 0x10, 0x20, 0x30, 0x40 }; + uint8_t rbuf[4]; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qtest_start(ARM_MACHINE_ARGS); + + writeb_secure(TEST_ADDR_ARM, 0x5A, 0); + val =3D readb_secure(TEST_ADDR_ARM, 0); + g_assert_cmpuint(val, =3D=3D, 0x5A); + + memwrite_secure(TEST_ADDR_ARM + 0x80, wbuf, sizeof(wbuf), 0); + memread_secure(TEST_ADDR_ARM + 0x80, rbuf, sizeof(rbuf), 0); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_end(); +} + +static void test_arm_single_space(void) +{ + uint32_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qtest_start(ARM_MACHINE_ARGS); + + writel_space(TEST_ADDR_ARM + 0x400, 0xA5A5A5A5, ARMSS_NonSecure); + val =3D readl_space(TEST_ADDR_ARM + 0x400, ARMSS_NonSecure); + g_assert_cmpuint(val, =3D=3D, 0xA5A5A5A5); + + writel_space(TEST_ADDR_ARM + 0x404, 0x1A2B3C4D, ARMSS_Realm); + val =3D readl_space(TEST_ADDR_ARM + 0x404, ARMSS_Realm); + g_assert_cmpuint(val, =3D=3D, 0x1A2B3C4D); + + writel_space(TEST_ADDR_ARM + 0x408, 0x55667788, ARMSS_Secure); + val =3D readl_space(TEST_ADDR_ARM + 0x408, ARMSS_Secure); + g_assert_cmpuint(val, =3D=3D, 0x55667788); + + writel_space(TEST_ADDR_ARM + 0x40C, 0xCCDDEEFF, ARMSS_Root); + val =3D readl_space(TEST_ADDR_ARM + 0x40C, ARMSS_Root); + g_assert_cmpuint(val, =3D=3D, 0xCCDDEEFF); + + qtest_end(); +} + +#define X86_MACHINE_ARGS "-machine pc -accel tcg" + +/* x86 *_secure tests */ +static void test_x86_writeb_readb_secure(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + /* secure=3D0: normal memory access (X86ASIdx_MEM) */ + qtest_writeb_secure(qts, TEST_ADDR_X86, 0x55, 0); + val =3D qtest_readb_secure(qts, TEST_ADDR_X86, 0); + g_assert_cmpuint(val, =3D=3D, 0x55); + + /* secure=3D1: SMM address space (X86ASIdx_SMM) */ + qtest_writeb_secure(qts, TEST_ADDR_X86, 0xAA, 1); + val =3D qtest_readb_secure(qts, TEST_ADDR_X86, 1); + g_assert_cmpuint(val, =3D=3D, 0xAA); + + qtest_quit(qts); +} + +static void test_x86_writew_readw_secure(void) +{ + QTestState *qts; + uint16_t val; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_writew_secure(qts, TEST_ADDR_X86, 0x1234, 0); + val =3D qtest_readw_secure(qts, TEST_ADDR_X86, 0); + g_assert_cmpuint(val, =3D=3D, 0x1234); + + qtest_writew_secure(qts, TEST_ADDR_X86, 0x5678, 1); + val =3D qtest_readw_secure(qts, TEST_ADDR_X86, 1); + g_assert_cmpuint(val, =3D=3D, 0x5678); + + qtest_quit(qts); +} + +static void test_x86_writel_readl_secure(void) +{ + QTestState *qts; + uint32_t val; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_writel_secure(qts, TEST_ADDR_X86, 0xDEADBEEF, 0); + val =3D qtest_readl_secure(qts, TEST_ADDR_X86, 0); + g_assert_cmpuint(val, =3D=3D, 0xDEADBEEF); + + qtest_writel_secure(qts, TEST_ADDR_X86, 0xCAFEBABE, 1); + val =3D qtest_readl_secure(qts, TEST_ADDR_X86, 1); + g_assert_cmpuint(val, =3D=3D, 0xCAFEBABE); + + qtest_quit(qts); +} + +static void test_x86_writeq_readq_secure(void) +{ + QTestState *qts; + uint64_t val; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_writeq_secure(qts, TEST_ADDR_X86, 0x123456789ABCDEF0ULL, 0); + val =3D qtest_readq_secure(qts, TEST_ADDR_X86, 0); + g_assert_cmpuint(val, =3D=3D, 0x123456789ABCDEF0ULL); + + qtest_writeq_secure(qts, TEST_ADDR_X86, 0xFEDCBA9876543210ULL, 1); + val =3D qtest_readq_secure(qts, TEST_ADDR_X86, 1); + g_assert_cmpuint(val, =3D=3D, 0xFEDCBA9876543210ULL); + + qtest_quit(qts); +} + +static void test_x86_memwrite_memread_secure(void) +{ + QTestState *qts; + uint8_t wbuf[16] =3D { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF }; + uint8_t rbuf[16]; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_memwrite_secure(qts, TEST_ADDR_X86, wbuf, sizeof(wbuf), 0); + qtest_memread_secure(qts, TEST_ADDR_X86, rbuf, sizeof(rbuf), 0); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_secure(qts, TEST_ADDR_X86 + 0x100, wbuf, sizeof(wbuf), = 1); + qtest_memread_secure(qts, TEST_ADDR_X86 + 0x100, rbuf, sizeof(rbuf), 1= ); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_quit(qts); +} + +static void test_x86_memset_secure(void) +{ + QTestState *qts; + uint8_t rbuf[16]; + size_t i; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_memset_secure(qts, TEST_ADDR_X86, 0x42, sizeof(rbuf), 0); + qtest_memread_secure(qts, TEST_ADDR_X86, rbuf, sizeof(rbuf), 0); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x42); + } + + qtest_memset_secure(qts, TEST_ADDR_X86 + 0x100, 0xBE, sizeof(rbuf), 1); + qtest_memread_secure(qts, TEST_ADDR_X86 + 0x100, rbuf, sizeof(rbuf), 1= ); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0xBE); + } + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + /* ARM *_secure tests (secure/non-secure, requires secure=3Don) */ + qtest_add_func("/qtest/arm/secure/writeb_readb", + test_arm_writeb_readb_secure); + qtest_add_func("/qtest/arm/secure/writew_readw", + test_arm_writew_readw_secure); + qtest_add_func("/qtest/arm/secure/writel_readl", + test_arm_writel_readl_secure); + qtest_add_func("/qtest/arm/secure/writeq_readq", + test_arm_writeq_readq_secure); + qtest_add_func("/qtest/arm/secure/memwrite_memread", + test_arm_memwrite_memread_secure); + qtest_add_func("/qtest/arm/secure/memset", + test_arm_memset_secure); + + /* ARM *_space tests (Secure/NonSecure/Root/Realm, requires secure=3Do= n) */ + qtest_add_func("/qtest/arm/space/writeb_readb", + test_arm_writeb_readb_space); + qtest_add_func("/qtest/arm/space/writew_readw", + test_arm_writew_readw_space); + qtest_add_func("/qtest/arm/space/writel_readl", + test_arm_writel_readl_space); + qtest_add_func("/qtest/arm/space/writeq_readq", + test_arm_writeq_readq_space); + qtest_add_func("/qtest/arm/space/memwrite_memread", + test_arm_memwrite_memread_space); + qtest_add_func("/qtest/arm/space/memset", + test_arm_memset_space); + qtest_add_func("/qtest/arm/secure/single_shortcuts", + test_arm_single_secure); + qtest_add_func("/qtest/arm/space/single_shortcuts", + test_arm_single_space); + + /* x86 *_secure tests (SMM address space, X86ASIdx_SMM =3D 1) */ + qtest_add_func("/qtest/x86/secure/writeb_readb", + test_x86_writeb_readb_secure); + qtest_add_func("/qtest/x86/secure/writew_readw", + test_x86_writew_readw_secure); + qtest_add_func("/qtest/x86/secure/writel_readl", + test_x86_writel_readl_secure); + qtest_add_func("/qtest/x86/secure/writeq_readq", + test_x86_writeq_readq_secure); + qtest_add_func("/qtest/x86/secure/memwrite_memread", + test_x86_memwrite_memread_secure); + qtest_add_func("/qtest/x86/secure/memset", + test_x86_memset_secure); + + return g_test_run(); +} --=20 2.34.1