From nobody Sun Apr 12 02:49:54 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771669186504943.0458882799161; Sat, 21 Feb 2026 02:19:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vtk5I-0004hZ-Jc; Sat, 21 Feb 2026 05:19:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vtk5G-0004M4-F2; Sat, 21 Feb 2026 05:19:34 -0500 Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net ([209.97.181.73]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vtk5E-0004iC-Qs; Sat, 21 Feb 2026 05:19:34 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwBnb2OyhplprLBVBw--.4868S2; Sat, 21 Feb 2026 18:19:30 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwDnQO6whplphk4cAA--.49134S3; Sat, 21 Feb 2026 18:19:28 +0800 (CST) From: Tao Tang To: Eric Auger , Peter Maydell , "Michael S . Tsirkin" , Marcel Apfelbaum Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mostafa Saleh , Chao Liu , Tao Tang Subject: [RFC v4 30/31] hw/arm/smmuv3: Add secure bank migration and secure-impl property Date: Sat, 21 Feb 2026 18:19:26 +0800 Message-Id: <20260221101926.2997959-1-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> References: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwDnQO6whplphk4cAA--.49134S3 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQANBWmYzyUAUQAAsD Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoWxXFykZF1rGr17Xw1UKr13XFb_yoWrXF17pr s8C3Z8GryDGF47Zr43Jw4rCFs5Cr4rGF4YkrZrCFZ3ta1kt3y7Xrnrt3y8u3s7JrWUXw47 uF1xuFZrJw4UArJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.97.181.73; envelope-from=tangtao1634@phytium.com.cn; helo=zg8tmja5ljk3lje4ms43mwaa.icoremail.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1771669187211158500 Content-Type: text/plain; charset="utf-8" Add a secure-impl device property and advertise it through S_IDR1.SECURE_IMPL. Usage: -global arm-smmuv3,secure-impl=3Dtrue Add the smmuv3/bank_s migration subsection for the secure register bank. Serialize secure bank state including GBPA, IRQ config, stream table and queue state. Signed-off-by: Tao Tang Reviewed-by: Pierrick Bouvier --- hw/arm/smmuv3.c | 56 +++++++++++++++++++++++++++++++++++++++++ include/hw/arm/smmuv3.h | 2 ++ 2 files changed, 58 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index f0fbc5fc96b..678cbd584e2 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -327,6 +327,7 @@ static void smmuv3_init_id_regs(SMMUv3State *s) memset(sbk->idr, 0, sizeof(sbk->idr)); sbk->idr[0] =3D FIELD_DP32(bk->idr[0], S_IDR0, STALL_MODEL, 1); /* No = stall */ sbk->idr[1] =3D FIELD_DP32(sbk->idr[1], S_IDR1, S_SIDSIZE, SMMU_IDR1_S= IDSIZE); + sbk->idr[1] =3D FIELD_DP32(sbk->idr[1], S_IDR1, SECURE_IMPL, s->secure= _impl); smmuv3_accel_idr_override(s); } =20 @@ -2632,6 +2633,54 @@ static const VMStateDescription vmstate_smmuv3_queue= =3D { }, }; =20 +static const VMStateDescription vmstate_smmuv3_secure_bank =3D { + .name =3D "smmuv3_secure_bank", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(features, SMMUv3RegBank), + VMSTATE_UINT8(sid_split, SMMUv3RegBank), + VMSTATE_UINT32_ARRAY(cr, SMMUv3RegBank, 3), + VMSTATE_UINT32(cr0ack, SMMUv3RegBank), + VMSTATE_UINT32(gbpa, SMMUv3RegBank), + VMSTATE_UINT32(irq_ctrl, SMMUv3RegBank), + VMSTATE_UINT32(gerror, SMMUv3RegBank), + VMSTATE_UINT32(gerrorn, SMMUv3RegBank), + VMSTATE_UINT64(gerror_irq_cfg0, SMMUv3RegBank), + VMSTATE_UINT32(gerror_irq_cfg1, SMMUv3RegBank), + VMSTATE_UINT32(gerror_irq_cfg2, SMMUv3RegBank), + VMSTATE_UINT64(strtab_base, SMMUv3RegBank), + VMSTATE_UINT32(strtab_base_cfg, SMMUv3RegBank), + VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3RegBank), + VMSTATE_UINT32(eventq_irq_cfg1, SMMUv3RegBank), + VMSTATE_UINT32(eventq_irq_cfg2, SMMUv3RegBank), + VMSTATE_STRUCT(cmdq, SMMUv3RegBank, 0, + vmstate_smmuv3_queue, SMMUQueue), + VMSTATE_STRUCT(eventq, SMMUv3RegBank, 0, + vmstate_smmuv3_queue, SMMUQueue), + VMSTATE_END_OF_LIST(), + }, +}; + +static bool smmuv3_secure_bank_needed(void *opaque) +{ + SMMUv3State *s =3D opaque; + + return s->secure_impl; +} + +static const VMStateDescription vmstate_smmuv3_bank_s =3D { + .name =3D "smmuv3/bank_s", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D smmuv3_secure_bank_needed, + .fields =3D (const VMStateField[]) { + VMSTATE_STRUCT(bank[SMMU_SEC_SID_S], SMMUv3State, 0, + vmstate_smmuv3_secure_bank, SMMUv3RegBank), + VMSTATE_END_OF_LIST(), + }, +}; + static bool smmuv3_gbpa_needed(void *opaque) { SMMUv3State *s =3D opaque; @@ -2686,6 +2735,7 @@ static const VMStateDescription vmstate_smmuv3 =3D { }, .subsections =3D (const VMStateDescription * const []) { &vmstate_gbpa, + &vmstate_smmuv3_bank_s, NULL } }; @@ -2707,6 +2757,12 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), + /* + * SECURE_IMPL field in S_IDR1 register. + * Indicates whether secure state is implemented. + * Defaults to false (0) + */ + DEFINE_PROP_BOOL("secure-impl", SMMUv3State, secure_impl, false), }; =20 static void smmuv3_instance_init(Object *obj) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index d07bdfa1f27..79ce7c754c4 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -78,6 +78,8 @@ struct SMMUv3State { bool ats; uint8_t oas; uint8_t ssidsize; + + bool secure_impl; }; =20 typedef enum { --=20 2.34.1