From nobody Sun Apr 12 02:50:39 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177166909158064.45285664007895; Sat, 21 Feb 2026 02:18:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vtk3f-0000Mp-0z; Sat, 21 Feb 2026 05:17:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vtk3d-0000Kr-EI; Sat, 21 Feb 2026 05:17:53 -0500 Received: from sgoci-sdnproxy-4.icoremail.net ([129.150.39.64]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vtk3a-0000em-LN; Sat, 21 Feb 2026 05:17:53 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwCHoqhJhplpRa9VBw--.6667S2; Sat, 21 Feb 2026 18:17:45 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwCn_epIhplpdE4cAA--.34722S3; Sat, 21 Feb 2026 18:17:44 +0800 (CST) From: Tao Tang To: Eric Auger , Peter Maydell , "Michael S . Tsirkin" , Marcel Apfelbaum Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mostafa Saleh , Chao Liu , Tao Tang Subject: [RFC v4 20/31] hw/arm/smmu: Make CMDQ invalidation security-state aware Date: Sat, 21 Feb 2026 18:17:41 +0800 Message-Id: <20260221101741.2995271-1-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> References: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwCn_epIhplpdE4cAA--.34722S3 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQANBWmYzyUAPQAAsv Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvAXoW3uw17XrW5XFy8XFWUWr45KFg_yoW8XrW3Ko WrJrWjgrW8Jr12gFn2vFn3GFW7ZryqyayUWr15Z3ya93ZxtF15tFyxtr4rXa1FyF4UJFWF vF95WrZ7XFy5AFyfn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3UbIjqfuFe4nvWSU8nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UU UUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.150.39.64; envelope-from=tangtao1634@phytium.com.cn; helo=sgoci-sdnproxy-4.icoremail.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1771669105170158500 Content-Type: text/plain; charset="utf-8" Refactor CMDQ invalidation paths to carry security state and apply cache invalidation per sec_sid instead of globally. Extend common IOTLB/config invalidation helpers with sec_sid filtering, while keeping SMMU_SEC_SID_NUM as the full-invalidate mode. In smmuv3, propagate sec_sid/ssec through CFGI and TLBI handling, and gate VMID usage on queue stage-2 capability (including SEL2 for secure CMDQ). Update tracepoints to include ssec for better observability. Signed-off-by: Tao Tang --- hw/arm/smmu-common.c | 96 ++++++++++++++++++++++++++++++++---- hw/arm/smmuv3.c | 67 ++++++++++++++++++------- hw/arm/trace-events | 6 +-- include/hw/arm/smmu-common.h | 8 +-- 4 files changed, 144 insertions(+), 33 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index bb43430cc3b..5dece2024a4 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -201,7 +201,7 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg= , SMMUTLBEntry *new) uint8_t tg =3D (new->granule - 10) / 2; =20 if (g_hash_table_size(bs->iotlb) >=3D SMMU_IOTLB_MAX_SIZE) { - smmu_iotlb_inv_all(bs); + smmu_iotlb_inv_all(bs, SMMU_SEC_SID_NUM); } =20 *key =3D smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, new->entry.iov= a, @@ -211,10 +211,23 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *c= fg, SMMUTLBEntry *new) g_hash_table_insert(bs->iotlb, key, new); } =20 -void smmu_iotlb_inv_all(SMMUState *s) +static gboolean smmu_hash_remove_by_sec_sid(gpointer key, gpointer value, + gpointer user_data) +{ + SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; + SMMUSecSID *sec_sid =3D (SMMUSecSID *)user_data; + + return SMMU_IOTLB_SEC_SID(*iotlb_key) =3D=3D *sec_sid; +} + +void smmu_iotlb_inv_all(SMMUState *s, SMMUSecSID sec_sid) { trace_smmu_iotlb_inv_all(); - g_hash_table_remove_all(s->iotlb); + if (sec_sid =3D=3D SMMU_SEC_SID_NUM) { + g_hash_table_remove_all(s->iotlb); + return; + } + g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_sec_sid, &se= c_sid); } =20 static gboolean smmu_hash_remove_by_asid_vmid(gpointer key, gpointer value, @@ -292,6 +305,16 @@ static gboolean smmu_hash_remove_by_vmid_ipa(gpointer = key, gpointer value, ((entry->iova & ~info->mask) =3D=3D info->iova); } =20 +typedef struct SMMUConfigInvRangeInfo { + SMMUSIDRange sid_range; + SMMUSecSID sec_sid; +} SMMUConfigInvRangeInfo; + +typedef struct SMMUConfigInvSdevInfo { + SMMUDevice *sdev; + SMMUSecSID sec_sid; +} SMMUConfigInvSdevInfo; + static gboolean smmu_hash_remove_by_sid_range(gpointer key, gpointer value, gpointer user_= data) { @@ -307,11 +330,41 @@ smmu_hash_remove_by_sid_range(gpointer key, gpointer = value, gpointer user_data) return true; } =20 -void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range) +static gboolean +smmu_hash_remove_by_sid_range_sec(gpointer key, gpointer value, + gpointer user_data) +{ + SMMUConfigKey *config_key =3D (SMMUConfigKey *)key; + SMMUConfigInvRangeInfo *info =3D (SMMUConfigInvRangeInfo *)user_data; + SMMUDevice *sdev =3D config_key->sdev; + uint32_t sid =3D smmu_get_sid(sdev); + + if (config_key->sec_sid !=3D info->sec_sid) { + return false; + } + if (sid < info->sid_range.start || sid > info->sid_range.end) { + return false; + } + trace_smmu_config_cache_inv(sid); + return true; +} + +void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range, + SMMUSecSID sec_sid) { + SMMUConfigInvRangeInfo info =3D { + .sid_range =3D sid_range, + .sec_sid =3D sec_sid, + }; + trace_smmu_configs_inv_sid_range(sid_range.start, sid_range.end); - g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sid_range, - &sid_range); + if (sec_sid =3D=3D SMMU_SEC_SID_NUM) { + g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sid_ra= nge, + &sid_range); + return; + } + g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sid_range_= sec, + &info); } =20 static gboolean smmu_hash_remove_by_sdev(gpointer key, gpointer value, @@ -327,9 +380,35 @@ static gboolean smmu_hash_remove_by_sdev(gpointer key,= gpointer value, return true; } =20 -void smmu_configs_inv_sdev(SMMUState *s, SMMUDevice *sdev) +static gboolean smmu_hash_remove_by_sdev_sec(gpointer key, gpointer value, + gpointer user_data) { - g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sdev, sdev= ); + SMMUConfigKey *config_key =3D (SMMUConfigKey *)key; + SMMUConfigInvSdevInfo *info =3D (SMMUConfigInvSdevInfo *)user_data; + + if (config_key->sdev !=3D info->sdev) { + return false; + } + if (config_key->sec_sid !=3D info->sec_sid) { + return false; + } + trace_smmu_config_cache_inv(smmu_get_sid(info->sdev)); + return true; +} + +void smmu_configs_inv_sdev(SMMUState *s, SMMUDevice *sdev, + SMMUSecSID sec_sid) +{ + SMMUConfigInvSdevInfo info =3D { + .sdev =3D sdev, + .sec_sid =3D sec_sid, + }; + + if (sec_sid =3D=3D SMMU_SEC_SID_NUM) { + g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sdev, = sdev); + return; + } + g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sdev_sec, = &info); } =20 void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, @@ -1193,4 +1272,3 @@ static void smmu_base_register_types(void) } =20 type_init(smmu_base_register_types) - diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index d4c58c0c724..29e862b8ae3 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -959,12 +959,13 @@ static SMMUTransCfg *smmuv3_get_config(SMMUDevice *sd= ev, SMMUEventInfo *event, return cfg; } =20 -static void smmuv3_flush_config(SMMUDevice *sdev) +/* Flush all config caches when sec_sid =3D=3D SMMU_SEC_SID_NUM */ +static void smmuv3_flush_config(SMMUDevice *sdev, SMMUSecSID sec_sid) { SMMUv3State *s =3D sdev->smmu; SMMUState *bc =3D &s->smmu_state; =20 - smmu_configs_inv_sdev(bc, sdev); + smmu_configs_inv_sdev(bc, sdev, sec_sid); } =20 /* Do translation with TLB lookup. */ @@ -1289,7 +1290,7 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, int vmid, } =20 static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage, - SMMUSecSID sec_sid) + SMMUSecSID sec_sid, bool use_vmid) { dma_addr_t end, addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); @@ -1302,10 +1303,8 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cm= d, SMMUStage stage, uint64_t num_pages; uint8_t granule; int asid =3D -1; - SMMUv3State *smmuv3 =3D ARM_SMMUV3(s); =20 - /* Only consider VMID if stage-2 is supported. */ - if (STAGE2_SUPPORTED(smmuv3)) { + if (use_vmid) { vmid =3D CMD_VMID(cmd); } =20 @@ -1351,6 +1350,25 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cm= d, SMMUStage stage, } } =20 +static inline bool smmu_cmdq_stage2_supported(SMMUv3State *s, SMMUSecSID s= ec_sid) +{ + /* IDR0.S2P: Stage 2 translation supported */ + bool s2p =3D STAGE2_SUPPORTED(s); + if (!s2p) { + return false; + } + + /* + * For Secure Command queue, Secure stage 2 is additionally gated by S= EL2 + * (SEL2 is 0 if S2P is 0). + */ + if (sec_sid =3D=3D SMMU_SEC_SID_S) { + return FIELD_EX32(s->bank[SMMU_SEC_SID_S].idr[1], S_IDR1, SEL2); + } + + return true; +} + static int smmuv3_cmdq_consume(SMMUv3State *s, Error **errp, SMMUSecSID se= c_sid) { SMMUState *bs =3D ARM_SMMU(s); @@ -1362,6 +1380,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp, SMMUSecSID sec_sid) AddressSpace *as =3D smmu_get_address_space(bs, sec_sid); /* Secure AddressSpace must be available, assert if not. */ g_assert(as); + bool queue_stage2_supported =3D smmu_cmdq_stage2_supported(s, sec_sid); =20 if (!smmuv3_cmdq_enabled(s, sec_sid)) { return 0; @@ -1376,6 +1395,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp, SMMUSecSID sec_sid) while (!smmuv3_q_empty(q)) { uint32_t pending =3D bank->gerror ^ bank->gerrorn; Cmd cmd; + SMMUSecSID ssec =3D SMMU_SEC_SID_NS; =20 trace_smmuv3_cmdq_consume(sec_sid, Q_PROD(q), Q_CONS(q), Q_PROD_WRAP(q), Q_CONS_WRAP(q)); @@ -1399,6 +1419,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp, SMMUSecSID sec_sid) cmd_error =3D SMMU_CERROR_ILL; break; } + ssec =3D SMMU_SEC_SID_S; } =20 type =3D CMD_TYPE(&cmd); @@ -1424,12 +1445,12 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Erro= r **errp, SMMUSecSID sec_sid) break; } =20 - trace_smmuv3_cmdq_cfgi_ste(sid); + trace_smmuv3_cmdq_cfgi_ste(ssec, sid); if (!smmuv3_accel_install_ste(s, sdev, sid, errp)) { cmd_error =3D SMMU_CERROR_ILL; break; } - smmuv3_flush_config(sdev); + smmuv3_flush_config(sdev, ssec); =20 break; } @@ -1443,12 +1464,12 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Erro= r **errp, SMMUSecSID sec_sid) sid_range.start =3D sid & ~mask; sid_range.end =3D sid_range.start + mask; =20 - trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.en= d); + trace_smmuv3_cmdq_cfgi_ste_range(ssec, sid_range.start, sid_ra= nge.end); if (!smmuv3_accel_install_ste_range(s, &sid_range, errp)) { cmd_error =3D SMMU_CERROR_ILL; break; } - smmu_configs_inv_sid_range(bs, sid_range); + smmu_configs_inv_sid_range(bs, sid_range, ssec); break; } case SMMU_CMD_CFGI_CD: @@ -1470,8 +1491,8 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp, SMMUSecSID sec_sid) break; } =20 - trace_smmuv3_cmdq_cfgi_cd(sid); - smmuv3_flush_config(sdev); + trace_smmuv3_cmdq_cfgi_cd(ssec, sid); + smmuv3_flush_config(sdev, ssec); if (!smmuv3_accel_issue_inv_cmd(s, &cmd, sdev, errp)) { cmd_error =3D SMMU_CERROR_ILL; break; @@ -1492,7 +1513,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp, SMMUSecSID sec_sid) * VMID is only matched when stage 2 is supported, otherwise s= et it * to -1 as the value used for stage-1 only VMIDs. */ - if (STAGE2_SUPPORTED(s)) { + if (queue_stage2_supported) { vmid =3D CMD_VMID(&cmd); } =20 @@ -1518,18 +1539,27 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Erro= r **errp, SMMUSecSID sec_sid) * If stage-2 is supported, invalidate for this VMID only, oth= erwise * invalidate the whole thing. */ - if (STAGE2_SUPPORTED(s)) { + if (queue_stage2_supported) { vmid =3D CMD_VMID(&cmd); trace_smmuv3_cmdq_tlbi_nh(sec_sid, vmid); smmu_iotlb_inv_vmid_s1(bs, vmid, sec_sid); break; } - QEMU_FALLTHROUGH; + trace_smmuv3_cmdq_tlbi_nh(sec_sid, vmid); + smmu_inv_notifiers_all(&s->smmu_state); + smmu_iotlb_inv_all(bs, sec_sid); + break; } case SMMU_CMD_TLBI_NSNH_ALL: trace_smmuv3_cmdq_tlbi_nsnh(); smmu_inv_notifiers_all(&s->smmu_state); - smmu_iotlb_inv_all(bs); + /* + * According to (IHI 0070G.b) 4.4.4.1 CMD_TLBI_NSNH_ALL, Page = 194: + * "When issuing to the Realm programming interface, even thou= gh + * this command has NS in its name, it only applies to Realm e= ntries." + */ + smmu_iotlb_inv_all(bs, sec_sid > SMMU_SEC_SID_S ? + sec_sid : SMMU_SEC_SID_NS); if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, errp)) { cmd_error =3D SMMU_CERROR_ILL; break; @@ -1541,7 +1571,8 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp, SMMUSecSID sec_sid) cmd_error =3D SMMU_CERROR_ILL; break; } - smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1, SMMU_SEC_SID_NS); + smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1, sec_sid, + queue_stage2_supported); if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, errp)) { cmd_error =3D SMMU_CERROR_ILL; break; @@ -1570,7 +1601,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp, SMMUSecSID sec_sid) * As currently only either s1 or s2 are supported * we can reuse same function for s2. */ - smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2, SMMU_SEC_SID_NS); + smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2, SMMU_SEC_SID_NS, tr= ue); break; case SMMU_CMD_ATC_INV: { diff --git a/hw/arm/trace-events b/hw/arm/trace-events index ca8485c96af..64f308a8d35 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -51,9 +51,9 @@ smmuv3_translate_success(const char *n, uint16_t sid, uin= t64_t iova, uint64_t tr smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64 smmuv3_decode_cd(uint32_t oas) "oas=3D%d" smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz= , bool had) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d had:%d" -smmuv3_cmdq_cfgi_ste(int streamid) "streamid=3D 0x%x" -smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=3D0x%x - end=3D0x%x" -smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=3D0x%x" +smmuv3_cmdq_cfgi_ste(int ssec, int streamid) "ssec=3D%d streamid=3D 0x%x" +smmuv3_cmdq_cfgi_ste_range(int ssec, int start, int end) "ssec=3D%d start= =3D0x%x - end=3D0x%x" +smmuv3_cmdq_cfgi_cd(int ssec, uint32_t sid) "ssec=3D%d sid=3D0x%x" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid=3D0x%x (hits=3D%d, misses=3D%d, hit ra= te=3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid=3D0x%x (hits=3D%d, misses=3D%d, hit = rate=3D%d)" smmuv3_range_inval(int sec_sid, int vmid, int asid, uint64_t addr, uint8_t= tg, uint64_t num_pages, uint8_t ttl, bool leaf, int stage) "sec_sid=3D%d v= mid=3D%d asid=3D%d addr=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" ttl= =3D%d leaf=3D%d stage=3D%d" diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 7d1d0936921..d05cf6ae53b 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -259,7 +259,7 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg= , SMMUTLBEntry *entry); SMMUIOTLBKey smmu_get_iotlb_key(int asid, int vmid, uint64_t iova, uint8_t tg, uint8_t level, SMMUSecSID sec_= sid); SMMUConfigKey smmu_get_config_key(SMMUDevice *sdev, SMMUSecSID sec_sid); -void smmu_iotlb_inv_all(SMMUState *s); +void smmu_iotlb_inv_all(SMMUState *s, SMMUSecSID sec_sid); void smmu_iotlb_inv_asid_vmid(SMMUState *s, int asid, int vmid, SMMUSecSID sec_sid); void smmu_iotlb_inv_vmid(SMMUState *s, int vmid, SMMUSecSID sec_sid); @@ -270,8 +270,10 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int v= mid, dma_addr_t iova, void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg, uint64_t num_pages, uint8_t ttl, SMMUSecSID sec_sid); -void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range); -void smmu_configs_inv_sdev(SMMUState *s, SMMUDevice *sdev); +void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range, + SMMUSecSID sec_sid); +void smmu_configs_inv_sdev(SMMUState *s, SMMUDevice *sdev, + SMMUSecSID sec_sid); /* Unmap the range of all the notifiers registered to any IOMMU mr */ void smmu_inv_notifiers_all(SMMUState *s); =20 --=20 2.34.1