From nobody Sun Apr 12 02:51:00 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17716690891681000.1167407887531; Sat, 21 Feb 2026 02:18:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vtk31-000796-Jf; Sat, 21 Feb 2026 05:17:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vtk30-00075p-ER; Sat, 21 Feb 2026 05:17:14 -0500 Received: from sgoci-sdnproxy-4.icoremail.net ([129.150.39.64]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vtk2x-0006Nf-9r; Sat, 21 Feb 2026 05:17:14 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-6 (Coremail) with SMTP id AQAAfwAHXdAihplp6x5zAA--.3190S2; Sat, 21 Feb 2026 18:17:06 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwC3DuwdhplpbE4cAA--.34817S3; Sat, 21 Feb 2026 18:17:02 +0800 (CST) From: Tao Tang To: Eric Auger , Peter Maydell , "Michael S . Tsirkin" , Marcel Apfelbaum Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mostafa Saleh , Chao Liu , Tao Tang Subject: [RFC v4 15/31] hw/arm/smmuv3: Tag IOTLB cache keys with SEC_SID Date: Sat, 21 Feb 2026 18:16:57 +0800 Message-Id: <20260221101657.2994097-1-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> References: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwC3DuwdhplpbE4cAA--.34817S3 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQANBWmYzyUAMwAAsh Authentication-Results: hzbj-icmmx-6; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvAXoW3ZFW7Aw43WF4DtF4rXFyrWFg_yoW8AFWrCo WxG3Wjqr48J3W7WFyqkFs7JFy2va4Dtay5Zw4rX3yag3ZxKrn8tFWxtr4fXF4Fgr4UAF40 vF95ArW8XF1UC3s3n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3UbIjqfuFe4nvWSU8nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UU UUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.150.39.64; envelope-from=tangtao1634@phytium.com.cn; helo=sgoci-sdnproxy-4.icoremail.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1771669091013158500 Content-Type: text/plain; charset="utf-8" To prevent aliasing between secure and non-secure translations for the same address space, the IOTLB lookup key must incorporate the security state of the transaction. This commit: - expands SMMUIOTLBKey with SEC_SID field for cache key differentiation - extends SMMUIOTLBPageInvInfo with SEC_SID for invalidation filtering - updates all IOTLB invalidation helpers (smmu_iotlb_inv_iova, smmu_iotlb_inv_ipa, smmu_iotlb_inv_asid_vmid, smmu_iotlb_inv_vmid, smmu_iotlb_inv_vmid_s1) to accept and filter by SEC_SID - plumbs SEC_SID through smmuv3_range_inval for TLB invalidation - enhances trace events to include SEC_SID for better debugging This ensures that secure and non-secure TLB entries are treated as distinct entities within the cache, preventing TLB pollution between different worlds. Signed-off-by: Tao Tang Reviewed-by: Pierrick Bouvier --- hw/arm/smmu-common.c | 80 ++++++++++++++++++++++++------------ hw/arm/smmu-internal.h | 2 + hw/arm/smmuv3.c | 36 ++++++++-------- hw/arm/trace-events | 12 +++--- include/hw/arm/smmu-common.h | 16 +++++--- 5 files changed, 92 insertions(+), 54 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 84e71df6767..bb43430cc3b 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -95,7 +95,7 @@ static guint smmu_iotlb_key_hash(gconstpointer v) =20 /* Jenkins hash */ a =3D b =3D c =3D JHASH_INITVAL + sizeof(*key); - a +=3D key->asid + key->vmid + key->level + key->tg; + a +=3D key->asid + key->vmid + key->level + key->tg + key->sec_sid; b +=3D extract64(key->iova, 0, 32); c +=3D extract64(key->iova, 32, 32); =20 @@ -111,14 +111,15 @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1= , gconstpointer v2) =20 return (k1->asid =3D=3D k2->asid) && (k1->iova =3D=3D k2->iova) && (k1->level =3D=3D k2->level) && (k1->tg =3D=3D k2->tg) && - (k1->vmid =3D=3D k2->vmid); + (k1->vmid =3D=3D k2->vmid) && (k1->sec_sid =3D=3D k2->sec_sid); } =20 SMMUIOTLBKey smmu_get_iotlb_key(int asid, int vmid, uint64_t iova, - uint8_t tg, uint8_t level) + uint8_t tg, uint8_t level, + SMMUSecSID sec_sid) { SMMUIOTLBKey key =3D {.asid =3D asid, .vmid =3D vmid, .iova =3D iova, - .tg =3D tg, .level =3D level}; + .tg =3D tg, .level =3D level, .sec_sid =3D sec_sid= }; =20 return key; } @@ -140,7 +141,7 @@ static SMMUTLBEntry *smmu_iotlb_lookup_all_levels(SMMUS= tate *bs, SMMUIOTLBKey key; =20 key =3D smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, - iova & ~mask, tg, level); + iova & ~mask, tg, level, cfg->sec_sid); entry =3D g_hash_table_lookup(bs->iotlb, &key); if (entry) { break; @@ -204,7 +205,7 @@ void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg= , SMMUTLBEntry *new) } =20 *key =3D smmu_get_iotlb_key(cfg->asid, cfg->s2cfg.vmid, new->entry.iov= a, - tg, new->level); + tg, new->level, cfg->sec_sid); trace_smmu_iotlb_insert(cfg->asid, cfg->s2cfg.vmid, new->entry.iova, tg, new->level); g_hash_table_insert(bs->iotlb, key, new); @@ -223,26 +224,29 @@ static gboolean smmu_hash_remove_by_asid_vmid(gpointe= r key, gpointer value, SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; =20 return (SMMU_IOTLB_ASID(*iotlb_key) =3D=3D info->asid) && - (SMMU_IOTLB_VMID(*iotlb_key) =3D=3D info->vmid); + (SMMU_IOTLB_VMID(*iotlb_key) =3D=3D info->vmid) && + (SMMU_IOTLB_SEC_SID(*iotlb_key) =3D=3D info->sec_sid); } =20 static gboolean smmu_hash_remove_by_vmid(gpointer key, gpointer value, gpointer user_data) { - int vmid =3D *(int *)user_data; + SMMUIOTLBPageInvInfo *info =3D (SMMUIOTLBPageInvInfo *)user_data; SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; =20 - return SMMU_IOTLB_VMID(*iotlb_key) =3D=3D vmid; + return (SMMU_IOTLB_VMID(*iotlb_key) =3D=3D info->vmid) && + (SMMU_IOTLB_SEC_SID(*iotlb_key) =3D=3D info->sec_sid); } =20 static gboolean smmu_hash_remove_by_vmid_s1(gpointer key, gpointer value, gpointer user_data) { - int vmid =3D *(int *)user_data; + SMMUIOTLBPageInvInfo *info =3D (SMMUIOTLBPageInvInfo *)user_data; SMMUIOTLBKey *iotlb_key =3D (SMMUIOTLBKey *)key; =20 - return (SMMU_IOTLB_VMID(*iotlb_key) =3D=3D vmid) && - (SMMU_IOTLB_ASID(*iotlb_key) >=3D 0); + return (SMMU_IOTLB_VMID(*iotlb_key) =3D=3D info->vmid) && + (SMMU_IOTLB_ASID(*iotlb_key) >=3D 0) && + (SMMU_IOTLB_SEC_SID(*iotlb_key) =3D=3D info->sec_sid); } =20 static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer = value, @@ -259,6 +263,9 @@ static gboolean smmu_hash_remove_by_asid_vmid_iova(gpoi= nter key, gpointer value, if (info->vmid >=3D 0 && info->vmid !=3D SMMU_IOTLB_VMID(iotlb_key)) { return false; } + if (info->sec_sid !=3D SMMU_IOTLB_SEC_SID(iotlb_key)) { + return false; + } return ((info->iova & ~entry->addr_mask) =3D=3D entry->iova) || ((entry->iova & ~info->mask) =3D=3D info->iova); } @@ -278,6 +285,9 @@ static gboolean smmu_hash_remove_by_vmid_ipa(gpointer k= ey, gpointer value, if (info->vmid !=3D SMMU_IOTLB_VMID(iotlb_key)) { return false; } + if (info->sec_sid !=3D SMMU_IOTLB_SEC_SID(iotlb_key)) { + return false; + } return ((info->iova & ~entry->addr_mask) =3D=3D entry->iova) || ((entry->iova & ~info->mask) =3D=3D info->iova); } @@ -323,13 +333,15 @@ void smmu_configs_inv_sdev(SMMUState *s, SMMUDevice *= sdev) } =20 void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, - uint8_t tg, uint64_t num_pages, uint8_t ttl) + uint8_t tg, uint64_t num_pages, uint8_t ttl, + SMMUSecSID sec_sid) { /* if tg is not set we use 4KB range invalidation */ uint8_t granule =3D tg ? tg * 2 + 10 : 12; =20 if (ttl && (num_pages =3D=3D 1) && (asid >=3D 0)) { - SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, vmid, iova, tg, ttl); + SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, vmid, iova, + tg, ttl, sec_sid); =20 if (g_hash_table_remove(s->iotlb, &key)) { return; @@ -343,7 +355,8 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vm= id, dma_addr_t iova, SMMUIOTLBPageInvInfo info =3D { .asid =3D asid, .iova =3D iova, .vmid =3D vmid, - .mask =3D (num_pages * 1 << granule) - 1}; + .mask =3D (num_pages * 1 << granule) - 1, + .sec_sid =3D sec_sid}; =20 g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_vmid_iova, @@ -355,13 +368,15 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int = vmid, dma_addr_t iova, * in Stage-1 invalidation ASID =3D -1, means don't care. */ void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg, - uint64_t num_pages, uint8_t ttl) + uint64_t num_pages, uint8_t ttl, + SMMUSecSID sec_sid) { uint8_t granule =3D tg ? tg * 2 + 10 : 12; int asid =3D -1; =20 if (ttl && (num_pages =3D=3D 1)) { - SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, vmid, ipa, tg, ttl); + SMMUIOTLBKey key =3D smmu_get_iotlb_key(asid, vmid, ipa, + tg, ttl, sec_sid); =20 if (g_hash_table_remove(s->iotlb, &key)) { return; @@ -371,34 +386,47 @@ void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_a= ddr_t ipa, uint8_t tg, SMMUIOTLBPageInvInfo info =3D { .iova =3D ipa, .vmid =3D vmid, - .mask =3D (num_pages << granule) - 1}; + .mask =3D (num_pages << granule) - 1, + .sec_sid =3D sec_sid}; =20 g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid_ipa, &info); } =20 -void smmu_iotlb_inv_asid_vmid(SMMUState *s, int asid, int vmid) +void smmu_iotlb_inv_asid_vmid(SMMUState *s, int asid, int vmid, + SMMUSecSID sec_sid) { SMMUIOTLBPageInvInfo info =3D { .asid =3D asid, .vmid =3D vmid, + .sec_sid =3D sec_sid, }; =20 - trace_smmu_iotlb_inv_asid_vmid(asid, vmid); + trace_smmu_iotlb_inv_asid_vmid(sec_sid, asid, vmid); g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_vmid, &= info); } =20 -void smmu_iotlb_inv_vmid(SMMUState *s, int vmid) +void smmu_iotlb_inv_vmid(SMMUState *s, int vmid, SMMUSecSID sec_sid) { - trace_smmu_iotlb_inv_vmid(vmid); - g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &vmid); + SMMUIOTLBPageInvInfo info =3D { + .vmid =3D vmid, + .sec_sid =3D sec_sid, + }; + + trace_smmu_iotlb_inv_vmid(sec_sid, vmid); + g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &info); } =20 -void smmu_iotlb_inv_vmid_s1(SMMUState *s, int vmid) +void smmu_iotlb_inv_vmid_s1(SMMUState *s, int vmid, SMMUSecSID sec_sid) { - trace_smmu_iotlb_inv_vmid_s1(vmid); - g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid_s1, &vm= id); + SMMUIOTLBPageInvInfo info =3D { + .vmid =3D vmid, + .sec_sid =3D sec_sid, + }; + + trace_smmu_iotlb_inv_vmid_s1(sec_sid, vmid); + g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid_s1, &in= fo); } =20 /* VMSAv8-64 Translation */ diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h index a0454f720da..5ddd0372d5b 100644 --- a/hw/arm/smmu-internal.h +++ b/hw/arm/smmu-internal.h @@ -145,12 +145,14 @@ static inline int pgd_concat_idx(int start_level, int= granule_sz, =20 #define SMMU_IOTLB_ASID(key) ((key).asid) #define SMMU_IOTLB_VMID(key) ((key).vmid) +#define SMMU_IOTLB_SEC_SID(key) ((key).sec_sid) =20 typedef struct SMMUIOTLBPageInvInfo { int asid; int vmid; uint64_t iova; uint64_t mask; + SMMUSecSID sec_sid; } SMMUIOTLBPageInvInfo; =20 #endif diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 504161ce06d..4a4de719a7c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1279,7 +1279,8 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, int vmid, } } =20 -static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage) +static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage, + SMMUSecSID sec_sid) { dma_addr_t end, addr =3D CMD_ADDR(cmd); uint8_t type =3D CMD_TYPE(cmd); @@ -1304,12 +1305,13 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *c= md, SMMUStage stage) } =20 if (!tg) { - trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf, stage= ); + trace_smmuv3_range_inval(sec_sid, vmid, asid, addr, + tg, 1, ttl, leaf, stage); smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, 1, stage); if (stage =3D=3D SMMU_STAGE_1) { - smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl); + smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl, sec_sid); } else { - smmu_iotlb_inv_ipa(s, vmid, addr, tg, 1, ttl); + smmu_iotlb_inv_ipa(s, vmid, addr, tg, 1, ttl, sec_sid); } return; } @@ -1326,13 +1328,15 @@ static void smmuv3_range_inval(SMMUState *s, Cmd *c= md, SMMUStage stage) uint64_t mask =3D dma_aligned_pow2_mask(addr, end, 64); =20 num_pages =3D (mask + 1) >> granule; - trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, - ttl, leaf, stage); - smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, num_pages, stag= e); + trace_smmuv3_range_inval(sec_sid, vmid, asid, addr, tg, + num_pages, ttl, leaf, stage); + smmuv3_inv_notifiers_iova(s, asid, vmid, addr, tg, + num_pages, stage); if (stage =3D=3D SMMU_STAGE_1) { - smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl); + smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, + num_pages, ttl, sec_sid); } else { - smmu_iotlb_inv_ipa(s, vmid, addr, tg, num_pages, ttl); + smmu_iotlb_inv_ipa(s, vmid, addr, tg, num_pages, ttl, sec_sid); } addr +=3D mask + 1; } @@ -1474,9 +1478,9 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp) vmid =3D CMD_VMID(&cmd); } =20 - trace_smmuv3_cmdq_tlbi_nh_asid(asid); + trace_smmuv3_cmdq_tlbi_nh_asid(sec_sid, asid); smmu_inv_notifiers_all(&s->smmu_state); - smmu_iotlb_inv_asid_vmid(bs, asid, vmid); + smmu_iotlb_inv_asid_vmid(bs, asid, vmid, sec_sid); if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, errp)) { cmd_error =3D SMMU_CERROR_ILL; break; @@ -1498,8 +1502,8 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp) */ if (STAGE2_SUPPORTED(s)) { vmid =3D CMD_VMID(&cmd); - trace_smmuv3_cmdq_tlbi_nh(vmid); - smmu_iotlb_inv_vmid_s1(bs, vmid); + trace_smmuv3_cmdq_tlbi_nh(sec_sid, vmid); + smmu_iotlb_inv_vmid_s1(bs, vmid, sec_sid); break; } QEMU_FALLTHROUGH; @@ -1519,7 +1523,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp) cmd_error =3D SMMU_CERROR_ILL; break; } - smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1); + smmuv3_range_inval(bs, &cmd, SMMU_STAGE_1, SMMU_SEC_SID_NS); if (!smmuv3_accel_issue_inv_cmd(s, &cmd, NULL, errp)) { cmd_error =3D SMMU_CERROR_ILL; break; @@ -1536,7 +1540,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp) =20 trace_smmuv3_cmdq_tlbi_s12_vmid(vmid); smmu_inv_notifiers_all(&s->smmu_state); - smmu_iotlb_inv_vmid(bs, vmid); + smmu_iotlb_inv_vmid(bs, vmid, SMMU_SEC_SID_NS); break; } case SMMU_CMD_TLBI_S2_IPA: @@ -1548,7 +1552,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp) * As currently only either s1 or s2 are supported * we can reuse same function for s2. */ - smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2); + smmuv3_range_inval(bs, &cmd, SMMU_STAGE_2, SMMU_SEC_SID_NS); break; case SMMU_CMD_ATC_INV: { diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 9c2cc131ab4..4e360b3c0d3 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -18,9 +18,9 @@ smmu_ptw_page_pte(int stage, int level, uint64_t iova, u= int64_t baseaddr, uint6 smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t ptead= dr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=3D%d le= vel=3D%d base@=3D0x%"PRIx64" pte@=3D0x%"PRIx64" pte=3D0x%"PRIx64" iova=3D0x= %"PRIx64" block address =3D 0x%"PRIx64" block size =3D %d MiB" smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte)= "baseaddr=3D0x%"PRIx64" index=3D0x%x, pteaddr=3D0x%"PRIx64", pte=3D0x%"PRI= x64 smmu_iotlb_inv_all(void) "IOTLB invalidate all" -smmu_iotlb_inv_asid_vmid(int asid, int vmid) "IOTLB invalidate asid=3D%d v= mid=3D%d" -smmu_iotlb_inv_vmid(int vmid) "IOTLB invalidate vmid=3D%d" -smmu_iotlb_inv_vmid_s1(int vmid) "IOTLB invalidate vmid=3D%d" +smmu_iotlb_inv_asid_vmid(int sec_sid, int asid, int vmid) "IOTLB invalidat= e sec_sid=3D%d asid=3D%d vmid=3D%d" +smmu_iotlb_inv_vmid(int sec_sid, int vmid) "IOTLB invalidate sec_sid=3D%d = vmid=3D%d" +smmu_iotlb_inv_vmid_s1(int sec_sid, int vmid) "IOTLB invalidate S1 sec_sid= =3D%d vmid=3D%d" smmu_iotlb_inv_iova(int asid, uint64_t addr) "IOTLB invalidate asid=3D%d a= ddr=3D0x%"PRIx64 smmu_configs_inv_sid_range(uint32_t start, uint32_t end) "Config cache INV= SID range from 0x%x to 0x%x" smmu_config_cache_inv(uint32_t sid) "Config cache INV for sid=3D0x%x" @@ -56,10 +56,10 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start= =3D0x%x - end=3D0x%x" smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=3D0x%x" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint= 32_t perc) "Config cache HIT for sid=3D0x%x (hits=3D%d, misses=3D%d, hit ra= te=3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uin= t32_t perc) "Config cache MISS for sid=3D0x%x (hits=3D%d, misses=3D%d, hit = rate=3D%d)" -smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t= num_pages, uint8_t ttl, bool leaf, int stage) "vmid=3D%d asid=3D%d addr=3D= 0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" ttl=3D%d leaf=3D%d stage=3D%d" -smmuv3_cmdq_tlbi_nh(int vmid) "vmid=3D%d" +smmuv3_range_inval(int sec_sid, int vmid, int asid, uint64_t addr, uint8_t= tg, uint64_t num_pages, uint8_t ttl, bool leaf, int stage) "sec_sid=3D%d v= mid=3D%d asid=3D%d addr=3D0x%"PRIx64" tg=3D%d num_pages=3D0x%"PRIx64" ttl= =3D%d leaf=3D%d stage=3D%d" +smmuv3_cmdq_tlbi_nh(int sec_sid, int vmid) "sec_sid=3D%d vmid=3D%d" smmuv3_cmdq_tlbi_nsnh(void) "" -smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=3D%d" +smmuv3_cmdq_tlbi_nh_asid(int sec_sid, int asid) "sec_sid=3D%d asid=3D%d" smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=3D%d" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index b0a02e12fe6..7d1d0936921 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -162,6 +162,7 @@ typedef struct SMMUIOTLBKey { int vmid; uint8_t tg; uint8_t level; + SMMUSecSID sec_sid; } SMMUIOTLBKey; =20 typedef struct SMMUConfigKey { @@ -256,16 +257,19 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTr= ansCfg *cfg, SMMUTransTableInfo *tt, hwaddr iova); void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *ent= ry); SMMUIOTLBKey smmu_get_iotlb_key(int asid, int vmid, uint64_t iova, - uint8_t tg, uint8_t level); + uint8_t tg, uint8_t level, SMMUSecSID sec_= sid); SMMUConfigKey smmu_get_config_key(SMMUDevice *sdev, SMMUSecSID sec_sid); void smmu_iotlb_inv_all(SMMUState *s); -void smmu_iotlb_inv_asid_vmid(SMMUState *s, int asid, int vmid); -void smmu_iotlb_inv_vmid(SMMUState *s, int vmid); -void smmu_iotlb_inv_vmid_s1(SMMUState *s, int vmid); +void smmu_iotlb_inv_asid_vmid(SMMUState *s, int asid, int vmid, + SMMUSecSID sec_sid); +void smmu_iotlb_inv_vmid(SMMUState *s, int vmid, SMMUSecSID sec_sid); +void smmu_iotlb_inv_vmid_s1(SMMUState *s, int vmid, SMMUSecSID sec_sid); void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, - uint8_t tg, uint64_t num_pages, uint8_t ttl); + uint8_t tg, uint64_t num_pages, uint8_t ttl, + SMMUSecSID sec_sid); void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg, - uint64_t num_pages, uint8_t ttl); + uint64_t num_pages, uint8_t ttl, + SMMUSecSID sec_sid); void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range); void smmu_configs_inv_sdev(SMMUState *s, SMMUDevice *sdev); /* Unmap the range of all the notifiers registered to any IOMMU mr */ --=20 2.34.1