From nobody Sun Apr 12 04:23:15 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771668318227126.50947829576648; Sat, 21 Feb 2026 02:05:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vtjpt-0005pH-OU; Sat, 21 Feb 2026 05:03:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vtjpf-0005mE-CL; Sat, 21 Feb 2026 05:03:28 -0500 Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net ([209.97.181.73]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vtjpZ-00056m-KB; Sat, 21 Feb 2026 05:03:27 -0500 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwCnr5vjgplpc6BVBw--.3730S2; Sat, 21 Feb 2026 18:03:15 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAfwD3TevcgplpBk4cAA--.34138S7; Sat, 21 Feb 2026 18:03:13 +0800 (CST) From: Tao Tang To: Eric Auger , Peter Maydell , "Michael S . Tsirkin" , Marcel Apfelbaum Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Chen Baozi , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mostafa Saleh , Chao Liu , Tao Tang Subject: [RFC v4 04/31] hw/arm/smmuv3: Introduce banked registers for SMMUv3 state Date: Sat, 21 Feb 2026 18:02:23 +0800 Message-Id: <20260221100250.2976287-5-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> References: <20260221100250.2976287-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAfwD3TevcgplpBk4cAA--.34138S7 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQANBWmYzyUAHgAAsM Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvAXoWfZw1xJr4kWF43CF1kXw1DKFg_yoWrJFy5Go W2yF4qqw4DZw4kCa48uFn5JF18tFW8Cw4qqa1YvrWa9FsFgw45Kryxtrs8CF9IkF45XrWk Cw4xu3yrXFWIvFn5n29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3UbIjqfuFe4nvWSU8nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UU UUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.97.181.73; envelope-from=tangtao1634@phytium.com.cn; helo=zg8tmja5ljk3lje4ms43mwaa.icoremail.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1771668319953158500 Content-Type: text/plain; charset="utf-8" Rework the SMMUv3 state management by introducing a banked register structure. This is a purely mechanical refactoring with no functional changes. To support multiple security states, a new enum, SMMUSecSID, is introduced to identify each state, sticking to the spec terminology. A new structure, SMMUv3RegBank, is then defined to hold the state for a single security context. The main SMMUv3State now contains an array of these banks, indexed by SMMUSecSID. This avoids the need for separate fields for non-secure and future secure registers. All existing code, which handles only the Non-secure state, is updated to access its state via s->bank[SMMU_SEC_SID_NS]. A local bank helper pointer is used where it improves readability. Function signatures and logic remain untouched in this commit to isolate the structural changes and simplify review. This is the foundational step for building multi-security-state support. Signed-off-by: Tao Tang Reviewed-by: Eric Auger Reviewed-by: Mostafa Saleh Reviewed-by: Pierrick Bouvier --- hw/arm/smmuv3-accel.c | 42 +++-- hw/arm/smmuv3-internal.h | 24 ++- hw/arm/smmuv3.c | 345 +++++++++++++++++++---------------- include/hw/arm/smmu-common.h | 6 + include/hw/arm/smmuv3.h | 30 ++- 5 files changed, 257 insertions(+), 190 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index f5cd4df336a..30d4b38c0a3 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -40,19 +40,20 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, struct iommu_hw_info_arm_smmuv3 *info, Error **errp) { + SMMUv3RegBank *bank =3D smmuv3_bank(s, SMMU_SEC_SID_NS); /* QEMU SMMUv3 supports both linear and 2-level stream tables */ if (FIELD_EX32(info->idr[0], IDR0, STLEVEL) !=3D - FIELD_EX32(s->idr[0], IDR0, STLEVEL)) { + FIELD_EX32(bank->idr[0], IDR0, STLEVEL)) { error_setg(errp, "Host SMMUv3 Stream Table format mismatch " "(host STLEVEL=3D%u, QEMU STLEVEL=3D%u)", FIELD_EX32(info->idr[0], IDR0, STLEVEL), - FIELD_EX32(s->idr[0], IDR0, STLEVEL)); + FIELD_EX32(bank->idr[0], IDR0, STLEVEL)); return false; } =20 /* QEMU SMMUv3 supports only little-endian translation table walks */ if (FIELD_EX32(info->idr[0], IDR0, TTENDIAN) > - FIELD_EX32(s->idr[0], IDR0, TTENDIAN)) { + FIELD_EX32(bank->idr[0], IDR0, TTENDIAN)) { error_setg(errp, "Host SMMUv3 doesn't support Little-endian " "translation table"); return false; @@ -60,7 +61,7 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, =20 /* QEMU SMMUv3 supports only AArch64 translation table format */ if (FIELD_EX32(info->idr[0], IDR0, TTF) < - FIELD_EX32(s->idr[0], IDR0, TTF)) { + FIELD_EX32(bank->idr[0], IDR0, TTF)) { error_setg(errp, "Host SMMUv3 doesn't support AArch64 translation " "table format"); return false; @@ -68,53 +69,53 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, =20 /* QEMU SMMUv3 supports SIDSIZE 16 */ if (FIELD_EX32(info->idr[1], IDR1, SIDSIZE) < - FIELD_EX32(s->idr[1], IDR1, SIDSIZE)) { + FIELD_EX32(bank->idr[1], IDR1, SIDSIZE)) { error_setg(errp, "Host SMMUv3 SIDSIZE not compatible " "(host=3D%u, QEMU=3D%u)", FIELD_EX32(info->idr[1], IDR1, SIDSIZE), - FIELD_EX32(s->idr[1], IDR1, SIDSIZE)); + FIELD_EX32(bank->idr[1], IDR1, SIDSIZE)); return false; } =20 /* Check SSIDSIZE value opted-in is compatible with Host SMMUv3 SSIDSI= ZE */ if (FIELD_EX32(info->idr[1], IDR1, SSIDSIZE) < - FIELD_EX32(s->idr[1], IDR1, SSIDSIZE)) { + FIELD_EX32(bank->idr[1], IDR1, SSIDSIZE)) { error_setg(errp, "Host SMMUv3 SSIDSIZE not compatible " "(host=3D%u, QEMU=3D%u)", FIELD_EX32(info->idr[1], IDR1, SSIDSIZE), - FIELD_EX32(s->idr[1], IDR1, SSIDSIZE)); + FIELD_EX32(bank->idr[1], IDR1, SSIDSIZE)); return false; } =20 /* User can disable QEMU SMMUv3 Range Invalidation support */ if (FIELD_EX32(info->idr[3], IDR3, RIL) < - FIELD_EX32(s->idr[3], IDR3, RIL)) { + FIELD_EX32(bank->idr[3], IDR3, RIL)) { error_setg(errp, "Host SMMUv3 doesn't support Range Invalidation"); return false; } /* Check OAS value opted is compatible with Host SMMUv3 IPA */ if (FIELD_EX32(info->idr[5], IDR5, OAS) < - FIELD_EX32(s->idr[5], IDR5, OAS)) { + FIELD_EX32(bank->idr[5], IDR5, OAS)) { error_setg(errp, "Host SMMUv3 supports only %d-bit IPA, but the vS= MMU " "OAS implies %d-bit IPA", smmuv3_oas_bits(FIELD_EX32(info->idr[5], IDR5, OAS)), - smmuv3_oas_bits(FIELD_EX32(s->idr[5], IDR5, OAS))); + smmuv3_oas_bits(FIELD_EX32(bank->idr[5], IDR5, OAS))); return false; } =20 /* QEMU SMMUv3 supports GRAN4K/GRAN16K/GRAN64K translation granules */ if (FIELD_EX32(info->idr[5], IDR5, GRAN4K) !=3D - FIELD_EX32(s->idr[5], IDR5, GRAN4K)) { + FIELD_EX32(bank->idr[5], IDR5, GRAN4K)) { error_setg(errp, "Host SMMUv3 doesn't support 4K translation granu= le"); return false; } if (FIELD_EX32(info->idr[5], IDR5, GRAN16K) !=3D - FIELD_EX32(s->idr[5], IDR5, GRAN16K)) { + FIELD_EX32(bank->idr[5], IDR5, GRAN16K)) { error_setg(errp, "Host SMMUv3 doesn't support 16K translation gran= ule"); return false; } if (FIELD_EX32(info->idr[5], IDR5, GRAN64K) !=3D - FIELD_EX32(s->idr[5], IDR5, GRAN64K)) { + FIELD_EX32(bank->idr[5], IDR5, GRAN64K)) { error_setg(errp, "Host SMMUv3 doesn't support 64K translation gran= ule"); return false; } @@ -168,7 +169,8 @@ static SMMUv3AccelDevice *smmuv3_accel_get_dev(SMMUStat= e *bs, SMMUPciBus *sbus, =20 static uint32_t smmuv3_accel_gbpa_hwpt(SMMUv3State *s, SMMUv3AccelState *a= ccel) { - return FIELD_EX32(s->gbpa, GBPA, ABORT) ? + SMMUv3RegBank *bank =3D smmuv3_bank(s, SMMU_SEC_SID_NS); + return FIELD_EX32(bank->gbpa, GBPA, ABORT) ? accel->abort_hwpt_id : accel->bypass_hwpt_id; } =20 @@ -687,22 +689,24 @@ void smmuv3_accel_idr_override(SMMUv3State *s) return; } =20 + SMMUv3RegBank *bank =3D smmuv3_bank(s, SMMU_SEC_SID_NS); + /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); + bank->idr[3] =3D FIELD_DP32(bank->idr[3], IDR3, RIL, s->ril); =20 /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); + bank->idr[0] =3D FIELD_DP32(bank->idr[0], IDR0, ATS, s->ats); =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ if (s->oas =3D=3D SMMU_OAS_48BIT) { - s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); + bank->idr[5] =3D FIELD_DP32(bank->idr[5], IDR5, OAS, SMMU_IDR5_OAS= _48); } =20 /* * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if u= ser * has enabled it. */ - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize); + bank->idr[1] =3D FIELD_DP32(bank->idr[1], IDR1, SSIDSIZE, s->ssidsize); } =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index ebdb4ebae67..deb1ef60e87 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -41,7 +41,9 @@ typedef enum SMMUTranslationClass { =20 static inline int smmu_enabled(SMMUv3State *s) { - return FIELD_EX32(s->cr[0], CR0, SMMUEN); + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); + return FIELD_EX32(bank->cr[0], CR0, SMMUEN); } =20 /* Command Queue Entry */ @@ -69,12 +71,16 @@ static inline uint32_t smmuv3_idreg(int regoffset) =20 static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s) { - return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN); + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); + return FIELD_EX32(bank->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN); } =20 static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s) { - return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN); + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); + return FIELD_EX32(bank->irq_ctrl, IRQ_CTRL, GERROR_IRQEN); } =20 /* Queue Handling */ @@ -119,17 +125,23 @@ static inline void queue_cons_incr(SMMUQueue *q) =20 static inline bool smmuv3_cmdq_enabled(SMMUv3State *s) { - return FIELD_EX32(s->cr[0], CR0, CMDQEN); + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); + return FIELD_EX32(bank->cr[0], CR0, CMDQEN); } =20 static inline bool smmuv3_eventq_enabled(SMMUv3State *s) { - return FIELD_EX32(s->cr[0], CR0, EVENTQEN); + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); + return FIELD_EX32(bank->cr[0], CR0, EVENTQEN); } =20 static inline void smmu_write_cmdq_err(SMMUv3State *s, uint32_t err_type) { - s->cmdq.cons =3D FIELD_DP32(s->cmdq.cons, CMDQ_CONS, ERR, err_type); + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); + bank->cmdq.cons =3D FIELD_DP32(bank->cmdq.cons, CMDQ_CONS, ERR, err_ty= pe); } =20 static const char *cmd_stringify[] =3D { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c08d58c5790..5511585601d 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -52,6 +52,8 @@ static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask) { + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); =20 bool pulse =3D false; =20 @@ -67,15 +69,15 @@ static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq = irq, break; case SMMU_IRQ_GERROR: { - uint32_t pending =3D s->gerror ^ s->gerrorn; + uint32_t pending =3D bank->gerror ^ bank->gerrorn; uint32_t new_gerrors =3D ~pending & gerror_mask; =20 if (!new_gerrors) { /* only toggle non pending errors */ return; } - s->gerror ^=3D new_gerrors; - trace_smmuv3_write_gerror(new_gerrors, s->gerror); + bank->gerror ^=3D new_gerrors; + trace_smmuv3_write_gerror(new_gerrors, bank->gerror); =20 pulse =3D smmuv3_gerror_irq_enabled(s); break; @@ -89,8 +91,10 @@ static void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq i= rq, =20 static void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn) { - uint32_t pending =3D s->gerror ^ s->gerrorn; - uint32_t toggled =3D s->gerrorn ^ new_gerrorn; + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); + uint32_t pending =3D bank->gerror ^ bank->gerrorn; + uint32_t toggled =3D bank->gerrorn ^ new_gerrorn; =20 if (toggled & ~pending) { qemu_log_mask(LOG_GUEST_ERROR, @@ -102,9 +106,9 @@ static void smmuv3_write_gerrorn(SMMUv3State *s, uint32= _t new_gerrorn) * We do not raise any error in case guest toggles bits corresponding * to not active IRQs (CONSTRAINED UNPREDICTABLE) */ - s->gerrorn =3D new_gerrorn; + bank->gerrorn =3D new_gerrorn; =20 - trace_smmuv3_write_gerrorn(toggled & pending, s->gerrorn); + trace_smmuv3_write_gerrorn(toggled & pending, bank->gerrorn); } =20 static inline MemTxResult queue_read(SMMUQueue *q, Cmd *cmd) @@ -146,7 +150,9 @@ static MemTxResult queue_write(SMMUQueue *q, Evt *evt_i= n) =20 static MemTxResult smmuv3_write_eventq(SMMUv3State *s, Evt *evt) { - SMMUQueue *q =3D &s->eventq; + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); + SMMUQueue *q =3D &bank->eventq; MemTxResult r; =20 if (!smmuv3_eventq_enabled(s)) { @@ -266,69 +272,75 @@ void smmuv3_record_event(SMMUv3State *s, SMMUEventInf= o *info) */ static void smmuv3_init_id_regs(SMMUv3State *s) { + SMMUv3RegBank *bk =3D smmuv3_bank(s, SMMU_SEC_SID_NS); + /* Based on sys property, the stages supported in smmu will be adverti= sed.*/ if (s->stage && !strcmp("2", s->stage)) { - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S2P, 1); + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, S2P, 1); } else if (s->stage && !strcmp("nested", s->stage)) { - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S1P, 1); - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S2P, 1); + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, S1P, 1); + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, S2P, 1); } else { - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S1P, 1); + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, S1P, 1); } =20 - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only= */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, VMID16, 1); /* 16-bit VMID */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endi= an */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall= */ + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, TTF, 2); /* AArch64 PTW on= ly */ + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, COHACC, 1); /* IO coherent= */ + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, ASID16, 1); /* 16-bit ASID= */ + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, VMID16, 1); /* 16-bit VMID= */ + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, TTENDIAN, 2); /* little en= dian */ + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, STALL_MODEL, 1); /* No sta= ll */ /* terminated transaction will always be aborted/error returned */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TERM_MODEL, 1); + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, TERM_MODEL, 1); /* 2-level stream table supported */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STLEVEL, 1); + bk->idr[0] =3D FIELD_DP32(bk->idr[0], IDR0, STLEVEL, 1); =20 - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SIDSIZE, SMMU_IDR1_SIDSIZE); - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS); + bk->idr[1] =3D FIELD_DP32(bk->idr[1], IDR1, SIDSIZE, SMMU_IDR1_SIDSIZE= ); + bk->idr[1] =3D FIELD_DP32(bk->idr[1], IDR1, EVENTQS, SMMU_EVENTQS); + bk->idr[1] =3D FIELD_DP32(bk->idr[1], IDR1, CMDQS, SMMU_CMDQS); =20 - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, HAD, 1); - if (FIELD_EX32(s->idr[0], IDR0, S2P)) { + bk->idr[3] =3D FIELD_DP32(bk->idr[3], IDR3, HAD, 1); + if (FIELD_EX32(bk->idr[0], IDR0, S2P)) { /* XNX is a stage-2-specific feature */ - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, XNX, 1); + bk->idr[3] =3D FIELD_DP32(bk->idr[3], IDR3, XNX, 1); } - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 1); - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, BBML, 2); + bk->idr[3] =3D FIELD_DP32(bk->idr[3], IDR3, RIL, 1); + bk->idr[3] =3D FIELD_DP32(bk->idr[3], IDR3, BBML, 2); =20 /* OAS: 44 bits */ - s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_44); + bk->idr[5] =3D FIELD_DP32(bk->idr[5], IDR5, OAS, SMMU_IDR5_OAS_44); /* 4K, 16K and 64K granule support */ - s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1); - s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN16K, 1); - s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, GRAN64K, 1); + bk->idr[5] =3D FIELD_DP32(bk->idr[5], IDR5, GRAN4K, 1); + bk->idr[5] =3D FIELD_DP32(bk->idr[5], IDR5, GRAN16K, 1); + bk->idr[5] =3D FIELD_DP32(bk->idr[5], IDR5, GRAN64K, 1); s->aidr =3D 0x1; smmuv3_accel_idr_override(s); } =20 static void smmuv3_reset(SMMUv3State *s) { - s->cmdq.base =3D deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); - s->cmdq.prod =3D 0; - s->cmdq.cons =3D 0; - s->cmdq.entry_size =3D sizeof(struct Cmd); - s->eventq.base =3D deposit64(s->eventq.base, 0, 5, SMMU_EVENTQS); - s->eventq.prod =3D 0; - s->eventq.cons =3D 0; - s->eventq.entry_size =3D sizeof(struct Evt); - - s->features =3D 0; - s->sid_split =3D 0; - s->cr[0] =3D 0; - s->cr0ack =3D 0; - s->irq_ctrl =3D 0; - s->gerror =3D 0; - s->gerrorn =3D 0; + SMMUv3RegBank *bk =3D smmuv3_bank(s, SMMU_SEC_SID_NS); + + bk->cmdq.base =3D deposit64(bk->cmdq.base, 0, 5, SMMU_CMDQS); + bk->cmdq.prod =3D 0; + bk->cmdq.cons =3D 0; + bk->cmdq.entry_size =3D sizeof(struct Cmd); + bk->eventq.base =3D deposit64(bk->eventq.base, 0, 5, SMMU_EVENTQS); + bk->eventq.prod =3D 0; + bk->eventq.cons =3D 0; + bk->eventq.entry_size =3D sizeof(struct Evt); + + bk->features =3D 0; + bk->sid_split =3D 0; + bk->cr[0] =3D 0; + bk->cr0ack =3D 0; + bk->irq_ctrl =3D 0; + bk->gerror =3D 0; + bk->gerrorn =3D 0; + bk->gbpa =3D SMMU_GBPA_RESET_VAL; + + s->aidr =3D 0x1; s->statusr =3D 0; - s->gbpa =3D SMMU_GBPA_RESET_VAL; } =20 static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, @@ -442,7 +454,7 @@ static bool s2_pgtable_config_valid(uint8_t sl0, uint8_= t t0sz, uint8_t gran) static int decode_ste_s2_cfg(SMMUv3State *s, SMMUTransCfg *cfg, STE *ste) { - uint8_t oas =3D FIELD_EX32(s->idr[5], IDR5, OAS); + uint8_t oas =3D FIELD_EX32(smmuv3_bank(s, SMMU_SEC_SID_NS)->idr[5], ID= R5, OAS); =20 if (STE_S2AA64(ste) =3D=3D 0x0) { qemu_log_mask(LOG_UNIMP, @@ -560,7 +572,8 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, STE *ste, SMMUEventInfo *event) { uint32_t config; - uint8_t oas =3D FIELD_EX32(s->idr[5], IDR5, OAS); + /* OAS field only presents on NS-IDR5 so we use hardcoded SMMU_SEC_SID= _NS */ + uint8_t oas =3D FIELD_EX32(smmuv3_bank(s, SMMU_SEC_SID_NS)->idr[5], ID= R5, OAS); int ret; =20 if (!STE_VALID(ste)) { @@ -649,9 +662,11 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *s= te, SMMUEventInfo *event) uint32_t log2size; int strtab_size_shift; int ret; + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); =20 - trace_smmuv3_find_ste(sid, s->features, s->sid_split); - log2size =3D FIELD_EX32(s->strtab_base_cfg, STRTAB_BASE_CFG, LOG2SIZE); + trace_smmuv3_find_ste(sid, bank->features, bank->sid_split); + log2size =3D FIELD_EX32(bank->strtab_base_cfg, STRTAB_BASE_CFG, LOG2SI= ZE); /* * Check SID range against both guest-configured and implementation li= mits */ @@ -659,7 +674,7 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *st= e, SMMUEventInfo *event) event->type =3D SMMU_EVT_C_BAD_STREAMID; return -EINVAL; } - if (s->features & SMMU_FEATURE_2LVL_STE) { + if (bank->features & SMMU_FEATURE_2LVL_STE) { int l1_ste_offset, l2_ste_offset, max_l2_ste, span, i; dma_addr_t l1ptr, l2ptr; STEDesc l1std; @@ -668,11 +683,11 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *= ste, SMMUEventInfo *event) * Align strtab base address to table size. For this purpose, assu= me it * is not bounded by SMMU_IDR1_SIDSIZE. */ - strtab_size_shift =3D MAX(5, (int)log2size - s->sid_split - 1 + 3); - strtab_base =3D s->strtab_base & SMMU_BASE_ADDR_MASK & + strtab_size_shift =3D MAX(5, (int)log2size - bank->sid_split - 1 += 3); + strtab_base =3D bank->strtab_base & SMMU_BASE_ADDR_MASK & ~MAKE_64BIT_MASK(0, strtab_size_shift); - l1_ste_offset =3D sid >> s->sid_split; - l2_ste_offset =3D sid & ((1 << s->sid_split) - 1); + l1_ste_offset =3D sid >> bank->sid_split; + l2_ste_offset =3D sid & ((1 << bank->sid_split) - 1); l1ptr =3D (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)= ); /* TODO: guarantee 64-bit single-copy atomicity */ ret =3D dma_memory_read(&address_space_memory, l1ptr, &l1std, @@ -701,7 +716,7 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *st= e, SMMUEventInfo *event) } max_l2_ste =3D (1 << span) - 1; l2ptr =3D l1std_l2ptr(&l1std); - trace_smmuv3_find_ste_2lvl(s->strtab_base, l1ptr, l1_ste_offset, + trace_smmuv3_find_ste_2lvl(bank->strtab_base, l1ptr, l1_ste_offset, l2ptr, l2_ste_offset, max_l2_ste); if (l2_ste_offset > max_l2_ste) { qemu_log_mask(LOG_GUEST_ERROR, @@ -713,7 +728,7 @@ int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *st= e, SMMUEventInfo *event) addr =3D l2ptr + l2_ste_offset * sizeof(*ste); } else { strtab_size_shift =3D log2size + 5; - strtab_base =3D s->strtab_base & SMMU_BASE_ADDR_MASK & + strtab_base =3D bank->strtab_base & SMMU_BASE_ADDR_MASK & ~MAKE_64BIT_MASK(0, strtab_size_shift); addr =3D strtab_base + sid * sizeof(*ste); } @@ -732,7 +747,7 @@ static int decode_cd(SMMUv3State *s, SMMUTransCfg *cfg, int i; SMMUTranslationStatus status; SMMUTLBEntry *entry; - uint8_t oas =3D FIELD_EX32(s->idr[5], IDR5, OAS); + uint8_t oas =3D FIELD_EX32(smmuv3_bank(s, SMMU_SEC_SID_NS)->idr[5], ID= R5, OAS); =20 if (!CD_VALID(cd) || !CD_AARCH64(cd)) { goto bad_cd; @@ -1054,6 +1069,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); SMMUv3State *s =3D sdev->smmu; uint32_t sid =3D smmu_get_sid(sdev); + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid, .inval_ste_allowed =3D false}; @@ -1071,7 +1088,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegi= on *mr, hwaddr addr, qemu_mutex_lock(&s->mutex); =20 if (!smmu_enabled(s)) { - if (FIELD_EX32(s->gbpa, GBPA, ABORT)) { + if (FIELD_EX32(bank->gbpa, GBPA, ABORT)) { status =3D SMMU_TRANS_ABORT; } else { status =3D SMMU_TRANS_DISABLE; @@ -1295,7 +1312,9 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp) { SMMUState *bs =3D ARM_SMMU(s); SMMUCmdError cmd_error =3D SMMU_CERROR_NONE; - SMMUQueue *q =3D &s->cmdq; + SMMUSecSID sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, sec_sid); + SMMUQueue *q =3D &bank->cmdq; SMMUCommandType type =3D 0; =20 if (!smmuv3_cmdq_enabled(s)) { @@ -1309,7 +1328,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Error = **errp) */ =20 while (!smmuv3_q_empty(q)) { - uint32_t pending =3D s->gerror ^ s->gerrorn; + uint32_t pending =3D bank->gerror ^ bank->gerrorn; Cmd cmd; =20 trace_smmuv3_cmdq_consume(Q_PROD(q), Q_CONS(q), @@ -1562,29 +1581,32 @@ static int smmuv3_cmdq_consume(SMMUv3State *s, Erro= r **errp) static MemTxResult smmu_writell(SMMUv3State *s, hwaddr offset, uint64_t data, MemTxAttrs attrs) { + SMMUSecSID reg_sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, reg_sec_sid); + switch (offset) { case A_GERROR_IRQ_CFG0: - s->gerror_irq_cfg0 =3D data; + bank->gerror_irq_cfg0 =3D data; return MEMTX_OK; case A_STRTAB_BASE: - s->strtab_base =3D data; + bank->strtab_base =3D data; return MEMTX_OK; case A_CMDQ_BASE: - s->cmdq.base =3D data; - s->cmdq.log2size =3D extract64(s->cmdq.base, 0, 5); - if (s->cmdq.log2size > SMMU_CMDQS) { - s->cmdq.log2size =3D SMMU_CMDQS; + bank->cmdq.base =3D data; + bank->cmdq.log2size =3D extract64(bank->cmdq.base, 0, 5); + if (bank->cmdq.log2size > SMMU_CMDQS) { + bank->cmdq.log2size =3D SMMU_CMDQS; } return MEMTX_OK; case A_EVENTQ_BASE: - s->eventq.base =3D data; - s->eventq.log2size =3D extract64(s->eventq.base, 0, 5); - if (s->eventq.log2size > SMMU_EVENTQS) { - s->eventq.log2size =3D SMMU_EVENTQS; + bank->eventq.base =3D data; + bank->eventq.log2size =3D extract64(bank->eventq.base, 0, 5); + if (bank->eventq.log2size > SMMU_EVENTQS) { + bank->eventq.log2size =3D SMMU_EVENTQS; } return MEMTX_OK; case A_EVENTQ_IRQ_CFG0: - s->eventq_irq_cfg0 =3D data; + bank->eventq_irq_cfg0 =3D data; return MEMTX_OK; default: qemu_log_mask(LOG_UNIMP, @@ -1598,22 +1620,24 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwad= dr offset, uint64_t data, MemTxAttrs attrs) { Error *local_err =3D NULL; + SMMUSecSID reg_sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, reg_sec_sid); =20 switch (offset) { case A_CR0: - s->cr[0] =3D data; - s->cr0ack =3D data & ~SMMU_CR0_RESERVED; + bank->cr[0] =3D data; + bank->cr0ack =3D data & ~SMMU_CR0_RESERVED; /* in case the command queue has been enabled */ smmuv3_cmdq_consume(s, &local_err); break; case A_CR1: - s->cr[1] =3D data; + bank->cr[1] =3D data; break; case A_CR2: - s->cr[2] =3D data; + bank->cr[2] =3D data; break; case A_IRQ_CTRL: - s->irq_ctrl =3D data; + bank->irq_ctrl =3D data; break; case A_GERRORN: smmuv3_write_gerrorn(s, data); @@ -1624,16 +1648,16 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwad= dr offset, smmuv3_cmdq_consume(s, &local_err); break; case A_GERROR_IRQ_CFG0: /* 64b */ - s->gerror_irq_cfg0 =3D deposit64(s->gerror_irq_cfg0, 0, 32, data); + bank->gerror_irq_cfg0 =3D deposit64(bank->gerror_irq_cfg0, 0, 32, = data); break; case A_GERROR_IRQ_CFG0 + 4: - s->gerror_irq_cfg0 =3D deposit64(s->gerror_irq_cfg0, 32, 32, data); + bank->gerror_irq_cfg0 =3D deposit64(bank->gerror_irq_cfg0, 32, 32,= data); break; case A_GERROR_IRQ_CFG1: - s->gerror_irq_cfg1 =3D data; + bank->gerror_irq_cfg1 =3D data; break; case A_GERROR_IRQ_CFG2: - s->gerror_irq_cfg2 =3D data; + bank->gerror_irq_cfg2 =3D data; break; case A_GBPA: /* @@ -1642,67 +1666,67 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwad= dr offset, */ if (data & R_GBPA_UPDATE_MASK) { /* Ignore update bit as write is synchronous. */ - s->gbpa =3D data & ~R_GBPA_UPDATE_MASK; + bank->gbpa =3D data & ~R_GBPA_UPDATE_MASK; smmuv3_accel_attach_gbpa_hwpt(s, &local_err); } break; case A_STRTAB_BASE: /* 64b */ - s->strtab_base =3D deposit64(s->strtab_base, 0, 32, data); + bank->strtab_base =3D deposit64(bank->strtab_base, 0, 32, data); break; case A_STRTAB_BASE + 4: - s->strtab_base =3D deposit64(s->strtab_base, 32, 32, data); + bank->strtab_base =3D deposit64(bank->strtab_base, 32, 32, data); break; case A_STRTAB_BASE_CFG: - s->strtab_base_cfg =3D data; + bank->strtab_base_cfg =3D data; if (FIELD_EX32(data, STRTAB_BASE_CFG, FMT) =3D=3D 1) { - s->sid_split =3D FIELD_EX32(data, STRTAB_BASE_CFG, SPLIT); - s->features |=3D SMMU_FEATURE_2LVL_STE; + bank->sid_split =3D FIELD_EX32(data, STRTAB_BASE_CFG, SPLIT); + bank->features |=3D SMMU_FEATURE_2LVL_STE; } break; case A_CMDQ_BASE: /* 64b */ - s->cmdq.base =3D deposit64(s->cmdq.base, 0, 32, data); - s->cmdq.log2size =3D extract64(s->cmdq.base, 0, 5); - if (s->cmdq.log2size > SMMU_CMDQS) { - s->cmdq.log2size =3D SMMU_CMDQS; + bank->cmdq.base =3D deposit64(bank->cmdq.base, 0, 32, data); + bank->cmdq.log2size =3D extract64(bank->cmdq.base, 0, 5); + if (bank->cmdq.log2size > SMMU_CMDQS) { + bank->cmdq.log2size =3D SMMU_CMDQS; } break; case A_CMDQ_BASE + 4: /* 64b */ - s->cmdq.base =3D deposit64(s->cmdq.base, 32, 32, data); + bank->cmdq.base =3D deposit64(bank->cmdq.base, 32, 32, data); break; case A_CMDQ_PROD: - s->cmdq.prod =3D data; + bank->cmdq.prod =3D data; smmuv3_cmdq_consume(s, &local_err); break; case A_CMDQ_CONS: - s->cmdq.cons =3D data; + bank->cmdq.cons =3D data; break; case A_EVENTQ_BASE: /* 64b */ - s->eventq.base =3D deposit64(s->eventq.base, 0, 32, data); - s->eventq.log2size =3D extract64(s->eventq.base, 0, 5); - if (s->eventq.log2size > SMMU_EVENTQS) { - s->eventq.log2size =3D SMMU_EVENTQS; + bank->eventq.base =3D deposit64(bank->eventq.base, 0, 32, data); + bank->eventq.log2size =3D extract64(bank->eventq.base, 0, 5); + if (bank->eventq.log2size > SMMU_EVENTQS) { + bank->eventq.log2size =3D SMMU_EVENTQS; } break; case A_EVENTQ_BASE + 4: - s->eventq.base =3D deposit64(s->eventq.base, 32, 32, data); + bank->eventq.base =3D deposit64(bank->eventq.base, 32, 32, data); break; case A_EVENTQ_PROD: - s->eventq.prod =3D data; + bank->eventq.prod =3D data; break; case A_EVENTQ_CONS: - s->eventq.cons =3D data; + bank->eventq.cons =3D data; break; case A_EVENTQ_IRQ_CFG0: /* 64b */ - s->eventq_irq_cfg0 =3D deposit64(s->eventq_irq_cfg0, 0, 32, data); + bank->eventq_irq_cfg0 =3D deposit64(bank->eventq_irq_cfg0, 0, 32, = data); break; case A_EVENTQ_IRQ_CFG0 + 4: - s->eventq_irq_cfg0 =3D deposit64(s->eventq_irq_cfg0, 32, 32, data); + bank->eventq_irq_cfg0 =3D deposit64(bank->eventq_irq_cfg0, 32, 32,= data); break; case A_EVENTQ_IRQ_CFG1: - s->eventq_irq_cfg1 =3D data; + bank->eventq_irq_cfg1 =3D data; break; case A_EVENTQ_IRQ_CFG2: - s->eventq_irq_cfg2 =3D data; + bank->eventq_irq_cfg2 =3D data; break; default: qemu_log_mask(LOG_UNIMP, @@ -1746,18 +1770,21 @@ static MemTxResult smmu_write_mmio(void *opaque, hw= addr offset, uint64_t data, static MemTxResult smmu_readll(SMMUv3State *s, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { + SMMUSecSID reg_sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, reg_sec_sid); + switch (offset) { case A_GERROR_IRQ_CFG0: - *data =3D s->gerror_irq_cfg0; + *data =3D bank->gerror_irq_cfg0; return MEMTX_OK; case A_STRTAB_BASE: - *data =3D s->strtab_base; + *data =3D bank->strtab_base; return MEMTX_OK; case A_CMDQ_BASE: - *data =3D s->cmdq.base; + *data =3D bank->cmdq.base; return MEMTX_OK; case A_EVENTQ_BASE: - *data =3D s->eventq.base; + *data =3D bank->eventq.base; return MEMTX_OK; default: *data =3D 0; @@ -1771,12 +1798,15 @@ static MemTxResult smmu_readll(SMMUv3State *s, hwad= dr offset, static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset, uint64_t *data, MemTxAttrs attrs) { + SMMUSecSID reg_sec_sid =3D SMMU_SEC_SID_NS; + SMMUv3RegBank *bank =3D smmuv3_bank(s, reg_sec_sid); + switch (offset) { case A_IDREGS ... A_IDREGS + 0x2f: *data =3D smmuv3_idreg(offset - A_IDREGS); return MEMTX_OK; case A_IDR0 ... A_IDR5: - *data =3D s->idr[(offset - A_IDR0) / 4]; + *data =3D bank->idr[(offset - A_IDR0) / 4]; return MEMTX_OK; case A_IIDR: *data =3D s->iidr; @@ -1785,77 +1815,77 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwadd= r offset, *data =3D s->aidr; return MEMTX_OK; case A_CR0: - *data =3D s->cr[0]; + *data =3D bank->cr[0]; return MEMTX_OK; case A_CR0ACK: - *data =3D s->cr0ack; + *data =3D bank->cr0ack; return MEMTX_OK; case A_CR1: - *data =3D s->cr[1]; + *data =3D bank->cr[1]; return MEMTX_OK; case A_CR2: - *data =3D s->cr[2]; + *data =3D bank->cr[2]; return MEMTX_OK; case A_STATUSR: *data =3D s->statusr; return MEMTX_OK; case A_GBPA: - *data =3D s->gbpa; + *data =3D bank->gbpa; return MEMTX_OK; case A_IRQ_CTRL: case A_IRQ_CTRL_ACK: - *data =3D s->irq_ctrl; + *data =3D bank->irq_ctrl; return MEMTX_OK; case A_GERROR: - *data =3D s->gerror; + *data =3D bank->gerror; return MEMTX_OK; case A_GERRORN: - *data =3D s->gerrorn; + *data =3D bank->gerrorn; return MEMTX_OK; case A_GERROR_IRQ_CFG0: /* 64b */ - *data =3D extract64(s->gerror_irq_cfg0, 0, 32); + *data =3D extract64(bank->gerror_irq_cfg0, 0, 32); return MEMTX_OK; case A_GERROR_IRQ_CFG0 + 4: - *data =3D extract64(s->gerror_irq_cfg0, 32, 32); + *data =3D extract64(bank->gerror_irq_cfg0, 32, 32); return MEMTX_OK; case A_GERROR_IRQ_CFG1: - *data =3D s->gerror_irq_cfg1; + *data =3D bank->gerror_irq_cfg1; return MEMTX_OK; case A_GERROR_IRQ_CFG2: - *data =3D s->gerror_irq_cfg2; + *data =3D bank->gerror_irq_cfg2; return MEMTX_OK; case A_STRTAB_BASE: /* 64b */ - *data =3D extract64(s->strtab_base, 0, 32); + *data =3D extract64(bank->strtab_base, 0, 32); return MEMTX_OK; case A_STRTAB_BASE + 4: /* 64b */ - *data =3D extract64(s->strtab_base, 32, 32); + *data =3D extract64(bank->strtab_base, 32, 32); return MEMTX_OK; case A_STRTAB_BASE_CFG: - *data =3D s->strtab_base_cfg; + *data =3D bank->strtab_base_cfg; return MEMTX_OK; case A_CMDQ_BASE: /* 64b */ - *data =3D extract64(s->cmdq.base, 0, 32); + *data =3D extract64(bank->cmdq.base, 0, 32); return MEMTX_OK; case A_CMDQ_BASE + 4: - *data =3D extract64(s->cmdq.base, 32, 32); + *data =3D extract64(bank->cmdq.base, 32, 32); return MEMTX_OK; case A_CMDQ_PROD: - *data =3D s->cmdq.prod; + *data =3D bank->cmdq.prod; return MEMTX_OK; case A_CMDQ_CONS: - *data =3D s->cmdq.cons; + *data =3D bank->cmdq.cons; return MEMTX_OK; case A_EVENTQ_BASE: /* 64b */ - *data =3D extract64(s->eventq.base, 0, 32); + *data =3D extract64(bank->eventq.base, 0, 32); return MEMTX_OK; case A_EVENTQ_BASE + 4: /* 64b */ - *data =3D extract64(s->eventq.base, 32, 32); + *data =3D extract64(bank->eventq.base, 32, 32); return MEMTX_OK; case A_EVENTQ_PROD: - *data =3D s->eventq.prod; + *data =3D bank->eventq.prod; return MEMTX_OK; case A_EVENTQ_CONS: - *data =3D s->eventq.cons; + *data =3D bank->eventq.cons; return MEMTX_OK; default: *data =3D 0; @@ -2039,9 +2069,10 @@ static const VMStateDescription vmstate_smmuv3_queue= =3D { static bool smmuv3_gbpa_needed(void *opaque) { SMMUv3State *s =3D opaque; + SMMUv3RegBank *bank =3D smmuv3_bank(s, SMMU_SEC_SID_NS); =20 /* Only migrate GBPA if it has different reset value. */ - return s->gbpa !=3D SMMU_GBPA_RESET_VAL; + return bank->gbpa !=3D SMMU_GBPA_RESET_VAL; } =20 static const VMStateDescription vmstate_gbpa =3D { @@ -2050,7 +2081,7 @@ static const VMStateDescription vmstate_gbpa =3D { .minimum_version_id =3D 1, .needed =3D smmuv3_gbpa_needed, .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(gbpa, SMMUv3State), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].gbpa, SMMUv3State), VMSTATE_END_OF_LIST() } }; @@ -2061,27 +2092,29 @@ static const VMStateDescription vmstate_smmuv3 =3D { .minimum_version_id =3D 1, .priority =3D MIG_PRI_IOMMU, .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(features, SMMUv3State), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].features, SMMUv3State), VMSTATE_UINT8(sid_size, SMMUv3State), - VMSTATE_UINT8(sid_split, SMMUv3State), + VMSTATE_UINT8(bank[SMMU_SEC_SID_NS].sid_split, SMMUv3State), =20 - VMSTATE_UINT32_ARRAY(cr, SMMUv3State, 3), - VMSTATE_UINT32(cr0ack, SMMUv3State), + VMSTATE_UINT32_ARRAY(bank[SMMU_SEC_SID_NS].cr, SMMUv3State, 3), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].cr0ack, SMMUv3State), VMSTATE_UINT32(statusr, SMMUv3State), - VMSTATE_UINT32(irq_ctrl, SMMUv3State), - VMSTATE_UINT32(gerror, SMMUv3State), - VMSTATE_UINT32(gerrorn, SMMUv3State), - VMSTATE_UINT64(gerror_irq_cfg0, SMMUv3State), - VMSTATE_UINT32(gerror_irq_cfg1, SMMUv3State), - VMSTATE_UINT32(gerror_irq_cfg2, SMMUv3State), - VMSTATE_UINT64(strtab_base, SMMUv3State), - VMSTATE_UINT32(strtab_base_cfg, SMMUv3State), - VMSTATE_UINT64(eventq_irq_cfg0, SMMUv3State), - VMSTATE_UINT32(eventq_irq_cfg1, SMMUv3State), - VMSTATE_UINT32(eventq_irq_cfg2, SMMUv3State), - - VMSTATE_STRUCT(cmdq, SMMUv3State, 0, vmstate_smmuv3_queue, SMMUQue= ue), - VMSTATE_STRUCT(eventq, SMMUv3State, 0, vmstate_smmuv3_queue, SMMUQ= ueue), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].irq_ctrl, SMMUv3State), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].gerror, SMMUv3State), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].gerrorn, SMMUv3State), + VMSTATE_UINT64(bank[SMMU_SEC_SID_NS].gerror_irq_cfg0, SMMUv3State), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].gerror_irq_cfg1, SMMUv3State), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].gerror_irq_cfg2, SMMUv3State), + VMSTATE_UINT64(bank[SMMU_SEC_SID_NS].strtab_base, SMMUv3State), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].strtab_base_cfg, SMMUv3State), + VMSTATE_UINT64(bank[SMMU_SEC_SID_NS].eventq_irq_cfg0, SMMUv3State), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].eventq_irq_cfg1, SMMUv3State), + VMSTATE_UINT32(bank[SMMU_SEC_SID_NS].eventq_irq_cfg2, SMMUv3State), + + VMSTATE_STRUCT(bank[SMMU_SEC_SID_NS].cmdq, SMMUv3State, 0, + vmstate_smmuv3_queue, SMMUQueue), + VMSTATE_STRUCT(bank[SMMU_SEC_SID_NS].eventq, SMMUv3State, 0, + vmstate_smmuv3_queue, SMMUQueue), =20 VMSTATE_END_OF_LIST(), }, diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 7b975abc25a..6ea40f6b074 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -40,6 +40,12 @@ #define CACHED_ENTRY_TO_ADDR(ent, addr) ((ent)->entry.translated_addr= + \ ((addr) & (ent)->entry.addr_m= ask)) =20 +/* StreamID Security state */ +typedef enum SMMUSecSID { + SMMU_SEC_SID_NS =3D 0, + SMMU_SEC_SID_NUM, +} SMMUSecSID; + /* * Page table walk error types */ diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 26b2fc42fd9..d07bdfa1f27 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -32,19 +32,13 @@ typedef struct SMMUQueue { uint8_t log2size; } SMMUQueue; =20 -struct SMMUv3State { - SMMUState smmu_state; - +typedef struct SMMUv3RegBank { uint32_t features; - uint8_t sid_size; uint8_t sid_split; =20 uint32_t idr[6]; - uint32_t iidr; - uint32_t aidr; uint32_t cr[3]; uint32_t cr0ack; - uint32_t statusr; uint32_t gbpa; uint32_t irq_ctrl; uint32_t gerror; @@ -59,6 +53,17 @@ struct SMMUv3State { uint32_t eventq_irq_cfg2; =20 SMMUQueue eventq, cmdq; +} SMMUv3RegBank; + +struct SMMUv3State { + SMMUState smmu_state; + + uint8_t sid_size; + uint32_t iidr; + uint32_t aidr; + uint32_t statusr; + + SMMUv3RegBank bank[SMMU_SEC_SID_NUM]; =20 qemu_irq irq[4]; QemuMutex mutex; @@ -94,7 +99,14 @@ struct SMMUv3Class { #define TYPE_ARM_SMMUV3 "arm-smmuv3" OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3) =20 -#define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P) -#define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P) +#define STAGE1_SUPPORTED(s) \ + FIELD_EX32((s)->bank[SMMU_SEC_SID_NS].idr[0], IDR0, S1P) +#define STAGE2_SUPPORTED(s) \ + FIELD_EX32((s)->bank[SMMU_SEC_SID_NS].idr[0], IDR0, S2P) + +static inline SMMUv3RegBank *smmuv3_bank(SMMUv3State *s, SMMUSecSID sec_si= d) +{ + return &s->bank[sec_sid]; +} =20 #endif --=20 2.34.1