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Extract sparc_fpu_gdb_write_register() out of sparc_cpu_gdb_read_register() and sparc_fpu_gdb_write_register() out of sparc_cpu_gdb_write_register(), taking care to update the register indexes in the switch cases. Register these helpers with a call to gdb_register_coprocessor() in sparc_cpu_register_gdb_regs(). [*] https://sourceware.org/git/?p=3Dbinutils-gdb.git;a=3Dtree;f=3Dgdb/featu= res/sparc;hb=3Drefs/tags/binutils-2_46 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- configs/targets/sparc64-linux-user.mak | 2 +- configs/targets/sparc64-softmmu.mak | 2 +- target/sparc/gdbstub.c | 88 +++++++++++++++++--------- gdb-xml/sparc64-core.xml | 50 --------------- gdb-xml/sparc64-fpu.xml | 59 +++++++++++++++++ 5 files changed, 119 insertions(+), 82 deletions(-) create mode 100644 gdb-xml/sparc64-fpu.xml diff --git a/configs/targets/sparc64-linux-user.mak b/configs/targets/sparc= 64-linux-user.mak index 930f7e13ab9..a5f8f8d51a2 100644 --- a/configs/targets/sparc64-linux-user.mak +++ b/configs/targets/sparc64-linux-user.mak @@ -4,6 +4,6 @@ TARGET_ABI_DIR=3Dsparc TARGET_SYSTBL_ABI=3Dcommon,64 TARGET_SYSTBL=3Dsyscall.tbl TARGET_BIG_ENDIAN=3Dy -TARGET_XML_FILES=3Dgdb-xml/sparc64-core.xml gdb-xml/sparc64-cp0.xml +TARGET_XML_FILES=3Dgdb-xml/sparc64-core.xml gdb-xml/sparc64-fpu.xml gdb-xm= l/sparc64-cp0.xml TARGET_LONG_BITS=3D64 TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-= softmmu.mak index 22e7f3c94a7..c35b6b1bb8a 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,7 +1,7 @@ TARGET_ARCH=3Dsparc64 TARGET_BASE_ARCH=3Dsparc TARGET_BIG_ENDIAN=3Dy -TARGET_XML_FILES=3Dgdb-xml/sparc64-core.xml gdb-xml/sparc64-cp0.xml +TARGET_XML_FILES=3Dgdb-xml/sparc64-core.xml gdb-xml/sparc64-fpu.xml gdb-xm= l/sparc64-cp0.xml TARGET_LONG_BITS=3D64 TARGET_NOT_USING_LEGACY_LDST_PHYS_API=3Dy TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=3Dy diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index bdd759dd0a9..b5b1494950a 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -40,32 +40,40 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) /* register window */ return gdb_get_rega(mem_buf, env->regwptr[n - 8]); } + return 0; +} + +__attribute__((unused)) +static int sparc_fpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, = int n) +{ + CPUSPARCState *env =3D cpu_env(cs); + #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) - if (n < 64) { + if (n < 32) { /* fprs */ if (n & 1) { - return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower); + return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.lower); } else { - return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper); + return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.upper); } } #else - if (n < 64) { + if (n < 32) { /* f0-f31 */ if (n & 1) { - return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower); + return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.lower); } else { - return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper); + return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.upper); } } - if (n < 80) { + if (n < 48) { /* f32-f62 (16 double width registers, even register numbers only) - * n =3D=3D 64: f32 : env->fpr[16] - * n =3D=3D 65: f34 : env->fpr[17] + * n =3D=3D 32: f32 : env->fpr[16] + * n =3D=3D 33: f34 : env->fpr[17] * etc... - * n =3D=3D 79: f62 : env->fpr[31] + * n =3D=3D 47: f62 : env->fpr[31] */ - return gdb_get_reg64(mem_buf, env->fpr[(n - 64) + 16].ll); + return gdb_get_reg64(mem_buf, env->fpr[(n - 32) + 16].ll); } #endif return 0; @@ -135,39 +143,55 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_= t *mem_buf, int n) if (n < 8) { /* g0..g7 */ env->gregs[n] =3D tmp; - } else if (n < 32) { + } else { /* register window */ env->regwptr[n - 8] =3D tmp; } #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) - else if (n < 64) { - /* fprs */ - /* f0-f31 */ - if (n & 1) { - env->fpr[(n - 32) / 2].l.lower =3D tmp; - } else { - env->fpr[(n - 32) / 2].l.upper =3D tmp; - } - } return 4; #else - else if (n < 64) { + return 8; +#endif +} + +__attribute__((unused)) +static int sparc_fpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, in= t n) +{ + CPUSPARCState *env =3D cpu_env(cs); + +#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) + uint32_t tmp; + + tmp =3D ldl_p(mem_buf); + + /* fprs */ + /* f0-f31 */ + if (n & 1) { + env->fpr[n / 2].l.lower =3D tmp; + } else { + env->fpr[n / 2].l.upper =3D tmp; + } + + return 4; +#else + if (n < 32) { /* f0-f31 */ - tmp =3D ldl_p(mem_buf); + uint32_t tmp =3D ldl_p(mem_buf); if (n & 1) { - env->fpr[(n - 32) / 2].l.lower =3D tmp; + env->fpr[n / 2].l.lower =3D tmp; } else { - env->fpr[(n - 32) / 2].l.upper =3D tmp; + env->fpr[n / 2].l.upper =3D tmp; } return 4; - } else if (n < 80) { + } else { + uint64_t tmp =3D ldq_p(mem_buf); /* f32-f62 (16 double width registers, even register numbers only) - * n =3D=3D 64: f32 : env->fpr[16] - * n =3D=3D 65: f34 : env->fpr[17] + * n =3D=3D 32: f32 : env->fpr[16] + * n =3D=3D 33: f34 : env->fpr[17] * etc... - * n =3D=3D 79: f62 : env->fpr[31] + * n =3D=3D 47: f62 : env->fpr[31] */ - env->fpr[(n - 64) + 16].ll =3D tmp; + env->fpr[(n - 32) + 16].ll =3D tmp; } return 8; #endif @@ -249,6 +273,10 @@ void sparc_cpu_register_gdb_regs(CPUState *cs) #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64) /* Not yet supported */ #else + gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register, + sparc_fpu_gdb_write_register, + gdb_find_static_feature("sparc64-fpu.xml"), + 0); gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register, sparc_cp0_gdb_write_register, gdb_find_static_feature("sparc64-cp0.xml"), diff --git a/gdb-xml/sparc64-core.xml b/gdb-xml/sparc64-core.xml index 1c26d8c01c1..85b0820a408 100644 --- a/gdb-xml/sparc64-core.xml +++ b/gdb-xml/sparc64-core.xml @@ -39,54 +39,4 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/gdb-xml/sparc64-fpu.xml b/gdb-xml/sparc64-fpu.xml new file mode 100644 index 00000000000..d7151b34c7f --- /dev/null +++ b/gdb-xml/sparc64-fpu.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --=20 2.52.0