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Thu, 19 Feb 2026 09:18:19 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , qemu-arm@nongnu.org, Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Akihiko Odaki , Aurelien Jarno , Jim MacArthur , Eduardo Habkost , Peter Maydell , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Richard Henderson , Zhao Liu , Jiaxun Yang , Yanan Wang , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH v2 07/14] hw/mips: defer finalising gcr_base until reset time Date: Thu, 19 Feb 2026 17:18:03 +0000 Message-ID: <20260219171810.602667-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219171810.602667-1-alex.bennee@linaro.org> References: <20260219171810.602667-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771521613015154100 Currently the cpu_reset() in mips_cpu_realizefn() hides an implicit sequencing requirement when setting gcr_base. Without it we barf because we end up setting the region between 0x0-0x000000001fbfffff which trips over a qtest that accesses the GCR during "memsave 0 4096 /dev/null". By moving to the reset phase we have to drop the property lest we are admonished for "Attempting to set...after it was realized" but there doesn't seem to be a need to expose the property anyway. NB: it would be safer if I could guarantee the place in the reset tree but I haven't quite grokked how to do that yet. Currently I see this sequence when testing: env MALLOC_PERTURB_=3D43 G_TEST_DBUS_DAEMON=3D/home/alex/lsrc/qemu.git/te= sts/dbus-vmstate-daemon.sh UBSAN_OPTIONS=3Dhalt_on_error=3D1:abort_on_error= =3D1:print_summary=3D1:print_stacktrace=3D1 QTEST_QEMU_IMG=3D./qemu-img QTE= ST_QEMU_BINARY=3D./qemu-system-mips64el SPEED=3Dthorough MESON_TEST_ITERATI= ON=3D1 MSAN_OPTIONS=3Dhalt_on_error=3D1:abort_on_error=3D1:print_summary=3D= 1:print_stacktrace=3D1 PYTHON=3D/home/alex/lsrc/qemu.git/builds/all/pyvenv/= bin/python3 QTEST_QEMU_STORAGE_DAEMON_BINARY=3D./storage-daemon/qemu-storag= e-daemon ASAN_OPTIONS=3Dhalt_on_error=3D1:abort_on_error=3D1:print_summary= =3D1 G_TEST_SLOW=3D1 RUST_BACKTRACE=3D1 /home/alex/lsrc/qemu.git/builds/all= /tests/qtest/test-hmp --tap -p /mips64el/hmp/boston TAP version 14 # random seed: R02S0d3b1a4f1aef5198107851bdee539e7d # Start of mips64el tests # Start of hmp tests # starting QEMU: exec ./qemu-system-mips64el -qtest unix:/tmp/qtest-53018= 1.sock -qtest-log /dev/null -chardev socket,path=3D/tmp/qtest-530181.qmp,id= =3Dchar0 -mon chardev=3Dchar0,mode=3Dcontrol -display none -audio none -run= -with exit-with-parent=3Don -S -M boston -accel qtest main_cpu_reset: dbg mips_gcr_reset: dbg mps_reset_exit: dbg ok 1 /mips64el/hmp/boston # End of hmp tests # End of mips64el tests 1..1 Cc: Peter Maydell Message-ID: <20260108143423.1378674-9-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Pierrick Bouvier --- v2 - use proper 3-phase reset --- include/hw/mips/cps.h | 14 +++++++++++++- hw/mips/cps.c | 26 +++++++++++++++++--------- hw/misc/mips_cmgcr.c | 1 - 3 files changed, 30 insertions(+), 11 deletions(-) diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h index 878b4d819f4..1084a10de0f 100644 --- a/include/hw/mips/cps.h +++ b/include/hw/mips/cps.h @@ -30,7 +30,7 @@ #include "qom/object.h" =20 #define TYPE_MIPS_CPS "mips-cps" -OBJECT_DECLARE_SIMPLE_TYPE(MIPSCPSState, MIPS_CPS) +OBJECT_DECLARE_TYPE(MIPSCPSState, MIPSCPSClass, MIPS_CPS) =20 struct MIPSCPSState { SysBusDevice parent_obj; @@ -48,6 +48,18 @@ struct MIPSCPSState { Clock *clock; }; =20 +/* + * MIPSCPSClass: + * @parent_phases: The parent class' reset phase handlers. + * + * A Coherent Processing System model. + */ +struct MIPSCPSClass { + SysBusDeviceClass parent_class; + + ResettablePhases parent_phases; +}; + qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number); =20 #endif diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 620ee972f8f..23918147276 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -55,6 +55,17 @@ static void main_cpu_reset(void *opaque) cpu_reset(cs); } =20 +static void mps_reset_exit(Object *obj, ResetType type) +{ + MIPSCPSState *s =3D MIPS_CPS(obj); + hwaddr gcr_base; + + /* Global Configuration Registers - only valid once the CPU has been r= eset */ + gcr_base =3D MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; + memory_region_add_subregion(&s->container, gcr_base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr)= , 0)); +} + static bool cpu_mips_itu_supported(CPUMIPSState *env) { bool is_mt =3D (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_availabl= e(env); @@ -65,7 +76,6 @@ static bool cpu_mips_itu_supported(CPUMIPSState *env) static void mips_cps_realize(DeviceState *dev, Error **errp) { MIPSCPSState *s =3D MIPS_CPS(dev); - target_ulong gcr_base; bool itu_present =3D false; =20 if (!clock_get(s->clock)) { @@ -144,16 +154,11 @@ static void mips_cps_realize(DeviceState *dev, Error = **errp) memory_region_add_subregion(&s->container, 0, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic)= , 0)); =20 - /* Global Configuration Registers */ - gcr_base =3D MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; - object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, &error_abort); object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, &error_abort); - object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base, - &error_abort); object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr), &error_abort); object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr), @@ -161,9 +166,6 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { return; } - - memory_region_add_subregion(&s->container, gcr_base, - sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr)= , 0)); } =20 static const Property mips_cps_properties[] =3D { @@ -176,8 +178,13 @@ static const Property mips_cps_properties[] =3D { static void mips_cps_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + MIPSCPSClass *mcs =3D MIPS_CPS_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->realize =3D mips_cps_realize; + + resettable_class_set_parent_phases(rc, NULL, NULL, mps_reset_exit, + &mcs->parent_phases); device_class_set_props(dc, mips_cps_properties); } =20 @@ -187,6 +194,7 @@ static const TypeInfo mips_cps_info =3D { .instance_size =3D sizeof(MIPSCPSState), .instance_init =3D mips_cps_init, .class_init =3D mips_cps_class_init, + .class_size =3D sizeof(MIPSCPSClass), }; =20 static void mips_cps_register_types(void) diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c index 3e262e828bc..9e1c8d26ea5 100644 --- a/hw/misc/mips_cmgcr.c +++ b/hw/misc/mips_cmgcr.c @@ -214,7 +214,6 @@ static const VMStateDescription vmstate_mips_gcr =3D { static const Property mips_gcr_properties[] =3D { DEFINE_PROP_UINT32("num-vp", MIPSGCRState, num_vps, 1), DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800), - DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR), DEFINE_PROP_LINK("gic", MIPSGCRState, gic_mr, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_LINK("cpc", MIPSGCRState, cpc_mr, TYPE_MEMORY_REGION, --=20 2.47.3