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Thu, 19 Feb 2026 09:18:12 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Yoshinori Sato , qemu-arm@nongnu.org, Laurent Vivier , Thomas Huth , Marcel Apfelbaum , Akihiko Odaki , Aurelien Jarno , Jim MacArthur , Eduardo Habkost , Peter Maydell , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Richard Henderson , Zhao Liu , Jiaxun Yang , Yanan Wang , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC PATCH v2 02/14] target/m68k: initialise pc/sp vector during reset Date: Thu, 19 Feb 2026 17:17:58 +0000 Message-ID: <20260219171810.602667-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219171810.602667-1-alex.bennee@linaro.org> References: <20260219171810.602667-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771521532637154100 All 68k chips should be able to follow the architectural behaviour on reset which is to load the initial sp/pc from the first 8 bytes of the address space. To avoid any potential issues with un-reset memory controllers we punt the final setting of the register to the exit phase when everything else is guaranteed to have been through the hold phase. Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Pierrick Bouvier Reviewed-by: Thomas Huth --- target/m68k/cpu.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index d849a4a90fc..0dce8ef282e 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -25,6 +25,7 @@ =20 #ifndef CONFIG_USER_ONLY #include "migration/vmstate.h" +#include "system/memory.h" #endif =20 #include "cpu.h" @@ -174,9 +175,25 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType= type) } cpu_m68k_set_fpcr(env, 0); env->fpsr =3D 0; +} =20 - /* TODO: We should set PC from the interrupt vector. */ - env->pc =3D 0; +/* + * We defer the final setting of the PC to the exit phase to ensure + * if any memory controllers need to be reset they are before we read + * the initial reset vector. This is a NOP for user-mode which will + * set the PC in init_main_thread() after the CPU is reset. + */ +static void m68k_cpu_reset_exit(Object *obj, ResetType type) +{ +#ifndef CONFIG_USER_ONLY + CPUState *cs =3D CPU(obj); + CPUM68KState *env =3D cpu_env(cs); + + env->aregs[7] =3D address_space_ldl_be(cs->as, 0, + MEMTXATTRS_UNSPECIFIED, NULL); + env->pc =3D address_space_ldl_be(cs->as, 4, + MEMTXATTRS_UNSPECIFIED, NULL); +#endif } =20 static void m68k_cpu_disas_set_info(const CPUState *cs, disassemble_info *= info) @@ -396,7 +413,6 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error = **errp) =20 m68k_cpu_init_gdb(cpu); =20 - cpu_reset(cs); qemu_init_vcpu(cs); =20 mcc->parent_realize(dev, errp); @@ -641,7 +657,8 @@ static void m68k_cpu_class_init(ObjectClass *c, const v= oid *data) =20 device_class_set_parent_realize(dc, m68k_cpu_realizefn, &mcc->parent_realize); - resettable_class_set_parent_phases(rc, NULL, m68k_cpu_reset_hold, NULL, + resettable_class_set_parent_phases(rc, NULL, + m68k_cpu_reset_hold, m68k_cpu_reset= _exit, &mcc->parent_phases); =20 cc->class_by_name =3D m68k_cpu_class_by_name; --=20 2.47.3