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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497252; x=1772102052; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ymWsJOl3EYWNePVYcoHaSpgh8B6NORXwc2lcKaczgL4=; b=dXu0AxhBlF2UB3Vkx22FKgAZvN8g92FEu2IUXA+Vx0Izv1jpnYBZTF6ScjnbgBA5EN S5KSE4x3K1XwWo3kgpE0+AQX3E9e7/Sz/d3EHpjWBlIl2LPw4yAcFFeDWhq2NmLHA55x 1G0vhUT0k0WES6MBYcPOTVJj7O3xuKWty1v/FigKp/I7EdKualehYjoDFKVut56Wa8N2 TvK+3S9cPur79IViq/FzWrzKqExoqk2AWXQYzbHYGyCTkitKFHhbh4ietQ0KWNzbhSxD rQcrSzSgR2eKy47WpVjJJ/iGyJi0Gqn9c3E4ga/9FWFHqqdyoXy9gtjSlr9MDXgyQqRM gH5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497252; x=1772102052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ymWsJOl3EYWNePVYcoHaSpgh8B6NORXwc2lcKaczgL4=; b=MD/EKtkPnimeBVaqlEgW2CGhK3nkMRq10fHjPoIb1X7pgT+VHVe9NCSd8JTz2zn4lA hC+BRm/MaKlmJytOYXLnSqQDk4wUzmjetleQo0/reVfHJEGMCf65OMzPpvG+JspaNcsk icx5Re+ZMgqPHNBs8J5krtfwEDo3/SQhTG3nJM+8sNaNRwvrh67sC7hfX3Znzrq7QAUP mf4cko2JrlrMY7GuIKlU9IZ9Kr3mqC/X6Fu2skkEaNTLQYGecAZhfNptUC1aqU2yENmZ W/lyvDYhbTCJiy901mOHO5CQIo2tFfBuzK+emJB/5YGow53hy55LRTWyhFyB8b7v+rzt uR4Q== X-Gm-Message-State: AOJu0YzACWNwxyPFAsiXMIBdsmwPBHTBcfftb8hsX2bJYj0kpDYk5POb TQQpmVwwFW0ZxflaFoX3QkzjIGHUupFY2Hp6PPXXe73b+7WffDL81i2KM6p/zZf40SOSZ6X8T1Y H8nG0 X-Gm-Gg: AZuq6aKkdwdshrOejkQeiMT0VrHbO2gQYPq4TshT4SDM48ZY1TDDgpUE2pXcT7NJW2w IS3UjpfMxjjqwL7mdsN8ZDYyQTNsRa7GxzajwyBVP4dTURJnpKor3p2MKmrvVCU0DypZWtJG+Ew P4LEwN/6e2MsN31HK3x+rEgfD1kglCRYHeGCQYk0GAaD2wArsOCRoJY7nHvkO/QHUpE56GEZCGf C0KaMwmCxnSYcOm1Vc9cOXKIlfZX4fumG8m6Qqgnlxl8qoxsTZvq45gfrKIiXaZ7WGUDCR5YnBq 87/I2kzA21cF7Hkzr8tMeElIHNWJhyMj8fNmd30VvnEy/pcrWP7xaQR0LtEmGlXpQMFtKw+8laq zdIaGMdAJ9g2JrOVCXNznvGrHDCCbq3FZvOUbPzp3TUhvGW6CJgUMay3EVa6K1H5HSrz789lJTu VCgz7rW179MzGD9yLtdRPjrtOVxNcmMadY702T+f8t1WQhcHHml2HadtEBSCjkgaW9oPNOjzHgD 8d35Xuah2+pZBkuGLDaR/hm96v5uyM= X-Received: by 2002:a05:600c:6912:b0:483:709e:f22d with SMTP id 5b1f17b1804b1-4837108fc46mr350480895e9.27.1771497252205; Thu, 19 Feb 2026 02:34:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/32] target/arm: Don't let 'sme=on' downgrade SME Date: Thu, 19 Feb 2026 10:33:38 +0000 Message-ID: <20260219103405.3793357-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497359393154100 Content-Type: text/plain; charset="utf-8" In our handling of the boolean 'sme' CPU property, we write this 0/1 value directly to ID_AA64PFR1_EL1.SME. This worked when the only valid values in that field were 0 (for no SME) and 1 (for SME1). However, with the addition of SME2 the SME field can now also read 2. This means that "-cpu max,sme=3Don" will result in an inconsistent set of ID registers, where ID_AA64PFR1_EL1.SME claims SME1 but ID_AA64SMFR0_EL1.SMEver claims SME2p1. This isn't a valid thing to report, and confuses Linux into reporting SME2 to userspace but not actually enabling userspace access for it. Fix this bug by having arm_cpu_sme_finalize() fix up the ID_AA64PFR1_EL1.SME field to match ID_AA64SMFR0.SMEver. This means the "sme" property's semantics are "off" for "no SME" and "on" for "enable at whatever the default SME version this CPU provides is". Update the documentation to clarify what 'sve=3Don' and 'sme=3Don' do. (We don't have the equivalent bug for 'sve=3Don' because ID_AA64PFR0_EL1.SVE only has 0 and 1 as valid values, but the semantics of the property are the same.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Manos Pitsidianakis Message-id: 20260202133353.2231685-6-peter.maydell@linaro.org --- docs/system/arm/cpu-features.rst | 10 ++++++++++ target/arm/cpu64.c | 15 +++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 37d5dfd15b..024119449c 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -318,6 +318,11 @@ SVE CPU Property Parsing Semantics provided an error will be generated. To avoid this error, one must enable at least one vector length prior to enabling SVE. =20 + 10) Enabling SVE (with ``sve=3Don`` or by default) enables all the SVE + sub-features that the CPU supports (for example, it may also + enable SVE2). There are not generally any lower-level controls + for disabling specific SVE sub-features. + SVE CPU Property Examples ------------------------- =20 @@ -430,6 +435,11 @@ and all vector lengths must be powers of 2. The maxim= um vector length supported by qemu is 2048 bits. Otherwise, there are no additional constraints on the set of vector lengths supported by SME. =20 +As with SVE, ``sme=3Don`` enables all the SME sub-features the CPU +supports (for example, it may also enable SME2), and there are +no lower-level controls for fine-grained disabling of specific +SME sub-features. + SME User-mode Default Vector Length Property -------------------------------------------- =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5d7c6b7fbb..4d316f5a71 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -366,6 +366,16 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) =20 cpu->sme_vq.map =3D vq_map; cpu->sme_max_vq =3D 32 - clz32(vq_map); + + /* + * The "sme" property setter writes a bool value into ID_AA64PFR1_EL1.= SME + * (and at this point we know it's not 0). Correct that value to report + * the same SME version as ID_AA64SMFR0_EL1.SMEver. + */ + if (FIELD_EX64_IDREG(&cpu->isar, ID_AA64SMFR0, SMEVER) !=3D 0) { + /* SME2 or better */ + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, 2); + } } =20 static bool cpu_arm_get_sme(Object *obj, Error **errp) @@ -378,6 +388,11 @@ static void cpu_arm_set_sme(Object *obj, bool value, E= rror **errp) { ARMCPU *cpu =3D ARM_CPU(obj); =20 + /* + * For now, write 0 for "off" and 1 for "on" into the PFR1 field. + * We will correct this value to report the right SME + * level (SME vs SME2) in arm_cpu_sme_finalize() later. + */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value); } =20 --=20 2.43.0