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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497261; x=1772102061; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UzzJHiP4Ww50cmlpD5s1nBOWMQn5ZNOxnnLL7RIFj0M=; b=zWNhNe3OgheL1ChsjxqgCT/oRi/DR/i9biBiYST/TG7UFNYn7mg0j0cU8fXa5x2pF2 3sDM/sw/r1xchUI50Mr2cljIYwU+A9m1Kjq32DPjFZ9nlS5iM/ic9T9J1+tFUxm7gZ4b R7z+Zx075e+AWXdjQjnYMF6Runz8b99WL4zAf/zfHwXvlZN/8MVm3gMO1WYpzs3orTAo rtmOhSvA5lCisFFw1zBSwUl4yjKcFqRDOxDL9YuKvC4xWXeaR6+4YhUfa/QLFESt7mMQ aUl0hzTGPijmezISEna40ayvIGFqu1qDuonuDzYa1vse+fRCifR//oDlRePfA3drCho7 KQPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497261; x=1772102061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=UzzJHiP4Ww50cmlpD5s1nBOWMQn5ZNOxnnLL7RIFj0M=; b=cE0pXtBZ8U1BCcqvd9ksZLcD1YdZDh44jXSnoQKZsye75YKiemXPtr2TeBroOddKEc kaHAdxRrY4bDoU0HL15wF7HWyq6emD1rxb+A1hjNQQwlBTN1mOxSTRwSAZJaMhc7SwFf E6IWKSlKJ3o4dsG0UPZUW5U+pn4pdUkNeTsl+p0G3BXTmqajFS+W2buFRpZbX//ioPdb pAsmQnOvUOyeFvCAFtOcyOYRtWLHnYIXrYsFOBv4zHZ8D9iIInoo5n5JYwIVxplt+ira QC+2d33PDjaKyCm3FEuy0VHDBUGMYPHxYUzw4a4dCUEnXVzJ27HhEnX1WhnsXxPDvUux Jq+A== X-Gm-Message-State: AOJu0YwmKvNkapdGLpsRitf+ZAzmAzSu4xTY0nVLiZGxyvFNVwrk9we+ WMsk1EeCnAKMdNr9EM9vX4Umrb9mo40HuKlSpgCRdOoJEyTyM443qB5jZ0KTBoKyaoWhGGLmsBi ztZ70 X-Gm-Gg: AZuq6aIvaAf6JEWNTDhXkXrsHiIKDGgB0ANsym2h9shBHmEMjzCZrFe82pNHHC7zxuu Ug9ZiyOkVNAUHN1Upfpjoh242filS3yzktIvI+q1BLiGUJzzqopGuv9IcIRQFc6V/xxKxoZ0J8B fTXkoYi80OREoFm2Gkh6APnahL/cQG2zGj/OfT2dYK5yv6ROKMXETzO4l08hkE0mHO+/jEPAGwg E7mKq281h6GYmQhyd4y21P7r11UV//tQxsWCYFNoRPyz9jw2QyLWyR7grENLYl/4amnZkaxNx9I HJCnoXMMDcnjneaOhvBIPB0G2c5DlKm2dFJGQcDzAycBrTCwjI38T0bQZvshwTILfCpBxHyDa4g 6rtx5r0F58Xf0Tgsm2aAr5rp6uMlU4hWsXMHTh2gUSPqGFnXQGMaFFY3JtXyO3Klb+8RKT2OhwW YYRXhWxhA+4KlVhYPpbn2xB8AvDJazYU478fDdiWQoA5yAcpyKRuBbmb3Xk2gKZObQLa9IFGXJS d7YOS/yk85zzp4531WwZCUFiFt+KqU= X-Received: by 2002:a05:600c:8b84:b0:483:4bbc:89ea with SMTP id 5b1f17b1804b1-48379c42db1mr290411605e9.37.1771497260764; Thu, 19 Feb 2026 02:34:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/32] target/arm: Permit configurations with SME but not SVE Date: Thu, 19 Feb 2026 10:33:48 +0000 Message-ID: <20260219103405.3793357-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497354319158500 In commit f7767ca30179 ("target/arm: Disable SME if SVE is disabled") we added code that forces SME to be disabled if SVE is disabled. This was something we did in the run-up to a release to avoid an assertion failure in smcr_write() if the user disabled SVE on the 'max' CPU without disabling SME also. Now that we have corrected the code so that it doesn't assert in an SME-without-SVE setup, we can let users select it. This effectively reverts f7767ca30179. Note that this now means that command lines like "-cpu max,sve=3Doff" which used to turn off SME and SVE will now give you a CPU with SME but not SVE. This is permitted by our loose "max can always give you extra stuff" rules, but may be unexpected to users. Mention this in the CPU property documentation. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Peter Maydell Message-id: 20260202133353.2231685-16-peter.maydell@linaro.org --- docs/system/arm/cpu-features.rst | 10 ++++++++-- target/arm/cpu.c | 10 ---------- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 024119449c..3db1f19401 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -323,12 +323,18 @@ SVE CPU Property Parsing Semantics enable SVE2). There are not generally any lower-level controls for disabling specific SVE sub-features. =20 + 11) Disabling SVE does not automatically disable SME. If you want to + disable both you must use ``sve=3Doff,sme=3Doff``. In particular, + for the ``max`` CPU, ``sve=3Doff`` alone will give you a CPU with + SME only (and which therefore still has the SVE vector registers). + Most users will want to disable both at once. + SVE CPU Property Examples ------------------------- =20 - 1) Disable SVE:: + 1) Disable SVE and SME:: =20 - $ qemu-system-aarch64 -M virt -cpu max,sve=3Doff + $ qemu-system-aarch64 -M virt -cpu max,sve=3Doff,sme=3Doff =20 2) Implicitly enable all vector lengths for the ``max`` CPU type:: =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7542444b18..10f8280eef 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1580,16 +1580,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **= errp) return; } =20 - /* - * FEAT_SME is not architecturally dependent on FEAT_SVE (unless - * FEAT_SME_FA64 is present). However our implementation currently - * assumes it, so if the user asked for sve=3Doff then turn off SM= E also. - * (KVM doesn't currently support SME at all.) - */ - if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve,= cpu)) { - object_property_set_bool(OBJECT(cpu), "sme", false, &error_abo= rt); - } - arm_cpu_sme_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.43.0