From nobody Sun Apr 12 04:23:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497272; cv=none; d=zohomail.com; s=zohoarc; b=SYimfZNUbnxbSpn2z5gPaBQBiWd/M5NEz84CbRwhJs9YRvbQAoiODveXHEhRZpVwAQB0JqBDGY06l4wmg/3lRGlw7wCDK6YFTLobp3K1dqi4tG2UjZNseOgiGMZKh82DCIgp/RLxNvtx8xfzz+fPcUF1ZBgJxGNFUaJ7uKvsvy8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497272; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=fZqFlJE71QpBgupRkc1HcKWWAy8MPJgu6Npsxt6eiZI=; b=AvKFYF0Wwpf2dCDj5eR6iJr6ZeR1o550L+g4w6b+61OkZEnhSH0ZORDeL/10ACZ3uXmN11MWverDKb3C9Vinxy4gR95RVh7yR4qtw9SyzC/WvKmpiyNqGnHJ0ladUXF1X5lZrHlwuniX1NsjTQhGURDa/eP+Mk/qWZUg5NlNw10= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497272631706.4334946802447; Thu, 19 Feb 2026 02:34:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1MY-00079F-Kv; Thu, 19 Feb 2026 05:34:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MM-00073t-Ou for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:16 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MI-00061b-7c for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:12 -0500 Received: by mail-wr1-x444.google.com with SMTP id ffacd0b85a97d-435f177a8f7so743924f8f.1 for ; Thu, 19 Feb 2026 02:34:09 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497248; x=1772102048; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fZqFlJE71QpBgupRkc1HcKWWAy8MPJgu6Npsxt6eiZI=; b=x5SAUUMPJg6mJ5TRk/JQAU44OVb8jiEXBw3DToxJ1dKWdUyInQr1cir7JOtiYnWok/ ONRXhZvNN6vvalLuwVefqQ0KNjxW3yph2vM9HWAX5DA8gxsRyA+1nbDle4EXPEwoa0aG QnkObcoJ1nMTa+BVhxZ6RQ1xdgfJWgo1TA4E+jkjhzIyyPfdMcard3NHVuCmSmA/n5bP afv3gOzIsdx1i0myVyxKc6EVwZyZ4yGiR65+nhRmOuIAteBl969QAjBjQcVUZ9YSyY96 O0nYtvPj9m4hxw8XL69B0x2F8c0xcgQwsqSmQpiZYq6U0VPgXV9EVccLNrmrBK7qaVKm GT7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497248; x=1772102048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=fZqFlJE71QpBgupRkc1HcKWWAy8MPJgu6Npsxt6eiZI=; b=IAz+3P3gexV2Mj356sk8X8ngTOF4GIKlw+HBdHCTIRaImDXKzC3XuzJhp+kE2sNikD +uWA8Hh906OO6hs/vmdEnunrys9bwzYCD4JQL5UgtKfPINvkp9QQzMRLliIsIsJbddUL zHsXpb0jkg757kQHmWbhX3ZMtSGOqxQOTrhPTmjTBkvoC5sCeqYfuolYCbGJsI0yMgoV QKI4JMSzoJ1RFuTsCdIlSgCX0rOBj0TsY9Yr/Xx/4IlNVqa3lmthaK5Xc5rWl7E3Jxul dNCnkvOTzFR3I83Bmf0HyIejkV2cR+wYUVIPRhiYSU0Xn3xfnv2goWjYc4bZ3iGQTv3Q rS3Q== X-Gm-Message-State: AOJu0YzCef4BT+qBFWkI6IGSJPGepBO4UTQujTajLxXDAt3vbLgflX48 vlCAA8YEH0/IRkYU9FW/XG/wlKI3889xfmnsztx5oO2F+5jRXvnpcfXtKTRbfqBQtMXOa8F5djK xA5QINNU= X-Gm-Gg: AZuq6aLbbej9i/5tyWcm23v9PMtbCY6Xtus6DQuo1Wps0Hl523tv+kRcqheW2Q5PrY5 +NFisLR+OWoKg0q4KdiwI4dVldKn8KYYlM/8m1zdba1YjDnfSBkpgm27ufqiwdkqKssG2S7WfZR 0hSrWMRHGQ8oiBUDz/hB/tZP/Du6hJJJ48jLZg5Ny9SBSU+Ic06Liww//1f4J9pxL2+JpAhEMCI e6IOaoSkAKl4s8z4DbGjRb1P1rM3laE8ZzU4UYf2ZDUAB96i3C5qOlU+RuckSKXbSJIMwLwTctO OJeAGw6ZeuS3YnfVZd7dPwfctZEdQzxOkeBdRfhEB6S2cizTi8Ggk0TAyWv7ItDu2vmNJiSWN6B It/wPr4QXyOvoGqgxH8tbwtwkC8bGmvywvTNX3GYiJqsPjSYWxRoSWI5adLm1G8UdK0n3Xn1wAT 7GaPbBC7frn+EXZXR0kZj9swVUJZp/3X5NM+3wK2CWmWVL1s4KWMfroE9VRpYU6xn0izg1hyEWH x+2jdSFq/vK+H+erbNGtQ4s/6a0784= X-Received: by 2002:a05:600c:83c6:b0:477:639d:bca2 with SMTP id 5b1f17b1804b1-48379b93357mr253017505e9.4.1771497248090; Thu, 19 Feb 2026 02:34:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/32] target/arm: Account for SME in aarch64_sve_narrow_vq() assertion Date: Thu, 19 Feb 2026 10:33:34 +0000 Message-ID: <20260219103405.3793357-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-Spam_score_int: 0 X-Spam_score: -0.1 X-Spam_bar: / X-Spam_report: (-0.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_PH_BODY_ACCOUNTS_POST=1.995 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497274245154100 In aarch64_sve_narrow_vq() we assert that the new VQ is within the maximum supported range for the CPU. We forgot to update this to account for SME, which might have a different maximum. Update the assert to permit any VQ which is valid for either SVE or SME. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20260202133353.2231685-2-peter.maydell@linaro.org --- target/arm/helper.c | 2 +- target/arm/internals.h | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8c5769477c..373f0ebcb3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10088,7 +10088,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsign= ed vq) uint64_t pmask; =20 assert(vq >=3D 1 && vq <=3D ARM_MAX_VQ); - assert(vq <=3D env_archcpu(env)->sve_max_vq); + assert(vq <=3D arm_max_vq(env_archcpu(env))); =20 /* Zap the high bits of the zregs. */ for (i =3D 0; i < 32; i++) { diff --git a/target/arm/internals.h b/target/arm/internals.h index f7b641342a..8ec2750847 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1808,6 +1808,15 @@ static inline uint64_t arm_mdcr_el2_eff(CPUARMState = *env) ((1 << (1 - 1)) | (1 << (2 - 1)) | \ (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) =20 +/* + * Return the maximum SVE/SME VQ for this CPU. This defines + * the maximum possible size of the Zn vector registers. + */ +static inline int arm_max_vq(ARMCPU *cpu) +{ + return MAX(cpu->sve_max_vq, cpu->sme_max_vq); +} + /* * Return true if it is possible to take a fine-grained-trap to EL2. */ --=20 2.43.0 From nobody Sun Apr 12 04:23:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497468; cv=none; d=zohomail.com; s=zohoarc; b=SBedSdlLCsi4n/Xuca8RntUf5Cgzb1mJ+lVFMLdZry5j+fGgsxTEWP1TOx4/hBrhoz8NpuuCzm/COxFZTe5eE0RWu4UvShNqR0Wc/1HCYQp/+DKKiA1e6jgH6z+0xVAUT9fwaybj78kuq2xcZdAfkozazRvNuwr9iboxontfLzk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497468; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ke4c6OiHVAc47JjS0Vki7YyrrpZ38dBDsvhKeDXkXZ0=; b=l+M67O3XF+lqxu7PokYV68u9RpjoFrIt+tCm8j5W1P/EgrX6A3XjpIuIpht8JHqU/he5wsAV33sJ+6Ie+HeFnXewNoA8ujG4dZonz0PPh/lVScFE2u3TSz0twPm/V7RnYLk2zfZogQoS4Gi3uQ/1koCA6E3+sJaph0Uonw8ueAM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497468625540.712733440011; Thu, 19 Feb 2026 02:37:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1MZ-0007Av-CX; Thu, 19 Feb 2026 05:34:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MO-00074F-Sc for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:18 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MJ-00062I-CM for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:14 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4837907f535so6932725e9.3 for ; Thu, 19 Feb 2026 02:34:10 -0800 (PST) Received: from lanath.. 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We always report the Zn vector registers with a width based on the maximum SVE vector register size, even though SME's maximum size could be larger. This is particularly bad in the case of a CPU with SME but not SVE, because there the SVE vector width will be zero. If we report the Zn registers in the XML as having a zero width then gdb falls over with an internal error: (gdb) target remote :1234 Remote debugging using :1234 /build/gdb-1WjiBe/gdb-15.0.50.20240403/gdb/aarch64-tdep.c:3066: internal-e= rror: aarch64_pseudo_register_type: bad register number 160 A problem internal to GDB has been detected, further debugging may prove unreliable. Report the Zn registers with their correct size. This matches how we already handle the 'vg' pseudoregister in org.gnu.gdb.aarch64.sve: we call sve_vqm1_for_el(), which returns the vector size accounting for SME, not the pure SVE vector size. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Message-id: 20260202133353.2231685-3-peter.maydell@linaro.org --- target/arm/gdbstub64.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index c584e5b4e6..b71666c3a1 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -158,7 +158,7 @@ int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *b= uf, int reg) case 0 ... 31: { int vq, len =3D 0; - for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { + for (vq =3D 0; vq < arm_max_vq(cpu); vq++) { len +=3D gdb_get_reg128(buf, env->vfp.zregs[reg].d[vq * 2 + 1], env->vfp.zregs[reg].d[vq * 2]); @@ -174,7 +174,7 @@ int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *b= uf, int reg) { int preg =3D reg - 34; int vq, len =3D 0; - for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { + for (vq =3D 0; vq < arm_max_vq(cpu); vq =3D vq + 4) { len +=3D gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]); } return len; @@ -208,7 +208,7 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf,= int reg) case 0 ... 31: { int vq, len =3D 0; - for (vq =3D 0; vq < cpu->sve_max_vq; vq++) { + for (vq =3D 0; vq < arm_max_vq(cpu); vq++) { if (target_big_endian()) { env->vfp.zregs[reg].d[vq * 2 + 1] =3D ldq_p(buf); buf +=3D 8; @@ -233,7 +233,7 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf,= int reg) { int preg =3D reg - 34; int vq, len =3D 0; - for (vq =3D 0; vq < cpu->sve_max_vq; vq =3D vq + 4) { + for (vq =3D 0; vq < arm_max_vq(cpu); vq =3D vq + 4) { env->vfp.pregs[preg].p[vq / 4] =3D ldq_p(buf); buf +=3D 8; len +=3D 8; @@ -540,8 +540,8 @@ static void output_vector_union_type(GDBFeatureBuilder = *builder, int reg_width, GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cs, int base_reg) { ARMCPU *cpu =3D ARM_CPU(cs); - int reg_width =3D cpu->sve_max_vq * 128; - int pred_width =3D cpu->sve_max_vq * 16; + int reg_width =3D arm_max_vq(cpu) * 128; + int pred_width =3D arm_max_vq(cpu) * 16; GDBFeatureBuilder builder; char *name; int reg =3D 0; --=20 2.43.0 From nobody Sun Apr 12 04:23:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497477; cv=none; d=zohomail.com; s=zohoarc; b=DhAvZ20CbWpd0IWlRyXyrCQyf5FF/m4hqNakyAi5vZpNo7hNX5Z3wX4agu7IeI/fnNWu5CtVK3LHgBuRt23lmVIxC+YYd0J22Ssks00tFA1xD4lrsv90tQrvK7yc1UsBHp1sSXBLRzi9pzpsTJgJdP5hoOMeM0qGa3unLgaIsCI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497477; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=z+HsSXvuuArtw7MqtuqE1Qn/nOwCvrNl8C8HwnH0cuo=; b=cIQ82YPi0Y43Lv0LbOFZSixnJfPTkPV+CQ5quRP+Z7xqwBUeB6laS8KOnEhe0TDeATwVckptTt7FGLlKdQCFiw2dzq9TMa6eL5SUJEvLZeE6iOA01IrqwHZE9+O3o/UvsWxPwIGRSfXJLg4b4H1zdHjVuFxWsgSk4n4CJ23A2/w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497477845444.1475642994718; Thu, 19 Feb 2026 02:37:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1MZ-0007B7-Jr; Thu, 19 Feb 2026 05:34:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MO-00074E-SD for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:18 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1ML-00062W-73 for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:16 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-483a233819aso2430625e9.3 for ; Thu, 19 Feb 2026 02:34:11 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497250; x=1772102050; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=z+HsSXvuuArtw7MqtuqE1Qn/nOwCvrNl8C8HwnH0cuo=; b=lmk9AauWKIFe1i4wtVIKq3hu/vmBPLTWWsjNFlzVx+rCfFz+ueKvUfLtvVrIX6JBZf no3c2WfZToQtQHy7rUtLaaSvfqfLbgIN3PPRLn+6EUPvYkpfptjNaBm9ILdRX+5O69/a 66pyuJ3CN+z/TDmHuX8YqrlMAaufY0sXRJZlqAZUbAIL1S/JB9TOTzDfbbidtL1czkP3 XtEIiQkZmyVqxy+53FiS3AkFGGtrunSyYEdW3Sf6mMSU3uQ3qWSvflacvH1nzU9eO1AW xU/QUpgmEUgTCA5fcrySU1GcZEp0A0DaInyUn1tDlYHh1XyUIKsEFViVZB1EnHs8D2GJ TXvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497250; x=1772102050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=z+HsSXvuuArtw7MqtuqE1Qn/nOwCvrNl8C8HwnH0cuo=; b=lzClccr9I09ZEXQVGdOZg9MhYrKlmBq2+/621cTfAmZa7mnIfTS602mSgfWDzzBkcr k7b/RBMMTIg6lY/vQbU+pt1qEwb5VVQejvnQQBX/9bYusOIr097EkGU0AWRZ+14hs06Y LjF9Moa/LmjVqAhEQJUm+NGol2uUkX309BDFCsXexneQbH6W6UM74tKYz3W8RLqynrWi jGh/v/rZpCzlRjjmuJOG40hgDztMkIGvM+HXPfb7liHG5D5nDtzS+fDLA8QrNUWB7ze8 K5CQ8niRaXTtHiG7bFzoKH/uJKX99mT7YZQlh36Ou9Dk5jM5bADL8z8wJxouaTty4nXW 4MfQ== X-Gm-Message-State: AOJu0YyFGmtjvsG5ZeFD21g/T73hGVU8ahJeHf22Md0fSPm7L7S5fKY9 20TJNrQjtOpNkeIrnP8W7PXmXmUlZDjHsT9/eF+3zGxG+XyGzk8t5OAD8aW9l8RPnWSeiQXombT 5YyBJ X-Gm-Gg: AZuq6aI4SmbJckEPiRBtsiioz245e71yTnsF/7KMOO9aeDtwSUTvrfVLrJCfGq434AX hl+Dc+K77li1WrQRNu8FwFeY16XrdJhFg9OprHKj4VG3Z52K6aizVTgKHjedWl6okl6B7QRHBdO xJ8MCS9og+Nvd+lLa3jINSy1yCndGGUyiZaqTRCc38utmzgI7Z5nN9/VAGWwgQ5XvwyosY7hLB3 /p5G/Zc29ZFOjOlZj18uTpyk5dNyDmkJhU0AapNsl2vLsjDyXlL0l1oL0f6YBR5j5hZ2rpSAh6z ptDsZKsNaWqmdgeCO/YzCnOoaxEzQJMCfjc0DrA6vZBYP7ffyqyK91W0TDMFaNJiffcbmTO3VOc P3m6HX/eG1+kqVLSaf4KM/30atXGdT88UnUs18D2tChxzsQdLLSEV1ou2Fy0TLkEk54IEr0aHSU fIKzoTnKJiDM2a/9tEfyBmp7BKJoPcyCsNg7hqMmkSGZeY1LWYX5fiA6qLtetuB5hQRURz/aRgd fVtofSW4RN0szx72adlfk0dXRPLKHo= X-Received: by 2002:a05:600c:c492:b0:483:8e43:6dce with SMTP id 5b1f17b1804b1-48398b6e014mr75039185e9.29.1771497250500; Thu, 19 Feb 2026 02:34:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/32] target/arm: Fix feature check in DO_SVE2_RRX, DO_SVE2_RRX_TB Date: Thu, 19 Feb 2026 10:33:36 +0000 Message-ID: <20260219103405.3793357-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497479203154100 Content-Type: text/plain; charset="utf-8" In the macros DO_SVE2_RRX and DO_SVE2_RRX_TB we use the feature check aa64_sve, thus exposing this set of instructions in SVE as well as SVE2. Use aa64_sve2 instead, so they UNDEF on an SVE1-only CPU as they should. Strictly, the condition here should be "SVE2 or SME"; but we will correct that in a following commit with all the other missing "or SME" checks. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Manos Pitsidianakis Message-id: 20260202133353.2231685-4-peter.maydell@linaro.org --- target/arm/tcg/translate-sve.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 64adb5c1ce..81f487152c 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3769,7 +3769,7 @@ TRANS_FEAT(UDOT_zzxw_2s, aa64_sme2_or_sve2p1, gen_gve= c_ool_arg_zzxz, gen_helper_gvec_udot_idx_2h, a) =20 #define DO_SVE2_RRX(NAME, FUNC) \ - TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzz, FUNC, \ a->rd, a->rn, a->rm, a->index) =20 DO_SVE2_RRX(MUL_zzx_h, gen_helper_gvec_mul_idx_h) @@ -3787,7 +3787,7 @@ DO_SVE2_RRX(SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_= idx_d) #undef DO_SVE2_RRX =20 #define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \ - TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzz, FUNC, \ a->rd, a->rn, a->rm, (a->index << 1) | TOP) =20 DO_SVE2_RRX_TB(SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false) --=20 2.43.0 From nobody Sun Apr 12 04:23:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497292; cv=none; d=zohomail.com; s=zohoarc; b=BfsU1n9v8i0ZGe99DC7QvPE9YxCGzEgCn8aX3ukjogpn3H4YFuOPnsBGqAAEvm1QxYqQ45HZ7tpcnxf/mFg/VQ3g8EGhwkXxC6COQ6WHZluiJs0q7YE/6ES+WJV/XXoUMqbzv4uK5wXD+zl9Su2OE04bFlThmveLjxefiBetsuk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497292; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=qB0g51eHPIGsbFIfbn6u6D25SBHy9hNdGol0ul1NVHo=; b=a1hvC9zmHM9Wn0enRM6z+4zdf251sjXFtFAIaxl+YXtHqaG2OOPVCp6d0nvMLKAtqW8OfylyMo1fnWOtDhl3BwJK61aG62ycdmJuUbDOMEfgWjMGFwZ8ILYgm+3pfHwbDDJt0EUBN5IITKnjn/UBtTnyZI3uLef0QSrDWopyOCw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497292189113.58422763096485; Thu, 19 Feb 2026 02:34:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mb-0007CJ-1e; Thu, 19 Feb 2026 05:34:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MT-00075f-J1 for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:22 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MM-00062n-5u for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:17 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-48069a48629so7844705e9.0 for ; Thu, 19 Feb 2026 02:34:12 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497251; x=1772102051; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qB0g51eHPIGsbFIfbn6u6D25SBHy9hNdGol0ul1NVHo=; b=UoS8GPVoLJmcrGU9NYTEDmLdDFRxPWxgn+UueTzlVzZqcvr6DemkFLiTSgycndDX02 9wb2AzhLgf/pMMGOfNornCi3sOix2qFzW8tdoQOLPhZl9XBHR8maGCJeMkZnbH+wUQiW HrIdBB76q/KI9opTZhtpdDzTfxqqNHdCWBKioablk/rLJW9bG0ZMhpjwv6zowga9vV8D SyoEfUZVyxbe+wKRad4NhpDhe4iyDPEPDfjx+WHRW/Zl+r0Au7Zw2eBOJF9ZxG2C3ytJ XX0NJ2vy2yk79eFgehKnjAOiau2QsIA/2Ma1Dh1Y7flaMKRhw+1SWtefyt8P0Yp+K7qC B+Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497251; x=1772102051; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=qB0g51eHPIGsbFIfbn6u6D25SBHy9hNdGol0ul1NVHo=; b=fhAEK22nCD6h37ztT5QkiEeV8A9bhGb1IE2cD0EuPyZNtMxH9gFPKr/SMpLjSN5nNg RKC73NGXC6u4Qqf/kxvCnWG8Us7Qbvq29qSDUpRTrEqYniPrspPn/sodIdLX758TtCE3 y5nCD4kFdZqf8KKzB6OtUuxmb+xvaAickngkmERzQZ1D9JhC+vw+wYrypUY2q3qJ86Kz ZkaG/xDuh9A8/S+ntClCSRyrbxHMgCPBpzvbX2jWgZzgvbbg6CIxgE0OYdJH8Fuq5BBB yyMfbhdhVxU/Ro+Pp+m2diC0auVpjN6PYPZwu+82Fcn06elbf+KIdHe07BShzV9TNXb8 i9zg== X-Gm-Message-State: AOJu0YwW7O8fd4dGSSOAAUsXn7gV0ATAEtxVM+hL4GZw8FcM004Mpx8Z br31Cvlgk9yF840fnDeBExEYMyMVibh8gFZeN7HgPsfDSEqcGWm9T8pec/Fi1aCDLPPbsMlTiF7 7t04R X-Gm-Gg: AZuq6aLWXPCdWS3Fa6/dzHMjvtZqWtdjaQmFDrzJoRYGSXaqKry5Z1QlmNO0qsNbvuJ DP+x8bbsx5/KBATusoySpV7WR0YCywkm1iyhZaZ2hJn/US4Yu87KdneHWcCM6amXINfEObQGwaK tAig9V7EcSshFjYEJapn49fw5UtEWiWXZJDFbmZkDEXKNYZcap/jaUW3CAUqebILpJqZ5q0v6EP 4Pqqkg+v4vgMhoiEg/u0uHEIyoPoeyq9MbsdmCZmdv68P+awyUuoPiL7WkTSRYVeTFYM7aona5l XTYcjf39ux425WvAl0SDU2m45dHTWGE1SuR54u8Jit+hg3r9WH9h4lST+0pfUSmV0OsqbG5KPKt fddAECxF2GRENW2sWjd1SA90/wwsiakQhB+/KdC6wekb5PeHVLK0VBG8uNCSxDwXUW9xLVwv2lZ KwUC1umZ9q17mkinphzLSxESzzwrhyk21WUG3j4DecJbOabX1arr7uYBDFpfzFMcm7y4lmx4Eja 7CvGf9jlFhxYf7AQ1sqgRdvgBSl6sLzD+4EQ3/8IA== X-Received: by 2002:a05:600c:8b2f:b0:46f:c55a:5a8d with SMTP id 5b1f17b1804b1-483739ff865mr299370645e9.4.1771497251352; Thu, 19 Feb 2026 02:34:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/32] target/arm/tcg: Allow SVE RAX1 in SME2p1 streaming mode Date: Thu, 19 Feb 2026 10:33:37 +0000 Message-ID: <20260219103405.3793357-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497294500154100 Content-Type: text/plain; charset="utf-8" The SVE RAX1 instruction is permitted in SME streaming mode starting from SME2p1. We forgot to allow this relaxation when we implemented SME2p1. Cc: qemu-stable@nongnu.org Fixes: 7b1613a1020d2 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260202133353.2231685-5-peter.maydell@linaro.org --- target/arm/tcg/translate-sve.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 81f487152c..e853b4dd0a 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -7803,8 +7803,17 @@ TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gve= c_ool_arg_zzz, TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz, gen_helper_crypto_sm4ekey, a, 0) =20 -TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, - gen_gvec_rax1, a) +static bool trans_RAX1(DisasContext *s, arg_RAX1 *a) +{ + if (!dc_isar_feature(aa64_sve2_sha3, s)) { + return false; + } + if (!dc_isar_feature(aa64_sme2p1, s)) { + /* SME2p1 adds this as valid in streaming SVE mode */ + s->is_nonstreaming =3D true; + } + return gen_gvec_fn_arg_zzz(s, gen_gvec_rax1, a); +} =20 TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) --=20 2.43.0 From nobody Sun Apr 12 04:23:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497358; cv=none; d=zohomail.com; s=zohoarc; b=KubdqEDb/IscPrJdB6tOj9Srvbf8/QU8x6LwP3nJQTJDk4rF8K+N7D3Eo8JrgSeHh7G/Vw5byiW+SXIJj7ic6qzXPmWowyKwTkdT1jxgtR5R00ASb/GNuXXBdTqnHaE465rA0qeG5MtZ+szrqJqU7KYHTfTJ/N4EIO0WmXZZ/KE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497358; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ymWsJOl3EYWNePVYcoHaSpgh8B6NORXwc2lcKaczgL4=; b=aNg6NZ4MzJjt+pyc2mUQ1oPWMHA61hmqULh5Z9dm+wvu2Du94gXD9Dfv0AGUn3rdlqMz0e2gcyf4nsjfizspzPl7X6oiPEqAkv+ndqDmP2EjFqJzjdHBOhIqSzJbOCNE9VTDTtvX3P/uE5BgrEcj28KsdYD2VO1+yL6LS9ZfE14= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497358180325.69207445199777; Thu, 19 Feb 2026 02:35:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mc-0007Ci-Jk; Thu, 19 Feb 2026 05:34:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MT-00075e-Io for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:22 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MM-00062y-GQ for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:17 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4837f27cf2dso6969955e9.2 for ; Thu, 19 Feb 2026 02:34:13 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497252; x=1772102052; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ymWsJOl3EYWNePVYcoHaSpgh8B6NORXwc2lcKaczgL4=; b=dXu0AxhBlF2UB3Vkx22FKgAZvN8g92FEu2IUXA+Vx0Izv1jpnYBZTF6ScjnbgBA5EN S5KSE4x3K1XwWo3kgpE0+AQX3E9e7/Sz/d3EHpjWBlIl2LPw4yAcFFeDWhq2NmLHA55x 1G0vhUT0k0WES6MBYcPOTVJj7O3xuKWty1v/FigKp/I7EdKualehYjoDFKVut56Wa8N2 TvK+3S9cPur79IViq/FzWrzKqExoqk2AWXQYzbHYGyCTkitKFHhbh4ietQ0KWNzbhSxD rQcrSzSgR2eKy47WpVjJJ/iGyJi0Gqn9c3E4ga/9FWFHqqdyoXy9gtjSlr9MDXgyQqRM gH5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497252; x=1772102052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ymWsJOl3EYWNePVYcoHaSpgh8B6NORXwc2lcKaczgL4=; b=MD/EKtkPnimeBVaqlEgW2CGhK3nkMRq10fHjPoIb1X7pgT+VHVe9NCSd8JTz2zn4lA hC+BRm/MaKlmJytOYXLnSqQDk4wUzmjetleQo0/reVfHJEGMCf65OMzPpvG+JspaNcsk icx5Re+ZMgqPHNBs8J5krtfwEDo3/SQhTG3nJM+8sNaNRwvrh67sC7hfX3Znzrq7QAUP mf4cko2JrlrMY7GuIKlU9IZ9Kr3mqC/X6Fu2skkEaNTLQYGecAZhfNptUC1aqU2yENmZ W/lyvDYhbTCJiy901mOHO5CQIo2tFfBuzK+emJB/5YGow53hy55LRTWyhFyB8b7v+rzt uR4Q== X-Gm-Message-State: AOJu0YzACWNwxyPFAsiXMIBdsmwPBHTBcfftb8hsX2bJYj0kpDYk5POb TQQpmVwwFW0ZxflaFoX3QkzjIGHUupFY2Hp6PPXXe73b+7WffDL81i2KM6p/zZf40SOSZ6X8T1Y H8nG0 X-Gm-Gg: AZuq6aKkdwdshrOejkQeiMT0VrHbO2gQYPq4TshT4SDM48ZY1TDDgpUE2pXcT7NJW2w IS3UjpfMxjjqwL7mdsN8ZDYyQTNsRa7GxzajwyBVP4dTURJnpKor3p2MKmrvVCU0DypZWtJG+Ew P4LEwN/6e2MsN31HK3x+rEgfD1kglCRYHeGCQYk0GAaD2wArsOCRoJY7nHvkO/QHUpE56GEZCGf C0KaMwmCxnSYcOm1Vc9cOXKIlfZX4fumG8m6Qqgnlxl8qoxsTZvq45gfrKIiXaZ7WGUDCR5YnBq 87/I2kzA21cF7Hkzr8tMeElIHNWJhyMj8fNmd30VvnEy/pcrWP7xaQR0LtEmGlXpQMFtKw+8laq zdIaGMdAJ9g2JrOVCXNznvGrHDCCbq3FZvOUbPzp3TUhvGW6CJgUMay3EVa6K1H5HSrz789lJTu VCgz7rW179MzGD9yLtdRPjrtOVxNcmMadY702T+f8t1WQhcHHml2HadtEBSCjkgaW9oPNOjzHgD 8d35Xuah2+pZBkuGLDaR/hm96v5uyM= X-Received: by 2002:a05:600c:6912:b0:483:709e:f22d with SMTP id 5b1f17b1804b1-4837108fc46mr350480895e9.27.1771497252205; Thu, 19 Feb 2026 02:34:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/32] target/arm: Don't let 'sme=on' downgrade SME Date: Thu, 19 Feb 2026 10:33:38 +0000 Message-ID: <20260219103405.3793357-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497359393154100 Content-Type: text/plain; charset="utf-8" In our handling of the boolean 'sme' CPU property, we write this 0/1 value directly to ID_AA64PFR1_EL1.SME. This worked when the only valid values in that field were 0 (for no SME) and 1 (for SME1). However, with the addition of SME2 the SME field can now also read 2. This means that "-cpu max,sme=3Don" will result in an inconsistent set of ID registers, where ID_AA64PFR1_EL1.SME claims SME1 but ID_AA64SMFR0_EL1.SMEver claims SME2p1. This isn't a valid thing to report, and confuses Linux into reporting SME2 to userspace but not actually enabling userspace access for it. Fix this bug by having arm_cpu_sme_finalize() fix up the ID_AA64PFR1_EL1.SME field to match ID_AA64SMFR0.SMEver. This means the "sme" property's semantics are "off" for "no SME" and "on" for "enable at whatever the default SME version this CPU provides is". Update the documentation to clarify what 'sve=3Don' and 'sme=3Don' do. (We don't have the equivalent bug for 'sve=3Don' because ID_AA64PFR0_EL1.SVE only has 0 and 1 as valid values, but the semantics of the property are the same.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Manos Pitsidianakis Message-id: 20260202133353.2231685-6-peter.maydell@linaro.org --- docs/system/arm/cpu-features.rst | 10 ++++++++++ target/arm/cpu64.c | 15 +++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 37d5dfd15b..024119449c 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -318,6 +318,11 @@ SVE CPU Property Parsing Semantics provided an error will be generated. To avoid this error, one must enable at least one vector length prior to enabling SVE. =20 + 10) Enabling SVE (with ``sve=3Don`` or by default) enables all the SVE + sub-features that the CPU supports (for example, it may also + enable SVE2). There are not generally any lower-level controls + for disabling specific SVE sub-features. + SVE CPU Property Examples ------------------------- =20 @@ -430,6 +435,11 @@ and all vector lengths must be powers of 2. The maxim= um vector length supported by qemu is 2048 bits. Otherwise, there are no additional constraints on the set of vector lengths supported by SME. =20 +As with SVE, ``sme=3Don`` enables all the SME sub-features the CPU +supports (for example, it may also enable SME2), and there are +no lower-level controls for fine-grained disabling of specific +SME sub-features. + SME User-mode Default Vector Length Property -------------------------------------------- =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5d7c6b7fbb..4d316f5a71 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -366,6 +366,16 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) =20 cpu->sme_vq.map =3D vq_map; cpu->sme_max_vq =3D 32 - clz32(vq_map); + + /* + * The "sme" property setter writes a bool value into ID_AA64PFR1_EL1.= SME + * (and at this point we know it's not 0). Correct that value to report + * the same SME version as ID_AA64SMFR0_EL1.SMEver. + */ + if (FIELD_EX64_IDREG(&cpu->isar, ID_AA64SMFR0, SMEVER) !=3D 0) { + /* SME2 or better */ + FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, 2); + } } =20 static bool cpu_arm_get_sme(Object *obj, Error **errp) @@ -378,6 +388,11 @@ static void cpu_arm_set_sme(Object *obj, bool value, E= rror **errp) { ARMCPU *cpu =3D ARM_CPU(obj); =20 + /* + * For now, write 0 for "off" and 1 for "on" into the PFR1 field. + * We will correct this value to report the right SME + * level (SME vs SME2) in arm_cpu_sme_finalize() later. + */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, value); } =20 --=20 2.43.0 From nobody Sun Apr 12 04:23:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497511; cv=none; d=zohomail.com; s=zohoarc; b=dhIpl8G+T2THE5QcsY/t+J5SpOtHxSwwEJUcSAA9VoMf0TuvtpkBhTSek8Y/Dmg9NZ3yCmtdjS6DWOPi3xCB5+juovo7/nt35PM3sO3cUqUdNdIPwaJKXol3QejRwekrIR/QiuCQZk9/C0qlqzHW6f/vjN26BFj0gmYviuXZX4k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497511; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=jonBmBAd2vKXepXDKOxHMTPQMo4nlAkRTz3mBiiL0xA=; b=hidFbrf1OY+6MbJVvlj/7gl+uLX5ssh3RDkQIX2NJ58VPmcRoEzZpUC9EmNAptgBhMkGy5ezi0GbPeY34vnNomeEM1Y/zEQQ23tzHKLoIvMDpCOmKpZALyQNkjZw7Lz1mOmLcVFa2j9VQVd+3ZcGBDQ813vYRF+eqMHHBNEDJMc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497511209890.6218327488252; Thu, 19 Feb 2026 02:38:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mi-0007Kh-Va; Thu, 19 Feb 2026 05:34:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MT-00075g-Rn for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:22 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MO-00063C-LQ for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:18 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-48371bb515eso10524765e9.1 for ; Thu, 19 Feb 2026 02:34:14 -0800 (PST) Received: from lanath.. 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This hits the "assert(sm)" at the bettom of the function in an SME-only CPU where sve_vq.map is zero. Add code to handle the "SME-only CPU not in streaming mode" case: we report an effective VL of 128 bits, which is what the architecture rule R_KXKNK says should be used when SVE instructions are disabled or trapped but floating point instructions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Message-id: 20260202133353.2231685-7-peter.maydell@linaro.org --- target/arm/helper.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 373f0ebcb3..ebf185000b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4775,7 +4775,7 @@ int sme_exception_el(CPUARMState *env, int el) } =20 /* - * Given that SVE is enabled, return the vector length for EL. + * Given that SVE or SME is enabled, return the vector length for EL. */ uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm) { @@ -4787,6 +4787,12 @@ uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el= , bool sm) if (sm) { cr =3D env->vfp.smcr_el; map =3D cpu->sme_vq.map; + } else if (map =3D=3D 0) { + /* + * SME-only CPU not in streaming mode: effective VL + * is 128 bits, per R_KXKNK. + */ + return 0; } =20 if (el <=3D 1 && !el_is_in_host(env, el)) { --=20 2.43.0 From nobody Sun Apr 12 04:23:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497362; cv=none; d=zohomail.com; s=zohoarc; b=IZ0nZpwrGB7NkdBMa7Et3kxmuSTmrdFqaDnO10Xlhl7y/HHcrOXykEQ5Z/n3VglRcPhCj304YaoLYy62jl2v7DK3/SoG7xKIbbivGA5RcuYb+etxSSpj0yryrf6DXja0eScZAj+9GwlCmPnBngQmAeZQv1fTZJsZ5N0j7loBlm8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497362; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=OQfEbThu7oMSWLhYHhXd3iUGX21b3ELkTS9VtOATfc8=; b=L838HpHgbWKJCeMn6OdQ7IuXVNqAW/YUotUHfYBS6KiblhHK0JEG5nbgthie8dX/qm5KYJTE9OJaMYHwC9H/APtS4Knw9jMDbwd7odN8OTiIi+vM3cunHOlMrl7o9+KH6BKZ9JCNKvOXpdnTrxgYa4UtP+pYWc2vfyqTGepTsgk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497361783232.45996248189067; Thu, 19 Feb 2026 02:36:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mg-0007IT-8S; Thu, 19 Feb 2026 05:34:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MU-00075p-DM for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:23 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MO-00063a-M9 for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:19 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4806bf39419so13207995e9.1 for ; Thu, 19 Feb 2026 02:34:15 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497254; x=1772102054; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OQfEbThu7oMSWLhYHhXd3iUGX21b3ELkTS9VtOATfc8=; b=XQNwpja6+XjH6Oz2fqeR4ftkIp1TuEQD02bS5G6O9F6F/KR3iFsO0VR4/jGUAyDOm8 CHhGLQWkqy1cFU6IXoRILwFvj7010yYjVSqNTI0UZbZZv10oFwKNWVBw8z1RVrJmrUlt tOaJEbVVc8NiHtBA97Kpvh6UZZ+GeBAZRFNWnbFX0VYnIwmSaa6OZ0l2Guo2vCp09J6Z l317XIqKyAWVyPSI/i1kXfN5/QVPpvVvB6pjpMfVZ876lG/yBZuSo8kEvgw3J1wKUgqx AlmBKUxYi1jofTRSLee65dNX62vCEGui5emZcH5Z9COxepDgeeZCUjt/fbMo6zn3iNyZ 2rFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497254; x=1772102054; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=OQfEbThu7oMSWLhYHhXd3iUGX21b3ELkTS9VtOATfc8=; b=vrrFCkLLRDhnkTgFUY5qGH0H9PFiyfo9/aMLe2t2H+8okMIZ8ambN7EWURbffuDmm+ nRMK/P2qzvyvMWUyOfXgKF2dWewj1nQjFd1ngJZYqjqsD15qS2jkTiwTl5i8M0JEj4Ei phXiHwEHQFOf0nXoJWxCnab4Ovw0V2I03LIDE7bF0RG8oJjApaF9TiMGQB6cdN7BM/nZ NbUbro0emxrNrHFQxYlxR/9FJxNArdCOZc4fDTV4YIqjAtiIRDgvSfujvet1P5m9GDQF AjAuMkS6YIUxitdBIJMaj8SsqlJEV4NVWclBxSZktPMwbfgGo9t0Y9Q0O4CmJy709/M2 hKhg== X-Gm-Message-State: AOJu0YyUKzvLZCW9b5HO3/jWRFMm7Sc58PilUYcEoVhIybeKq5P0qLi1 rCIhyjbESZrpBE5O2Z9YE5OwKZAC5a9iR6TcH7Agko8ctSXmX+atllfrfV6ZTcnVoHuxtMt1wCY HijUU X-Gm-Gg: AZuq6aLkX5dms66ShSTy8XLwW5O5czNA3SvlV9sZg8YlW4BtT1gqKo74551SWkAEpXn ZMk3zD2LY0A70BIKG18ye1HW3T9kajlHGvAEwCa7DEuBOMG68ez+KfLtQerRc8R/poIYvtNqALU amBkL+/n6SmxsnpABpAu1N65jIeY6kANiNrywIs1edHGAlg+DLaJKCDmydrOgYiNdiqZBpmWWDd mq030c1HHoS8gEL6Eiqnq/pUedkDu8DvxIYv/l9dci23R4GHzz6X7CyMnUAZhUZ6pb1JoFDPJiy ZTcC1l76vrB/0BzwRcjt8h2RhEQrBlageDCFIn9oOvyjHjGbvrY+YzCXdgrbWmXVZSsvpWJKWX5 MKBrmOUpbT5BzNoZlHtECq4h8W6BLoCD3HnFI+JiO6Hpm0I6y8wfZgVAalz+0xWflpwHBJc/voW /l48ZNLtMJ3IEwU84Ku1fp5E2VA6NMnCqKkJ6rN3vu1Tz8v/7RD9VbBzqemNWFpXrgXxJ6T6ls5 ax9ZrLhQpKUQ5/mkhAyGlOC/DJR9c4= X-Received: by 2002:a05:600c:4616:b0:477:a71c:d200 with SMTP id 5b1f17b1804b1-483a00a51b6mr12544465e9.11.1771497253932; Thu, 19 Feb 2026 02:34:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/32] target/arm: Handle SME-without-SVE on change of EL Date: Thu, 19 Feb 2026 10:33:40 +0000 Message-ID: <20260219103405.3793357-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497363384154100 aarch64_sve_change_el() currently assumes that SME implies SVE, and will return without doing anything if SVE is not implemented, skipping a possible requirement to change the vector register state because the SME vector length has changed. Update it to handle SME also. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260202133353.2231685-8-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ebf185000b..e12b2455d3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10139,8 +10139,8 @@ void aarch64_sve_change_el(CPUARMState *env, int ol= d_el, int old_len, new_len; bool old_a64, new_a64, sm; =20 - /* Nothing to do if no SVE. */ - if (!cpu_isar_feature(aa64_sve, cpu)) { + /* Nothing to do if no SVE or SME. */ + if (!cpu_isar_feature(aa64_sve, cpu) && !cpu_isar_feature(aa64_sme, cp= u)) { return; } =20 --=20 2.43.0 From nobody Sun Apr 12 04:23:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497497; cv=none; d=zohomail.com; s=zohoarc; b=CYLjgAduSL6MBSVpsiCRpdq3U5yTEYC0C699ZvxylW82aUxzSb2/5/xHxnhMOB2ijYKAeXzn69Tb1fd6D7ugw6rN5WWIH+NoviIBaTCNHrlFrDRS7m3zd2Ywhm1M84zApKnNz5eYdAUuogwG9a7CiXiu2asTuHanKzdYtKJ3rwY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497497; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=MsmPUrRagvo2cMfuuEF3Q3H/QYPRKo/Q2Vmbz/5Q72Y=; b=FjbRPbV7bOZyjbGxIySmlIijWTmbxFr+NpyT5z9wupvw/1Z0ylvdnEiKLQaJWFHZILrTtryL+NYij+hM/eZhpAqdZ7xvdPXKEKUHvWNfKcbqODq+JvdMk/xb1byDAyuBWSiFbCd3PCRV+5y+4IaAsJ76EhVscrPWr+R/6gE8dUw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497497114225.19772048685206; Thu, 19 Feb 2026 02:38:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mf-0007Hc-Pj; Thu, 19 Feb 2026 05:34:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MU-00075l-4L for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:22 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MO-00063n-Kr for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:18 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4836f4cbe0bso6185865e9.3 for ; Thu, 19 Feb 2026 02:34:15 -0800 (PST) Received: from lanath.. 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We correctly handle this when the emulated CPU has both FEAT_SVE and FEAT_SME, because sve_access_check() includes the logic for this, matching the pseudocode CheckSVEEnabled(). However if the emulated CPU only implement FEAT_SME, it will fail the initial dc_isar_feature(aa64_sve, s) feature check, because this doesn't match the check in the per-instruction decode pseudocode, which is typically: !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) Add a new aa64_sme_or_sve feature function that we can use to update the relevant uses of aa64_sve, and similarly aa64_sme_or_sve2 for where we need to check FEAT_SVE2 || FEAT_SME. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260202133353.2231685-9-peter.maydell@linaro.org --- target/arm/cpu-features.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 49c50e850a..6935ef2f78 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1522,6 +1522,16 @@ static inline bool isar_feature_aa64_sme2p1(const AR= MISARegisters *id) /* * Combinations of feature tests, for ease of use with TRANS_FEAT. */ +static inline bool isar_feature_aa64_sme_or_sve(const ARMISARegisters *id) +{ + return isar_feature_aa64_sme(id) || isar_feature_aa64_sve(id); +} + +static inline bool isar_feature_aa64_sme_or_sve2(const ARMISARegisters *id) +{ + return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2(id); +} + static inline bool isar_feature_aa64_sme_or_sve2p1(const ARMISARegisters *= id) { return isar_feature_aa64_sme(id) || isar_feature_aa64_sve2p1(id); --=20 2.43.0 From nobody Sun Apr 12 04:23:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497380; cv=none; d=zohomail.com; s=zohoarc; b=dJWNbpFhEGtxKu4DUxO9XUO4tTCMwcHvJMDFnFeN1Y97iO2LQGl5FTMiLwXH2xAWmxQRNu1kVuF0LGxjFubGbX6wwKeIvRYA0gZDXWakfUNKKJaeVHB/LYoWQHhLPaQEkBAOBenz45Uxl615ZU/E2zozHs6HMlfA3lv0xFs5nZs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497380; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=L1ctnhdXePTfsqLLCfBe5tFGjQ3Y/lUw+bu7pneikjI=; b=UJDQrPY/y9/y+sPvKywcvGkNNj6d37L44sE7KxiTwRf0EVHv6pGpXnPVA2hR5EHqmlN8LH2Ghuz9K847BGqn9L+VUrCi8scI1zN4Cv+jAlwZD5mOsA6n7b38Y4PpOuWCVid0MT97YYqdcEpIzWbQteFEJHJdK+SP5ReHqgxtVZ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177149738027478.93760992480668; Thu, 19 Feb 2026 02:36:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mk-0007Mb-Jn; Thu, 19 Feb 2026 05:34:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MX-00078U-7J for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:25 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MS-000644-RX for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:23 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4836f4cbe0bso6185985e9.3 for ; Thu, 19 Feb 2026 02:34:17 -0800 (PST) Received: from lanath.. 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This is currently a redundant check because we only invoke this function via the macro invocation TRANS_FEAT(..., aa64_sve2, do_trans_pmull, ...) and it's actively wrong for an SME-only CPU, because these insns are also available via SME. Remove the unnecessary logic. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260202133353.2231685-10-peter.maydell@linaro.org --- target/arm/tcg/translate-sve.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index e853b4dd0a..fe59126d2b 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -6782,8 +6782,6 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_e= sz *a, bool sel) return false; } s->is_nonstreaming =3D true; - } else if (!dc_isar_feature(aa64_sve, s)) { - return false; } return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); } --=20 2.43.0 From nobody Sun Apr 12 04:23:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497311; cv=none; d=zohomail.com; s=zohoarc; b=WAV3q6jOgkQ0zUBudhanSrwvSvCDtywH3EiRJo+T+rP4NIqjYFgQn1MFh0PdTcGpMHEaLAQdsXruVS0h35N6LpUlC7YRdt0Z4gjIuqzfFObDtztev2E/SWyfCYrqQFmdET5vFV2USWWatqUWcw7HoSCki20ejtGCVmmASJt7vH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497311; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=QXOLjZ4U5U2q3Qg6rXDRueepoZ5qW603viTnzSgRj7s=; b=TeOMAHmcNtxeAEutJ55D4bFmnNW6w0VLV+T2Y9Lt+izofrOy5Mt57k4Rw5oBUpy+u5BaObVr1Feep1dEiq5CC5KGKFlJwuZJFHS+MPR1ypxCjqR3Dp49eMebY47LZevWNi84SKfAMoqdl+WYb2Gifx7yiq3kv+2QMbbGYfS95Zo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497311915960.0005679636904; Thu, 19 Feb 2026 02:35:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mk-0007Mg-Tv; Thu, 19 Feb 2026 05:34:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MZ-0007BF-G2 for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:27 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MT-00064c-C1 for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:27 -0500 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4836f4cbe0bso6186185e9.3 for ; Thu, 19 Feb 2026 02:34:18 -0800 (PST) Received: from lanath.. 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Currently we largely check only for features aa64_sve or aa64_sve2. This happens to work because we forbid creation of a CPU with SME but not SVE. To allow users to create SME-only CPUs we need to update the conditions to use the "or SME" versions of the feature tests instead. This commit was created by going through translate-sve.c from top to bottom looking for aa64_sve feature tests and cross checking those against the instruction descriptions in the Arm ARM, which will say "(FEAT_SVE || FEAT_SME)" for instructions that are provided for both features, and "(FEAT_SME)" for the rarer instructions that are SME only. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260202133353.2231685-11-peter.maydell@linaro.org --- target/arm/tcg/translate-sve.c | 854 ++++++++++++++++----------------- 1 file changed, 427 insertions(+), 427 deletions(-) diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index fe59126d2b..44eda7b07d 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -570,14 +570,14 @@ static bool trans_INVALID(DisasContext *s, arg_INVALI= D *a) *** SVE Logical - Unpredicated Group */ =20 -TRANS_FEAT(AND_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and, a) -TRANS_FEAT(ORR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_or, a) -TRANS_FEAT(EOR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_xor, a) -TRANS_FEAT(BIC_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_andc, a) +TRANS_FEAT(AND_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and= , a) +TRANS_FEAT(ORR_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_or,= a) +TRANS_FEAT(EOR_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_xor= , a) +TRANS_FEAT(BIC_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and= c, a) =20 static bool trans_XAR(DisasContext *s, arg_rrri_esz *a) { - if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) { + if (a->esz < 0 || !dc_isar_feature(aa64_sme_or_sve2, s)) { return false; } if (sve_access_check(s)) { @@ -589,8 +589,8 @@ static bool trans_XAR(DisasContext *s, arg_rrri_esz *a) return true; } =20 -TRANS_FEAT(EOR3, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_gvec_eor3, a) -TRANS_FEAT(BCAX, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_gvec_bcax, a) +TRANS_FEAT(EOR3, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_gvec_eor3, a) +TRANS_FEAT(BCAX, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_gvec_bcax, a) =20 static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m, uint32_t a, uint32_t oprsz, uint32_t maxsz) @@ -599,7 +599,7 @@ static void gen_bsl(unsigned vece, uint32_t d, uint32_t= n, uint32_t m, tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz); } =20 -TRANS_FEAT(BSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl, a) +TRANS_FEAT(BSL, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_bsl, a) =20 static void gen_bsl1n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) { @@ -628,7 +628,7 @@ static void gen_bsl1n(unsigned vece, uint32_t d, uint32= _t n, uint32_t m, tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } =20 -TRANS_FEAT(BSL1N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl1n, a) +TRANS_FEAT(BSL1N, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_bsl1n, a) =20 static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) { @@ -666,7 +666,7 @@ static void gen_bsl2n(unsigned vece, uint32_t d, uint32= _t n, uint32_t m, tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } =20 -TRANS_FEAT(BSL2N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl2n, a) +TRANS_FEAT(BSL2N, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_bsl2n, a) =20 static void gen_nbsl_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k) { @@ -695,18 +695,18 @@ static void gen_nbsl(unsigned vece, uint32_t d, uint3= 2_t n, uint32_t m, tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); } =20 -TRANS_FEAT(NBSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_nbsl, a) +TRANS_FEAT(NBSL, aa64_sme_or_sve2, gen_gvec_fn_arg_zzzz, gen_nbsl, a) =20 /* *** SVE Integer Arithmetic - Unpredicated Group */ =20 -TRANS_FEAT(ADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_add, a) -TRANS_FEAT(SUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sub, a) -TRANS_FEAT(SQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ssadd, a) -TRANS_FEAT(SQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sssub, a) -TRANS_FEAT(UQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_usadd, a) -TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a) +TRANS_FEAT(ADD_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_add= , a) +TRANS_FEAT(SUB_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sub= , a) +TRANS_FEAT(SQADD_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_s= sadd, a) +TRANS_FEAT(SQSUB_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_s= ssub, a) +TRANS_FEAT(UQADD_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_u= sadd, a) +TRANS_FEAT(UQSUB_zzz, aa64_sme_or_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_u= ssub, a) =20 /* *** SVE Integer Arithmetic - Binary Predicated Group @@ -732,40 +732,40 @@ static bool do_sel_z(DisasContext *s, int rd, int rn,= int rm, int pg, int esz) TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpzz, \ name##_zpzz_fns[a->esz], a, 0) =20 -DO_ZPZZ(AND_zpzz, aa64_sve, sve_and) -DO_ZPZZ(EOR_zpzz, aa64_sve, sve_eor) -DO_ZPZZ(ORR_zpzz, aa64_sve, sve_orr) -DO_ZPZZ(BIC_zpzz, aa64_sve, sve_bic) +DO_ZPZZ(AND_zpzz, aa64_sme_or_sve, sve_and) +DO_ZPZZ(EOR_zpzz, aa64_sme_or_sve, sve_eor) +DO_ZPZZ(ORR_zpzz, aa64_sme_or_sve, sve_orr) +DO_ZPZZ(BIC_zpzz, aa64_sme_or_sve, sve_bic) =20 -DO_ZPZZ(ADD_zpzz, aa64_sve, sve_add) -DO_ZPZZ(SUB_zpzz, aa64_sve, sve_sub) +DO_ZPZZ(ADD_zpzz, aa64_sme_or_sve, sve_add) +DO_ZPZZ(SUB_zpzz, aa64_sme_or_sve, sve_sub) =20 -DO_ZPZZ(SMAX_zpzz, aa64_sve, sve_smax) -DO_ZPZZ(UMAX_zpzz, aa64_sve, sve_umax) -DO_ZPZZ(SMIN_zpzz, aa64_sve, sve_smin) -DO_ZPZZ(UMIN_zpzz, aa64_sve, sve_umin) -DO_ZPZZ(SABD_zpzz, aa64_sve, sve_sabd) -DO_ZPZZ(UABD_zpzz, aa64_sve, sve_uabd) +DO_ZPZZ(SMAX_zpzz, aa64_sme_or_sve, sve_smax) +DO_ZPZZ(UMAX_zpzz, aa64_sme_or_sve, sve_umax) +DO_ZPZZ(SMIN_zpzz, aa64_sme_or_sve, sve_smin) +DO_ZPZZ(UMIN_zpzz, aa64_sme_or_sve, sve_umin) +DO_ZPZZ(SABD_zpzz, aa64_sme_or_sve, sve_sabd) +DO_ZPZZ(UABD_zpzz, aa64_sme_or_sve, sve_uabd) =20 -DO_ZPZZ(MUL_zpzz, aa64_sve, sve_mul) -DO_ZPZZ(SMULH_zpzz, aa64_sve, sve_smulh) -DO_ZPZZ(UMULH_zpzz, aa64_sve, sve_umulh) +DO_ZPZZ(MUL_zpzz, aa64_sme_or_sve, sve_mul) +DO_ZPZZ(SMULH_zpzz, aa64_sme_or_sve, sve_smulh) +DO_ZPZZ(UMULH_zpzz, aa64_sme_or_sve, sve_umulh) =20 -DO_ZPZZ(ASR_zpzz, aa64_sve, sve_asr) -DO_ZPZZ(LSR_zpzz, aa64_sve, sve_lsr) -DO_ZPZZ(LSL_zpzz, aa64_sve, sve_lsl) +DO_ZPZZ(ASR_zpzz, aa64_sme_or_sve, sve_asr) +DO_ZPZZ(LSR_zpzz, aa64_sme_or_sve, sve_lsr) +DO_ZPZZ(LSL_zpzz, aa64_sme_or_sve, sve_lsl) =20 static gen_helper_gvec_4 * const sdiv_fns[4] =3D { NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d }; -TRANS_FEAT(SDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, sdiv_fns[a->esz], a= , 0) +TRANS_FEAT(SDIV_zpzz, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz, sdiv_fns[a->= esz], a, 0) =20 static gen_helper_gvec_4 * const udiv_fns[4] =3D { NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d }; -TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a= , 0) +TRANS_FEAT(UDIV_zpzz, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->= esz], a, 0) =20 -TRANS_FEAT(SEL_zpzz, aa64_sve, do_sel_z, a->rd, a->rn, a->rm, a->pg, a->es= z) +TRANS_FEAT(SEL_zpzz, aa64_sme_or_sve, do_sel_z, a->rd, a->rn, a->rm, a->pg= , a->esz) =20 /* *** SVE Integer Arithmetic - Unary Predicated Group @@ -778,14 +778,14 @@ TRANS_FEAT(SEL_zpzz, aa64_sve, do_sel_z, a->rd, a->rn= , a->rm, a->pg, a->esz) }; \ TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0) =20 -DO_ZPZ(CLS, aa64_sve, sve_cls) -DO_ZPZ(CLZ, aa64_sve, sve_clz) -DO_ZPZ(CNT_zpz, aa64_sve, sve_cnt_zpz) -DO_ZPZ(CNOT, aa64_sve, sve_cnot) -DO_ZPZ(NOT_zpz, aa64_sve, sve_not_zpz) -DO_ZPZ(ABS, aa64_sve, sve_abs) -DO_ZPZ(NEG, aa64_sve, sve_neg) -DO_ZPZ(RBIT, aa64_sve, sve_rbit) +DO_ZPZ(CLS, aa64_sme_or_sve, sve_cls) +DO_ZPZ(CLZ, aa64_sme_or_sve, sve_clz) +DO_ZPZ(CNT_zpz, aa64_sme_or_sve, sve_cnt_zpz) +DO_ZPZ(CNOT, aa64_sme_or_sve, sve_cnot) +DO_ZPZ(NOT_zpz, aa64_sme_or_sve, sve_not_zpz) +DO_ZPZ(ABS, aa64_sme_or_sve, sve_abs) +DO_ZPZ(NEG, aa64_sme_or_sve, sve_neg) +DO_ZPZ(RBIT, aa64_sme_or_sve, sve_rbit) DO_ZPZ(ORQV, aa64_sme2p1_or_sve2p1, sve2p1_orqv) DO_ZPZ(EORQV, aa64_sme2p1_or_sve2p1, sve2p1_eorqv) DO_ZPZ(ANDQV, aa64_sme2p1_or_sve2p1, sve2p1_andqv) @@ -798,7 +798,7 @@ static gen_helper_gvec_3 * const fabs_ah_fns[4] =3D { NULL, gen_helper_sve_ah_fabs_h, gen_helper_sve_ah_fabs_s, gen_helper_sve_ah_fabs_d, }; -TRANS_FEAT(FABS, aa64_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(FABS, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, s->fpcr_ah ? fabs_ah_fns[a->esz] : fabs_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const fneg_fns[4] =3D { @@ -809,34 +809,34 @@ static gen_helper_gvec_3 * const fneg_ah_fns[4] =3D { NULL, gen_helper_sve_ah_fneg_h, gen_helper_sve_ah_fneg_s, gen_helper_sve_ah_fneg_d, }; -TRANS_FEAT(FNEG, aa64_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(FNEG, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, s->fpcr_ah ? fneg_ah_fns[a->esz] : fneg_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const sxtb_fns[4] =3D { NULL, gen_helper_sve_sxtb_h, gen_helper_sve_sxtb_s, gen_helper_sve_sxtb_d, }; -TRANS_FEAT(SXTB, aa64_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], a, 0) +TRANS_FEAT(SXTB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], = a, 0) =20 static gen_helper_gvec_3 * const uxtb_fns[4] =3D { NULL, gen_helper_sve_uxtb_h, gen_helper_sve_uxtb_s, gen_helper_sve_uxtb_d, }; -TRANS_FEAT(UXTB, aa64_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], a, 0) +TRANS_FEAT(UXTB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], = a, 0) =20 static gen_helper_gvec_3 * const sxth_fns[4] =3D { NULL, NULL, gen_helper_sve_sxth_s, gen_helper_sve_sxth_d }; -TRANS_FEAT(SXTH, aa64_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], a, 0) +TRANS_FEAT(SXTH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], = a, 0) =20 static gen_helper_gvec_3 * const uxth_fns[4] =3D { NULL, NULL, gen_helper_sve_uxth_s, gen_helper_sve_uxth_d }; -TRANS_FEAT(UXTH, aa64_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], a, 0) +TRANS_FEAT(UXTH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], = a, 0) =20 -TRANS_FEAT(SXTW, aa64_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(SXTW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_sxtw_d : NULL, a, 0) -TRANS_FEAT(UXTW, aa64_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(UXTW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_uxtw_d : NULL, a, 0) =20 static gen_helper_gvec_3 * const addqv_fns[4] =3D { @@ -912,7 +912,7 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ }; \ - TRANS_FEAT(NAME, aa64_sve, do_vpz_ool, a, name##_fns[a->esz]) + TRANS_FEAT(NAME, aa64_sme_or_sve, do_vpz_ool, a, name##_fns[a->esz]) =20 DO_VPZ(ORV, orv) DO_VPZ(ANDV, andv) @@ -928,7 +928,7 @@ static gen_helper_gvec_reduc * const saddv_fns[4] =3D { gen_helper_sve_saddv_b, gen_helper_sve_saddv_h, gen_helper_sve_saddv_s, NULL }; -TRANS_FEAT(SADDV, aa64_sve, do_vpz_ool, a, saddv_fns[a->esz]) +TRANS_FEAT(SADDV, aa64_sme_or_sve, do_vpz_ool, a, saddv_fns[a->esz]) =20 #undef DO_VPZ =20 @@ -980,59 +980,59 @@ static gen_helper_gvec_3 * const asr_zpzi_fns[4] =3D { gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h, gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d, }; -TRANS_FEAT(ASR_zpzi, aa64_sve, do_shift_zpzi, a, true, asr_zpzi_fns) +TRANS_FEAT(ASR_zpzi, aa64_sme_or_sve, do_shift_zpzi, a, true, asr_zpzi_fns) =20 static gen_helper_gvec_3 * const lsr_zpzi_fns[4] =3D { gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h, gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d, }; -TRANS_FEAT(LSR_zpzi, aa64_sve, do_shift_zpzi, a, false, lsr_zpzi_fns) +TRANS_FEAT(LSR_zpzi, aa64_sme_or_sve, do_shift_zpzi, a, false, lsr_zpzi_fn= s) =20 static gen_helper_gvec_3 * const lsl_zpzi_fns[4] =3D { gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h, gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d, }; -TRANS_FEAT(LSL_zpzi, aa64_sve, do_shift_zpzi, a, false, lsl_zpzi_fns) +TRANS_FEAT(LSL_zpzi, aa64_sme_or_sve, do_shift_zpzi, a, false, lsl_zpzi_fn= s) =20 static gen_helper_gvec_3 * const asrd_fns[4] =3D { gen_helper_sve_asrd_b, gen_helper_sve_asrd_h, gen_helper_sve_asrd_s, gen_helper_sve_asrd_d, }; -TRANS_FEAT(ASRD, aa64_sve, do_shift_zpzi, a, false, asrd_fns) +TRANS_FEAT(ASRD, aa64_sme_or_sve, do_shift_zpzi, a, false, asrd_fns) =20 static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] =3D { gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h, gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d, }; -TRANS_FEAT(SQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi, +TRANS_FEAT(SQSHL_zpzi, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzi, a->esz < 0 ? NULL : sqshl_zpzi_fns[a->esz], a) =20 static gen_helper_gvec_3 * const uqshl_zpzi_fns[4] =3D { gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h, gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d, }; -TRANS_FEAT(UQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi, +TRANS_FEAT(UQSHL_zpzi, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzi, a->esz < 0 ? NULL : uqshl_zpzi_fns[a->esz], a) =20 static gen_helper_gvec_3 * const srshr_fns[4] =3D { gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h, gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d, }; -TRANS_FEAT(SRSHR, aa64_sve2, gen_gvec_ool_arg_zpzi, +TRANS_FEAT(SRSHR, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzi, a->esz < 0 ? NULL : srshr_fns[a->esz], a) =20 static gen_helper_gvec_3 * const urshr_fns[4] =3D { gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h, gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d, }; -TRANS_FEAT(URSHR, aa64_sve2, gen_gvec_ool_arg_zpzi, +TRANS_FEAT(URSHR, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzi, a->esz < 0 ? NULL : urshr_fns[a->esz], a) =20 static gen_helper_gvec_3 * const sqshlu_fns[4] =3D { gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h, gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d, }; -TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi, +TRANS_FEAT(SQSHLU, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzi, a->esz < 0 ? NULL : sqshlu_fns[a->esz], a) =20 /* @@ -1044,7 +1044,7 @@ TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi, gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \ gen_helper_sve_##name##_zpzw_s, NULL \ }; \ - TRANS_FEAT(NAME##_zpzw, aa64_sve, gen_gvec_ool_arg_zpzz, \ + TRANS_FEAT(NAME##_zpzw, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz, = \ a->esz < 0 ? NULL : name##_zpzw_fns[a->esz], a, 0) =20 DO_ZPZW(ASR, asr) @@ -1084,16 +1084,16 @@ static bool do_shift_imm(DisasContext *s, arg_rri_e= sz *a, bool asr, return true; } =20 -TRANS_FEAT(ASR_zzi, aa64_sve, do_shift_imm, a, true, tcg_gen_gvec_sari) -TRANS_FEAT(LSR_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shri) -TRANS_FEAT(LSL_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shli) +TRANS_FEAT(ASR_zzi, aa64_sme_or_sve, do_shift_imm, a, true, tcg_gen_gvec_s= ari) +TRANS_FEAT(LSR_zzi, aa64_sme_or_sve, do_shift_imm, a, false, tcg_gen_gvec_= shri) +TRANS_FEAT(LSL_zzi, aa64_sme_or_sve, do_shift_imm, a, false, tcg_gen_gvec_= shli) =20 #define DO_ZZW(NAME, name) \ static gen_helper_gvec_3 * const name##_zzw_fns[4] =3D { = \ gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \ gen_helper_sve_##name##_zzw_s, NULL \ }; \ - TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_arg_zzz, \ + TRANS_FEAT(NAME, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, = \ name##_zzw_fns[a->esz], a, 0) =20 DO_ZZW(ASR_zzw, asr) @@ -1125,13 +1125,13 @@ static gen_helper_gvec_5 * const mla_fns[4] =3D { gen_helper_sve_mla_b, gen_helper_sve_mla_h, gen_helper_sve_mla_s, gen_helper_sve_mla_d, }; -TRANS_FEAT(MLA, aa64_sve, do_zpzzz_ool, a, mla_fns[a->esz]) +TRANS_FEAT(MLA, aa64_sme_or_sve, do_zpzzz_ool, a, mla_fns[a->esz]) =20 static gen_helper_gvec_5 * const mls_fns[4] =3D { gen_helper_sve_mls_b, gen_helper_sve_mls_h, gen_helper_sve_mls_s, gen_helper_sve_mls_d, }; -TRANS_FEAT(MLS, aa64_sve, do_zpzzz_ool, a, mls_fns[a->esz]) +TRANS_FEAT(MLS, aa64_sme_or_sve, do_zpzzz_ool, a, mls_fns[a->esz]) =20 /* *** SVE Index Generation Group @@ -1172,13 +1172,13 @@ static bool do_index(DisasContext *s, int esz, int = rd, return true; } =20 -TRANS_FEAT(INDEX_ii, aa64_sve, do_index, a->esz, a->rd, +TRANS_FEAT(INDEX_ii, aa64_sme_or_sve, do_index, a->esz, a->rd, tcg_constant_i64(a->imm1), tcg_constant_i64(a->imm2)) -TRANS_FEAT(INDEX_ir, aa64_sve, do_index, a->esz, a->rd, +TRANS_FEAT(INDEX_ir, aa64_sme_or_sve, do_index, a->esz, a->rd, tcg_constant_i64(a->imm), cpu_reg(s, a->rm)) -TRANS_FEAT(INDEX_ri, aa64_sve, do_index, a->esz, a->rd, +TRANS_FEAT(INDEX_ri, aa64_sme_or_sve, do_index, a->esz, a->rd, cpu_reg(s, a->rn), tcg_constant_i64(a->imm)) -TRANS_FEAT(INDEX_rr, aa64_sve, do_index, a->esz, a->rd, +TRANS_FEAT(INDEX_rr, aa64_sme_or_sve, do_index, a->esz, a->rd, cpu_reg(s, a->rn), cpu_reg(s, a->rm)) =20 /* @@ -1187,7 +1187,7 @@ TRANS_FEAT(INDEX_rr, aa64_sve, do_index, a->esz, a->r= d, =20 static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1213,7 +1213,7 @@ static bool trans_ADDSVL(DisasContext *s, arg_ADDSVL = *a) =20 static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1239,7 +1239,7 @@ static bool trans_ADDSPL(DisasContext *s, arg_ADDSPL = *a) =20 static bool trans_RDVL(DisasContext *s, arg_RDVL *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1370,7 +1370,7 @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!a->s) { @@ -1408,7 +1408,7 @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!a->s && a->pg =3D=3D a->rn) { @@ -1439,7 +1439,7 @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } /* Alias NOT (predicate) is EOR Pd.B, Pg/Z, Pn.B, Pg.B */ @@ -1451,7 +1451,7 @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_= s *a) =20 static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a) { - if (a->s || !dc_isar_feature(aa64_sve, s)) { + if (a->s || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1486,7 +1486,7 @@ static bool trans_ORR_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!a->s && a->pg =3D=3D a->rn && a->rn =3D=3D a->rm) { @@ -1517,7 +1517,7 @@ static bool trans_ORN_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } return do_pppp_flags(s, a, &op); @@ -1545,7 +1545,7 @@ static bool trans_NOR_pppp(DisasContext *s, arg_rprr_= s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } return do_pppp_flags(s, a, &op); @@ -1573,7 +1573,7 @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr= _s *a) .prefer_i64 =3D true, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } return do_pppp_flags(s, a, &op); @@ -1585,7 +1585,7 @@ static bool trans_NAND_pppp(DisasContext *s, arg_rprr= _s *a) =20 static bool trans_PTEST(DisasContext *s, arg_PTEST *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1723,7 +1723,7 @@ static bool do_predset(DisasContext *s, int esz, int = rd, int pat, bool setflag) return true; } =20 -TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s) +TRANS_FEAT(PTRUE, aa64_sme_or_sve, do_predset, a->esz, a->rd, a->pat, a->s) =20 static bool trans_PTRUE_cnt(DisasContext *s, arg_PTRUE_cnt *a) { @@ -1746,7 +1746,7 @@ TRANS_FEAT_NONSTREAMING(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false) =20 /* Note pat =3D=3D 32 is #unimp, to set no elements. */ -TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false) +TRANS_FEAT(PFALSE, aa64_sme_or_sve, do_predset, 0, a->rd, 32, false) =20 static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a) { @@ -1791,8 +1791,8 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_e= sz *a, return true; } =20 -TRANS_FEAT(PFIRST, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pfirst) -TRANS_FEAT(PNEXT, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pnext) +TRANS_FEAT(PFIRST, aa64_sme_or_sve, do_pfirst_pnext, a, gen_helper_sve_pfi= rst) +TRANS_FEAT(PNEXT, aa64_sme_or_sve, do_pfirst_pnext, a, gen_helper_sve_pnex= t) =20 /* *** SVE Element Count Group @@ -1946,7 +1946,7 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, =20 static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1959,7 +1959,7 @@ static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) =20 static bool trans_INCDEC_r(DisasContext *s, arg_incdec_cnt *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -1975,7 +1975,7 @@ static bool trans_INCDEC_r(DisasContext *s, arg_incde= c_cnt *a) =20 static bool trans_SINCDEC_r_32(DisasContext *s, arg_incdec_cnt *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!sve_access_check(s)) { @@ -2002,7 +2002,7 @@ static bool trans_SINCDEC_r_32(DisasContext *s, arg_i= ncdec_cnt *a) =20 static bool trans_SINCDEC_r_64(DisasContext *s, arg_incdec_cnt *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!sve_access_check(s)) { @@ -2022,7 +2022,7 @@ static bool trans_SINCDEC_r_64(DisasContext *s, arg_i= ncdec_cnt *a) =20 static bool trans_INCDEC_v(DisasContext *s, arg_incdec2_cnt *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } =20 @@ -2045,7 +2045,7 @@ static bool trans_INCDEC_v(DisasContext *s, arg_incde= c2_cnt *a) =20 static bool trans_SINCDEC_v(DisasContext *s, arg_incdec2_cnt *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } =20 @@ -2079,15 +2079,15 @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *= a, GVecGen2iFn *gvec_fn) return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm); } =20 -TRANS_FEAT(AND_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_andi) -TRANS_FEAT(ORR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_ori) -TRANS_FEAT(EOR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_xori) +TRANS_FEAT(AND_zzi, aa64_sme_or_sve, do_zz_dbm, a, tcg_gen_gvec_andi) +TRANS_FEAT(ORR_zzi, aa64_sme_or_sve, do_zz_dbm, a, tcg_gen_gvec_ori) +TRANS_FEAT(EOR_zzi, aa64_sme_or_sve, do_zz_dbm, a, tcg_gen_gvec_xori) =20 static bool trans_DUPM(DisasContext *s, arg_DUPM *a) { uint64_t imm; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!logic_imm_decode_wmask(&imm, extract32(a->dbm, 12, 1), @@ -2131,7 +2131,7 @@ static void do_cpy_m(DisasContext *s, int esz, int rd= , int rn, int pg, =20 static bool trans_FCPY(DisasContext *s, arg_FCPY *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2144,7 +2144,7 @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a) =20 static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2160,7 +2160,7 @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_= i *a) gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d, }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2207,8 +2207,8 @@ static bool do_EXT(DisasContext *s, int rd, int rn, i= nt rm, int imm) return true; } =20 -TRANS_FEAT(EXT, aa64_sve, do_EXT, a->rd, a->rn, a->rm, a->imm) -TRANS_FEAT(EXT_sve2, aa64_sve2, do_EXT, a->rd, a->rn, (a->rn + 1) % 32, a-= >imm) +TRANS_FEAT(EXT, aa64_sme_or_sve, do_EXT, a->rd, a->rn, a->rm, a->imm) +TRANS_FEAT(EXT_sve2, aa64_sme_or_sve2, do_EXT, a->rd, a->rn, (a->rn + 1) %= 32, a->imm) =20 static bool trans_EXTQ(DisasContext *s, arg_EXTQ *a) { @@ -2265,7 +2265,7 @@ static bool trans_EXTQ(DisasContext *s, arg_EXTQ *a) =20 static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2278,7 +2278,7 @@ static bool trans_DUP_s(DisasContext *s, arg_DUP_s *a) =20 static bool trans_DUP_x(DisasContext *s, arg_DUP_x *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if ((a->imm & 0x1f) =3D=3D 0) { @@ -2347,7 +2347,7 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz = *a, TCGv_i64 val) =20 static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2360,7 +2360,7 @@ static bool trans_INSR_f(DisasContext *s, arg_rrr_esz= *a) =20 static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2373,19 +2373,19 @@ static gen_helper_gvec_2 * const rev_fns[4] =3D { gen_helper_sve_rev_b, gen_helper_sve_rev_h, gen_helper_sve_rev_s, gen_helper_sve_rev_d }; -TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn= , 0) +TRANS_FEAT(REV_v, aa64_sme_or_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd= , a->rn, 0) =20 static gen_helper_gvec_3 * const sve_tbl_fns[4] =3D { gen_helper_sve_tbl_b, gen_helper_sve_tbl_h, gen_helper_sve_tbl_s, gen_helper_sve_tbl_d }; -TRANS_FEAT(TBL, aa64_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz], a, 0) +TRANS_FEAT(TBL, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz]= , a, 0) =20 static gen_helper_gvec_4 * const sve2_tbl_fns[4] =3D { gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h, gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d }; -TRANS_FEAT(TBL_sve2, aa64_sve2, gen_gvec_ool_zzzz, sve2_tbl_fns[a->esz], +TRANS_FEAT(TBL_sve2, aa64_sme_or_sve2, gen_gvec_ool_zzzz, sve2_tbl_fns[a->= esz], a->rd, a->rn, (a->rn + 1) % 32, a->rm, 0) =20 static gen_helper_gvec_3 * const tblq_fns[4] =3D { @@ -2399,7 +2399,7 @@ static gen_helper_gvec_3 * const tbx_fns[4] =3D { gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h, gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d }; -TRANS_FEAT(TBX, aa64_sve2, gen_gvec_ool_arg_zzz, tbx_fns[a->esz], a, 0) +TRANS_FEAT(TBX, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, tbx_fns[a->esz], a= , 0) =20 static gen_helper_gvec_3 * const tbxq_fns[4] =3D { gen_helper_sve2p1_tbxq_b, gen_helper_sve2p1_tbxq_h, @@ -2515,7 +2515,7 @@ static bool trans_UNPK(DisasContext *s, arg_UNPK *a) { gen_helper_sve_sunpk_d, gen_helper_sve_uunpk_d }, }; =20 - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2581,16 +2581,16 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_e= sz *a, bool high_odd, return true; } =20 -TRANS_FEAT(ZIP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_zip_p) -TRANS_FEAT(ZIP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_zip_p) -TRANS_FEAT(UZP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_uzp_p) -TRANS_FEAT(UZP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_uzp_p) -TRANS_FEAT(TRN1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_trn_p) -TRANS_FEAT(TRN2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_trn_p) +TRANS_FEAT(ZIP1_p, aa64_sme_or_sve, do_perm_pred3, a, 0, gen_helper_sve_zi= p_p) +TRANS_FEAT(ZIP2_p, aa64_sme_or_sve, do_perm_pred3, a, 1, gen_helper_sve_zi= p_p) +TRANS_FEAT(UZP1_p, aa64_sme_or_sve, do_perm_pred3, a, 0, gen_helper_sve_uz= p_p) +TRANS_FEAT(UZP2_p, aa64_sme_or_sve, do_perm_pred3, a, 1, gen_helper_sve_uz= p_p) +TRANS_FEAT(TRN1_p, aa64_sme_or_sve, do_perm_pred3, a, 0, gen_helper_sve_tr= n_p) +TRANS_FEAT(TRN2_p, aa64_sme_or_sve, do_perm_pred3, a, 1, gen_helper_sve_tr= n_p) =20 -TRANS_FEAT(REV_p, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_rev_p) -TRANS_FEAT(PUNPKLO, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_punpk_p) -TRANS_FEAT(PUNPKHI, aa64_sve, do_perm_pred2, a, 1, gen_helper_sve_punpk_p) +TRANS_FEAT(REV_p, aa64_sme_or_sve, do_perm_pred2, a, 0, gen_helper_sve_rev= _p) +TRANS_FEAT(PUNPKLO, aa64_sme_or_sve, do_perm_pred2, a, 0, gen_helper_sve_p= unpk_p) +TRANS_FEAT(PUNPKHI, aa64_sme_or_sve, do_perm_pred2, a, 1, gen_helper_sve_p= unpk_p) =20 /* *** SVE Permute - Interleaving Group @@ -2617,9 +2617,9 @@ static gen_helper_gvec_3 * const zip_fns[4] =3D { gen_helper_sve_zip_b, gen_helper_sve_zip_h, gen_helper_sve_zip_s, gen_helper_sve_zip_d, }; -TRANS_FEAT(ZIP1_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(ZIP1_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, zip_fns[a->esz], a, 0) -TRANS_FEAT(ZIP2_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(ZIP2_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, zip_fns[a->esz], a, vec_full_reg_size(s) / 2) =20 TRANS_FEAT_NONSTREAMING(ZIP1_q, aa64_sve_f64mm, do_interleave_q, @@ -2641,9 +2641,9 @@ static gen_helper_gvec_3 * const uzp_fns[4] =3D { gen_helper_sve_uzp_b, gen_helper_sve_uzp_h, gen_helper_sve_uzp_s, gen_helper_sve_uzp_d, }; -TRANS_FEAT(UZP1_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UZP1_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, uzp_fns[a->esz], a, 0) -TRANS_FEAT(UZP2_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UZP2_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, uzp_fns[a->esz], a, 1 << a->esz) =20 TRANS_FEAT_NONSTREAMING(UZP1_q, aa64_sve_f64mm, do_interleave_q, @@ -2665,9 +2665,9 @@ static gen_helper_gvec_3 * const trn_fns[4] =3D { gen_helper_sve_trn_s, gen_helper_sve_trn_d, }; =20 -TRANS_FEAT(TRN1_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(TRN1_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, trn_fns[a->esz], a, 0) -TRANS_FEAT(TRN2_z, aa64_sve, gen_gvec_ool_arg_zzz, +TRANS_FEAT(TRN2_z, aa64_sme_or_sve, gen_gvec_ool_arg_zzz, trn_fns[a->esz], a, 1 << a->esz) =20 TRANS_FEAT_NONSTREAMING(TRN1_q, aa64_sve_f64mm, do_interleave_q, @@ -2828,8 +2828,8 @@ static bool do_clast_vector(DisasContext *s, arg_rprr= _esz *a, bool before) return true; } =20 -TRANS_FEAT(CLASTA_z, aa64_sve, do_clast_vector, a, false) -TRANS_FEAT(CLASTB_z, aa64_sve, do_clast_vector, a, true) +TRANS_FEAT(CLASTA_z, aa64_sme_or_sve, do_clast_vector, a, false) +TRANS_FEAT(CLASTB_z, aa64_sme_or_sve, do_clast_vector, a, true) =20 /* Compute CLAST for a scalar. */ static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm, @@ -2873,8 +2873,8 @@ static bool do_clast_fp(DisasContext *s, arg_rpr_esz = *a, bool before) return true; } =20 -TRANS_FEAT(CLASTA_v, aa64_sve, do_clast_fp, a, false) -TRANS_FEAT(CLASTB_v, aa64_sve, do_clast_fp, a, true) +TRANS_FEAT(CLASTA_v, aa64_sme_or_sve, do_clast_fp, a, false) +TRANS_FEAT(CLASTB_v, aa64_sme_or_sve, do_clast_fp, a, true) =20 /* Compute CLAST for a Xreg. */ static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before) @@ -2906,8 +2906,8 @@ static bool do_clast_general(DisasContext *s, arg_rpr= _esz *a, bool before) return true; } =20 -TRANS_FEAT(CLASTA_r, aa64_sve, do_clast_general, a, false) -TRANS_FEAT(CLASTB_r, aa64_sve, do_clast_general, a, true) +TRANS_FEAT(CLASTA_r, aa64_sme_or_sve, do_clast_general, a, false) +TRANS_FEAT(CLASTB_r, aa64_sme_or_sve, do_clast_general, a, true) =20 /* Compute LAST for a scalar. */ static TCGv_i64 do_last_scalar(DisasContext *s, int esz, @@ -2935,8 +2935,8 @@ static bool do_last_fp(DisasContext *s, arg_rpr_esz *= a, bool before) return true; } =20 -TRANS_FEAT(LASTA_v, aa64_sve, do_last_fp, a, false) -TRANS_FEAT(LASTB_v, aa64_sve, do_last_fp, a, true) +TRANS_FEAT(LASTA_v, aa64_sme_or_sve, do_last_fp, a, false) +TRANS_FEAT(LASTB_v, aa64_sme_or_sve, do_last_fp, a, true) =20 /* Compute LAST for a Xreg. */ static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before) @@ -2948,12 +2948,12 @@ static bool do_last_general(DisasContext *s, arg_rp= r_esz *a, bool before) return true; } =20 -TRANS_FEAT(LASTA_r, aa64_sve, do_last_general, a, false) -TRANS_FEAT(LASTB_r, aa64_sve, do_last_general, a, true) +TRANS_FEAT(LASTA_r, aa64_sme_or_sve, do_last_general, a, false) +TRANS_FEAT(LASTB_r, aa64_sme_or_sve, do_last_general, a, true) =20 static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2964,7 +2964,7 @@ static bool trans_CPY_m_r(DisasContext *s, arg_rpr_es= z *a) =20 static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -2979,22 +2979,22 @@ static gen_helper_gvec_3 * const revb_fns[4] =3D { NULL, gen_helper_sve_revb_h, gen_helper_sve_revb_s, gen_helper_sve_revb_d, }; -TRANS_FEAT(REVB, aa64_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], a, 0) +TRANS_FEAT(REVB, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], = a, 0) =20 static gen_helper_gvec_3 * const revh_fns[4] =3D { NULL, NULL, gen_helper_sve_revh_s, gen_helper_sve_revh_d, }; -TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0) +TRANS_FEAT(REVH, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], = a, 0) =20 -TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz, +TRANS_FEAT(REVW, aa64_sme_or_sve, gen_gvec_ool_arg_zpz, a->esz =3D=3D 3 ? gen_helper_sve_revw_d : NULL, a, 0) =20 TRANS_FEAT(REVD, aa64_sme, gen_gvec_ool_arg_zpz, gen_helper_sme_revd_q, a,= 0) =20 -TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz, +TRANS_FEAT(SPLICE, aa64_sme_or_sve, gen_gvec_ool_arg_zpzz, gen_helper_sve_splice, a, a->esz) =20 -TRANS_FEAT(SPLICE_sve2, aa64_sve2, gen_gvec_ool_zzzp, gen_helper_sve_splic= e, +TRANS_FEAT(SPLICE_sve2, aa64_sme_or_sve2, gen_gvec_ool_zzzp, gen_helper_sv= e_splice, a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz) =20 /* @@ -3038,7 +3038,7 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_e= sz *a, gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \ gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \ }; \ - TRANS_FEAT(NAME##_ppzz, aa64_sve, do_ppzz_flags, \ + TRANS_FEAT(NAME##_ppzz, aa64_sme_or_sve, do_ppzz_flags, = \ a, name##_ppzz_fns[a->esz]) =20 DO_PPZZ(CMPEQ, cmpeq) @@ -3055,7 +3055,7 @@ DO_PPZZ(CMPHS, cmphs) gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \ gen_helper_sve_##name##_ppzw_s, NULL \ }; \ - TRANS_FEAT(NAME##_ppzw, aa64_sve, do_ppzz_flags, \ + TRANS_FEAT(NAME##_ppzw, aa64_sme_or_sve, do_ppzz_flags, = \ a, name##_ppzw_fns[a->esz]) =20 DO_PPZW(CMPEQ, cmpeq) @@ -3110,7 +3110,7 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_e= sz *a, gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \ gen_helper_sve_##name##_ppzi_s, gen_helper_sve_##name##_ppzi_d, \ }; \ - TRANS_FEAT(NAME##_ppzi, aa64_sve, do_ppzi_flags, a, \ + TRANS_FEAT(NAME##_ppzi, aa64_sme_or_sve, do_ppzi_flags, a, = \ name##_ppzi_fns[a->esz]) =20 DO_PPZI(CMPEQ, cmpeq) @@ -3190,22 +3190,22 @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a, return true; } =20 -TRANS_FEAT(BRKPA, aa64_sve, do_brk3, a, +TRANS_FEAT(BRKPA, aa64_sme_or_sve, do_brk3, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas) -TRANS_FEAT(BRKPB, aa64_sve, do_brk3, a, +TRANS_FEAT(BRKPB, aa64_sme_or_sve, do_brk3, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs) =20 -TRANS_FEAT(BRKA_m, aa64_sve, do_brk2, a, +TRANS_FEAT(BRKA_m, aa64_sme_or_sve, do_brk2, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m) -TRANS_FEAT(BRKB_m, aa64_sve, do_brk2, a, +TRANS_FEAT(BRKB_m, aa64_sme_or_sve, do_brk2, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m) =20 -TRANS_FEAT(BRKA_z, aa64_sve, do_brk2, a, +TRANS_FEAT(BRKA_z, aa64_sme_or_sve, do_brk2, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z) -TRANS_FEAT(BRKB_z, aa64_sve, do_brk2, a, +TRANS_FEAT(BRKB_z, aa64_sme_or_sve, do_brk2, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z) =20 -TRANS_FEAT(BRKN, aa64_sve, do_brk2, a, +TRANS_FEAT(BRKN, aa64_sme_or_sve, do_brk2, a, gen_helper_sve_brkn, gen_helper_sve_brkns) =20 /* @@ -3250,7 +3250,7 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, in= t esz, int pn, int pg) =20 static bool trans_CNTP(DisasContext *s, arg_CNTP *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3291,7 +3291,7 @@ static bool trans_CNTP_c(DisasContext *s, arg_CNTP_c = *a) =20 static bool trans_INCDECP_r(DisasContext *s, arg_incdec_pred *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3310,7 +3310,7 @@ static bool trans_INCDECP_r(DisasContext *s, arg_incd= ec_pred *a) =20 static bool trans_INCDECP_z(DisasContext *s, arg_incdec2_pred *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3327,7 +3327,7 @@ static bool trans_INCDECP_z(DisasContext *s, arg_incd= ec2_pred *a) =20 static bool trans_SINCDECP_r_32(DisasContext *s, arg_incdec_pred *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3342,7 +3342,7 @@ static bool trans_SINCDECP_r_32(DisasContext *s, arg_= incdec_pred *a) =20 static bool trans_SINCDECP_r_64(DisasContext *s, arg_incdec_pred *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3357,7 +3357,7 @@ static bool trans_SINCDECP_r_64(DisasContext *s, arg_= incdec_pred *a) =20 static bool trans_SINCDECP_z(DisasContext *s, arg_incdec2_pred *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3374,7 +3374,7 @@ static bool trans_SINCDECP_z(DisasContext *s, arg_inc= dec2_pred *a) =20 static bool trans_CTERM(DisasContext *s, arg_CTERM *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!sve_access_check(s)) { @@ -3498,9 +3498,9 @@ static bool do_WHILE(DisasContext *s, arg_while *a, return true; } =20 -TRANS_FEAT(WHILE_lt, aa64_sve, do_WHILE, +TRANS_FEAT(WHILE_lt, aa64_sme_or_sve, do_WHILE, a, true, 0, 0, gen_helper_sve_whilel) -TRANS_FEAT(WHILE_gt, aa64_sve2, do_WHILE, +TRANS_FEAT(WHILE_gt, aa64_sme_or_sve2, do_WHILE, a, false, 0, 0, gen_helper_sve_whileg) =20 TRANS_FEAT(WHILE_lt_pair, aa64_sme2_or_sve2p1, do_WHILE, @@ -3525,7 +3525,7 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) unsigned vsz =3D vec_full_reg_size(s); unsigned desc =3D 0; =20 - if (!dc_isar_feature(aa64_sve2, s)) { + if (!dc_isar_feature(aa64_sme_or_sve2, s)) { return false; } if (!sve_access_check(s)) { @@ -3618,7 +3618,7 @@ TRANS_FEAT(PEXT_2, aa64_sme2_or_sve2p1, do_pext, a, 2) =20 static bool trans_FDUP(DisasContext *s, arg_FDUP *a) { - if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sve, s)) { + if (a->esz =3D=3D 0 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3635,7 +3635,7 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a) =20 static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3646,7 +3646,7 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a) return true; } =20 -TRANS_FEAT(ADD_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_addi, a) +TRANS_FEAT(ADD_zzi, aa64_sme_or_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_add= i, a) =20 static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a) { @@ -3685,7 +3685,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_e= sz *a) .scalar_first =3D true } }; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -3697,7 +3697,7 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_e= sz *a) return true; } =20 -TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a) +TRANS_FEAT(MUL_zzi, aa64_sme_or_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_mul= i, a) =20 static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d) { @@ -3708,10 +3708,10 @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz= *a, bool u, bool d) return true; } =20 -TRANS_FEAT(SQADD_zzi, aa64_sve, do_zzi_sat, a, false, false) -TRANS_FEAT(UQADD_zzi, aa64_sve, do_zzi_sat, a, true, false) -TRANS_FEAT(SQSUB_zzi, aa64_sve, do_zzi_sat, a, false, true) -TRANS_FEAT(UQSUB_zzi, aa64_sve, do_zzi_sat, a, true, true) +TRANS_FEAT(SQADD_zzi, aa64_sme_or_sve, do_zzi_sat, a, false, false) +TRANS_FEAT(UQADD_zzi, aa64_sme_or_sve, do_zzi_sat, a, true, false) +TRANS_FEAT(SQSUB_zzi, aa64_sme_or_sve, do_zzi_sat, a, false, true) +TRANS_FEAT(UQSUB_zzi, aa64_sme_or_sve, do_zzi_sat, a, true, true) =20 static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i= *fn) { @@ -3729,7 +3729,7 @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *= a, gen_helper_gvec_2i *fn) gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \ gen_helper_sve_##name##i_s, gen_helper_sve_##name##i_d, \ }; \ - TRANS_FEAT(NAME##_zzi, aa64_sve, do_zzi_ool, a, name##i_fns[a->esz]) + TRANS_FEAT(NAME##_zzi, aa64_sme_or_sve, do_zzi_ool, a, name##i_fns[a->= esz]) =20 DO_ZZI(SMAX, smax) DO_ZZI(UMAX, umax) @@ -3742,20 +3742,20 @@ static gen_helper_gvec_4 * const dot_fns[2][2] =3D { { gen_helper_gvec_sdot_4b, gen_helper_gvec_sdot_4h }, { gen_helper_gvec_udot_4b, gen_helper_gvec_udot_4h } }; -TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz, +TRANS_FEAT(DOT_zzzz, aa64_sme_or_sve, gen_gvec_ool_zzzz, dot_fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0) =20 /* * SVE Multiply - Indexed */ =20 -TRANS_FEAT(SDOT_zzxw_4s, aa64_sve, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(SDOT_zzxw_4s, aa64_sme_or_sve, gen_gvec_ool_arg_zzxz, gen_helper_gvec_sdot_idx_4b, a) -TRANS_FEAT(SDOT_zzxw_4d, aa64_sve, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(SDOT_zzxw_4d, aa64_sme_or_sve, gen_gvec_ool_arg_zzxz, gen_helper_gvec_sdot_idx_4h, a) -TRANS_FEAT(UDOT_zzxw_4s, aa64_sve, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(UDOT_zzxw_4s, aa64_sme_or_sve, gen_gvec_ool_arg_zzxz, gen_helper_gvec_udot_idx_4b, a) -TRANS_FEAT(UDOT_zzxw_4d, aa64_sve, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(UDOT_zzxw_4d, aa64_sme_or_sve, gen_gvec_ool_arg_zzxz, gen_helper_gvec_udot_idx_4h, a) =20 TRANS_FEAT(SUDOT_zzxw_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, @@ -3769,7 +3769,7 @@ TRANS_FEAT(UDOT_zzxw_2s, aa64_sme2_or_sve2p1, gen_gve= c_ool_arg_zzxz, gen_helper_gvec_udot_idx_2h, a) =20 #define DO_SVE2_RRX(NAME, FUNC) \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_zzz, FUNC, \ a->rd, a->rn, a->rm, a->index) =20 DO_SVE2_RRX(MUL_zzx_h, gen_helper_gvec_mul_idx_h) @@ -3787,7 +3787,7 @@ DO_SVE2_RRX(SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_= idx_d) #undef DO_SVE2_RRX =20 #define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_zzz, FUNC, \ a->rd, a->rn, a->rm, (a->index << 1) | TOP) =20 DO_SVE2_RRX_TB(SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false) @@ -3808,7 +3808,7 @@ DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_id= x_d, true) #undef DO_SVE2_RRX_TB =20 #define DO_SVE2_RRXR(NAME, FUNC) \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzxz, FUNC, a) + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_arg_zzxz, FUNC, a) =20 DO_SVE2_RRXR(MLA_zzxz_h, gen_helper_gvec_mla_idx_h) DO_SVE2_RRXR(MLA_zzxz_s, gen_helper_gvec_mla_idx_s) @@ -3829,7 +3829,7 @@ DO_SVE2_RRXR(SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmls= h_idx_d) #undef DO_SVE2_RRXR =20 #define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_zzzz, FUNC, \ a->rd, a->rn, a->rm, a->ra, (a->index << 1) | TOP) =20 DO_SVE2_RRXR_TB(SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false) @@ -3865,7 +3865,7 @@ DO_SVE2_RRXR_TB(UMLSLT_zzxw_d, gen_helper_sve2_umlsl_= idx_d, true) #undef DO_SVE2_RRXR_TB =20 #define DO_SVE2_RRXR_ROT(NAME, FUNC) \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \ + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_zzzz, FUNC, \ a->rd, a->rn, a->rm, a->ra, (a->index << 2) | a->rot) =20 DO_SVE2_RRXR_ROT(CMLA_zzxz_h, gen_helper_sve2_cmla_idx_h) @@ -3898,7 +3898,7 @@ static gen_helper_gvec_4_ptr * const fmla_idx_fns[4] = =3D { gen_helper_gvec_bfmla_idx, gen_helper_gvec_fmla_idx_h, gen_helper_gvec_fmla_idx_s, gen_helper_gvec_fmla_idx_d }; -TRANS_FEAT(FMLA_zzxz, aa64_sve, do_fmla_zzxz, a, fmla_idx_fns[a->esz]) +TRANS_FEAT(FMLA_zzxz, aa64_sme_or_sve, do_fmla_zzxz, a, fmla_idx_fns[a->es= z]) =20 static gen_helper_gvec_4_ptr * const fmls_idx_fns[4][2] =3D { { gen_helper_gvec_bfmls_idx, gen_helper_gvec_ah_bfmls_idx }, @@ -3906,7 +3906,7 @@ static gen_helper_gvec_4_ptr * const fmls_idx_fns[4][= 2] =3D { { gen_helper_gvec_fmls_idx_s, gen_helper_gvec_ah_fmls_idx_s }, { gen_helper_gvec_fmls_idx_d, gen_helper_gvec_ah_fmls_idx_d }, }; -TRANS_FEAT(FMLS_zzxz, aa64_sve, do_fmla_zzxz, a, +TRANS_FEAT(FMLS_zzxz, aa64_sme_or_sve, do_fmla_zzxz, a, fmls_idx_fns[a->esz][s->fpcr_ah]) =20 /* @@ -3917,7 +3917,7 @@ static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = =3D { gen_helper_gvec_fmul_idx_b16, gen_helper_gvec_fmul_idx_h, gen_helper_gvec_fmul_idx_s, gen_helper_gvec_fmul_idx_d, }; -TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz, +TRANS_FEAT(FMUL_zzx, aa64_sme_or_sve, gen_gvec_fpst_zzz, fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 @@ -3965,7 +3965,7 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a, NULL, gen_helper_sve_##name##_h, \ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ }; \ - TRANS_FEAT(NAME, aa64_sve, do_reduce, a, name##_fns[a->esz]) + TRANS_FEAT(NAME, aa64_sme_or_sve, do_reduce, a, name##_fns[a->esz]) =20 #define DO_VPZ_AH(NAME, name) \ static gen_helper_fp_reduce * const name##_fns[4] =3D { = \ @@ -3976,7 +3976,7 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a, NULL, gen_helper_sve_ah_##name##_h, \ gen_helper_sve_ah_##name##_s, gen_helper_sve_ah_##name##_d, \ }; \ - TRANS_FEAT(NAME, aa64_sve, do_reduce, a, \ + TRANS_FEAT(NAME, aa64_sme_or_sve, do_reduce, a, = \ s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz]) =20 DO_VPZ(FADDV, faddv) @@ -4047,7 +4047,7 @@ static gen_helper_gvec_2_ptr * const frecpe_rpres_fns= [] =3D { NULL, gen_helper_gvec_frecpe_h, gen_helper_gvec_frecpe_rpres_s, gen_helper_gvec_frecpe_d, }; -TRANS_FEAT(FRECPE, aa64_sve, gen_gvec_fpst_ah_arg_zz, +TRANS_FEAT(FRECPE, aa64_sme_or_sve, gen_gvec_fpst_ah_arg_zz, s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ? frecpe_rpres_fns[a->esz] : frecpe_fns[a->esz], a, 0) =20 @@ -4059,7 +4059,7 @@ static gen_helper_gvec_2_ptr * const frsqrte_rpres_fn= s[] =3D { NULL, gen_helper_gvec_frsqrte_h, gen_helper_gvec_frsqrte_rpres_s, gen_helper_gvec_frsqrte_d, }; -TRANS_FEAT(FRSQRTE, aa64_sve, gen_gvec_fpst_ah_arg_zz, +TRANS_FEAT(FRSQRTE, aa64_sme_or_sve, gen_gvec_fpst_ah_arg_zz, s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ? frsqrte_rpres_fns[a->esz] : frsqrte_fns[a->esz], a, 0) =20 @@ -4091,7 +4091,7 @@ static bool do_ppz_fp(DisasContext *s, arg_rpr_esz *a, NULL, gen_helper_sve_##name##_h, \ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \ }; \ - TRANS_FEAT(NAME, aa64_sve, do_ppz_fp, a, name##_fns[a->esz]) + TRANS_FEAT(NAME, aa64_sme_or_sve, do_ppz_fp, a, name##_fns[a->esz]) =20 DO_PPZ(FCMGE_ppz0, fcmge0) DO_PPZ(FCMGT_ppz0, fcmgt0) @@ -4164,7 +4164,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz= *a) gen_helper_gvec_##name##_b16, gen_helper_gvec_##name##_h, \ gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \ }; \ - TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_arg_zzz, name##_fns[a->esz], = a, 0) + TRANS_FEAT(NAME, aa64_sme_or_sve, gen_gvec_fpst_arg_zzz, name##_fns[a-= >esz], a, 0) =20 #define DO_FP3_AH(NAME, name) \ static gen_helper_gvec_3_ptr * const name##_fns[4] =3D { \ @@ -4175,7 +4175,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz= *a) NULL, gen_helper_gvec_ah_##name##_h, \ gen_helper_gvec_ah_##name##_s, gen_helper_gvec_ah_##name##_d \ }; \ - TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_ah_arg_zzz, \ + TRANS_FEAT(NAME, aa64_sme_or_sve, gen_gvec_fpst_ah_arg_zzz, \ s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz], a,= 0) =20 DO_FP3(FADD_zzz, fadd) @@ -4238,17 +4238,17 @@ TRANS_FEAT_NONSTREAMING(FTSMUL, aa64_sve, gen_gvec_= fpst_arg_zzz, s->fpcr_ah ? name##_ah_zpzz_fns[a->esz] : \ name##_zpzz_fns[a->esz], a) =20 -DO_ZPZZ_FP_B16(FADD_zpzz, aa64_sve, sve_fadd) -DO_ZPZZ_FP_B16(FSUB_zpzz, aa64_sve, sve_fsub) -DO_ZPZZ_FP_B16(FMUL_zpzz, aa64_sve, sve_fmul) -DO_ZPZZ_AH_FP_B16(FMIN_zpzz, aa64_sve, sve_fmin, sve_ah_fmin) -DO_ZPZZ_AH_FP_B16(FMAX_zpzz, aa64_sve, sve_fmax, sve_ah_fmax) -DO_ZPZZ_FP_B16(FMINNM_zpzz, aa64_sve, sve_fminnum) -DO_ZPZZ_FP_B16(FMAXNM_zpzz, aa64_sve, sve_fmaxnum) -DO_ZPZZ_AH_FP(FABD, aa64_sve, sve_fabd, sve_ah_fabd) -DO_ZPZZ_FP(FSCALE, aa64_sve, sve_fscalbn) -DO_ZPZZ_FP(FDIV, aa64_sve, sve_fdiv) -DO_ZPZZ_FP(FMULX, aa64_sve, sve_fmulx) +DO_ZPZZ_FP_B16(FADD_zpzz, aa64_sme_or_sve, sve_fadd) +DO_ZPZZ_FP_B16(FSUB_zpzz, aa64_sme_or_sve, sve_fsub) +DO_ZPZZ_FP_B16(FMUL_zpzz, aa64_sme_or_sve, sve_fmul) +DO_ZPZZ_AH_FP_B16(FMIN_zpzz, aa64_sme_or_sve, sve_fmin, sve_ah_fmin) +DO_ZPZZ_AH_FP_B16(FMAX_zpzz, aa64_sme_or_sve, sve_fmax, sve_ah_fmax) +DO_ZPZZ_FP_B16(FMINNM_zpzz, aa64_sme_or_sve, sve_fminnum) +DO_ZPZZ_FP_B16(FMAXNM_zpzz, aa64_sme_or_sve, sve_fmaxnum) +DO_ZPZZ_AH_FP(FABD, aa64_sme_or_sve, sve_fabd, sve_ah_fabd) +DO_ZPZZ_FP(FSCALE, aa64_sme_or_sve, sve_fscalbn) +DO_ZPZZ_FP(FDIV, aa64_sme_or_sve, sve_fdiv) +DO_ZPZZ_FP(FMULX, aa64_sme_or_sve, sve_fmulx) =20 typedef void gen_helper_sve_fp2scalar(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr, TCGv_i32); @@ -4297,7 +4297,7 @@ static bool do_fp_imm(DisasContext *s, arg_rpri_esz *= a, uint64_t imm, { float32_##const0, float32_##const1 }, \ { float64_##const0, float64_##const1 }, \ }; \ - TRANS_FEAT(NAME##_zpzi, aa64_sve, do_fp_imm, a, \ + TRANS_FEAT(NAME##_zpzi, aa64_sme_or_sve, do_fp_imm, a, = \ name##_const[a->esz][a->imm], name##_fns[a->esz]) =20 #define DO_FP_AH_IMM(NAME, name, const0, const1) \ @@ -4317,7 +4317,7 @@ static bool do_fp_imm(DisasContext *s, arg_rpri_esz *= a, uint64_t imm, { float32_##const0, float32_##const1 }, \ { float64_##const0, float64_##const1 }, \ }; \ - TRANS_FEAT(NAME##_zpzi, aa64_sve, do_fp_imm, a, \ + TRANS_FEAT(NAME##_zpzi, aa64_sme_or_sve, do_fp_imm, a, = \ name##_const[a->esz][a->imm], \ s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz]) =20 @@ -4355,7 +4355,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *= a, NULL, gen_helper_sve_##name##_h, \ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d \ }; \ - TRANS_FEAT(NAME##_ppzz, aa64_sve, do_fp_cmp, a, name##_fns[a->esz]) + TRANS_FEAT(NAME##_ppzz, aa64_sme_or_sve, do_fp_cmp, a, name##_fns[a->e= sz]) =20 DO_FPCMP(FCMGE, fcmge) DO_FPCMP(FCMGT, fcmgt) @@ -4371,7 +4371,7 @@ static gen_helper_gvec_4_ptr * const fcadd_fns[] =3D { NULL, gen_helper_sve_fcadd_h, gen_helper_sve_fcadd_s, gen_helper_sve_fcadd_d, }; -TRANS_FEAT(FCADD, aa64_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz], +TRANS_FEAT(FCADD, aa64_sme_or_sve, gen_gvec_fpst_zzzp, fcadd_fns[a->esz], a->rd, a->rn, a->rm, a->pg, a->rot | (s->fpcr_ah << 1), a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 @@ -4395,7 +4395,7 @@ static bool do_fmla_zpzzz(DisasContext *s, arg_rprrr_= esz *a, gen_helper_sve_##ah_name##_b16, gen_helper_sve_##ah_name##_h, \ gen_helper_sve_##ah_name##_s, gen_helper_sve_##ah_name##_d \ }; \ - TRANS_FEAT(NAME, aa64_sve, do_fmla_zpzzz, a, \ + TRANS_FEAT(NAME, aa64_sme_or_sve, do_fmla_zpzzz, a, = \ s->fpcr_ah ? name##_ah_fns[a->esz] : name##_fns[a->esz]) =20 /* We don't need an ah_fmla_zpzzz because fmla doesn't negate anything */ @@ -4410,14 +4410,14 @@ static gen_helper_gvec_5_ptr * const fcmla_fns[4] = =3D { NULL, gen_helper_sve_fcmla_zpzzz_h, gen_helper_sve_fcmla_zpzzz_s, gen_helper_sve_fcmla_zpzzz_d, }; -TRANS_FEAT(FCMLA_zpzzz, aa64_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a->esz], +TRANS_FEAT(FCMLA_zpzzz, aa64_sme_or_sve, gen_gvec_fpst_zzzzp, fcmla_fns[a-= >esz], a->rd, a->rn, a->rm, a->ra, a->pg, a->rot | (s->fpcr_ah << 2), a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static gen_helper_gvec_4_ptr * const fcmla_idx_fns[4] =3D { NULL, gen_helper_gvec_fcmlah_idx, gen_helper_gvec_fcmlas_idx, NULL }; -TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[a->esz], +TRANS_FEAT(FCMLA_zzxz, aa64_sme_or_sve, gen_gvec_fpst_zzzz, fcmla_idx_fns[= a->esz], a->rd, a->rn, a->rm, a->ra, a->index * 4 + a->rot, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 @@ -4425,53 +4425,53 @@ TRANS_FEAT(FCMLA_zzxz, aa64_sve, gen_gvec_fpst_zzzz= , fcmla_idx_fns[a->esz], *** SVE Floating Point Unary Operations Predicated Group */ =20 -TRANS_FEAT(FCVT_sh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sh, a, 0, FPST_A64) -TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16) =20 TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 -TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_dh, a, 0, FPST_A64) -TRANS_FEAT(FCVT_hd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hd, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVT_ds, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_ds, a, 0, FPST_A64) -TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVT_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_sd, a, 0, FPST_A64) =20 -TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZU_hh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZS_hs, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hs, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZU_hs, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_hs, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZS_hd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_hd, a, 0, FPST_A64_F16) -TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_hd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_hd, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_ss, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_ss, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_ss, a, 0, FPST_A64) -TRANS_FEAT(FCVTZS_sd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_sd, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_sd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_sd, a, 0, FPST_A64) -TRANS_FEAT(FCVTZS_ds, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_ds, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_ds, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_ds, a, 0, FPST_A64) =20 -TRANS_FEAT(FCVTZS_dd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZS_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzs_dd, a, 0, FPST_A64) -TRANS_FEAT(FCVTZU_dd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTZU_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvtzu_dd, a, 0, FPST_A64) =20 static gen_helper_gvec_3_ptr * const frint_fns[] =3D { @@ -4480,7 +4480,7 @@ static gen_helper_gvec_3_ptr * const frint_fns[] =3D { gen_helper_sve_frint_s, gen_helper_sve_frint_d }; -TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz], +TRANS_FEAT(FRINTI, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->es= z], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static gen_helper_gvec_3_ptr * const frintx_fns[] =3D { @@ -4489,7 +4489,7 @@ static gen_helper_gvec_3_ptr * const frintx_fns[] =3D= { gen_helper_sve_frintx_s, gen_helper_sve_frintx_d }; -TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz], +TRANS_FEAT(FRINTX, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->e= sz], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64); =20 static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, @@ -4519,63 +4519,63 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_= esz *a, return true; } =20 -TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a, +TRANS_FEAT(FRINTN, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_TIEEVEN, frint_fns[a->esz]) -TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a, +TRANS_FEAT(FRINTP, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_POSINF, frint_fns[a->esz]) -TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a, +TRANS_FEAT(FRINTM, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_NEGINF, frint_fns[a->esz]) -TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a, +TRANS_FEAT(FRINTZ, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_ZERO, frint_fns[a->esz]) -TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a, +TRANS_FEAT(FRINTA, aa64_sme_or_sve, do_frint_mode, a, FPROUNDING_TIEAWAY, frint_fns[a->esz]) =20 static gen_helper_gvec_3_ptr * const frecpx_fns[] =3D { NULL, gen_helper_sve_frecpx_h, gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d, }; -TRANS_FEAT(FRECPX, aa64_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->esz], +TRANS_FEAT(FRECPX, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->e= sz], a, 0, select_ah_fpst(s, a->esz)) =20 static gen_helper_gvec_3_ptr * const fsqrt_fns[] =3D { NULL, gen_helper_sve_fsqrt_h, gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d, }; -TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz], +TRANS_FEAT(FSQRT, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz= ], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 -TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(SCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_sh, a, 0, FPST_A64_F16) -TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_dh, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_ss, a, 0, FPST_A64) -TRANS_FEAT(SCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_ds, a, 0, FPST_A64) =20 -TRANS_FEAT(SCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_sd, a, 0, FPST_A64) -TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(SCVTF_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_scvt_dd, a, 0, FPST_A64) =20 -TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_hh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_hh, a, 0, FPST_A64_F16) -TRANS_FEAT(UCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_sh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_sh, a, 0, FPST_A64_F16) -TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_dh, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_dh, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_ss, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_ss, a, 0, FPST_A64) -TRANS_FEAT(UCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_ds, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_ds, a, 0, FPST_A64) -TRANS_FEAT(UCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_sd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_sd, a, 0, FPST_A64) =20 -TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(UCVTF_dd, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_ucvt_dd, a, 0, FPST_A64) =20 /* @@ -4803,7 +4803,7 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int = vofs, =20 static bool trans_LDR_zri(DisasContext *s, arg_rri *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -4817,7 +4817,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a) =20 static bool trans_LDR_pri(DisasContext *s, arg_rri *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -4831,7 +4831,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a) =20 static bool trans_STR_zri(DisasContext *s, arg_rri *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -4845,7 +4845,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a) =20 static bool trans_STR_pri(DisasContext *s, arg_rri *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -5101,7 +5101,7 @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_l= oad *a) /* dtypes 16-18 are artificial, representing 128-bit element */ switch (a->dtype) { case 0 ... 15: - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } break; @@ -5134,7 +5134,7 @@ static bool trans_LD_zpri(DisasContext *s, arg_rpri_l= oad *a) /* dtypes 16-18 are artificial, representing 128-bit element */ switch (a->dtype) { case 0 ... 15: - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } break; @@ -5420,7 +5420,7 @@ static void do_ldrq(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int dtype) =20 static bool trans_LD1RQ_zprr(DisasContext *s, arg_rprr_load *a) { - if (a->rm =3D=3D 31 || !dc_isar_feature(aa64_sve, s)) { + if (a->rm =3D=3D 31 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -5435,7 +5435,7 @@ static bool trans_LD1RQ_zprr(DisasContext *s, arg_rpr= r_load *a) =20 static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (sve_access_check(s)) { @@ -5554,7 +5554,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri= _load *a) TCGv_i64 temp, clean_addr; MemOp memop; =20 - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } if (!sve_access_check(s)) { @@ -5746,7 +5746,7 @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_s= tore *a) } switch (a->esz) { case MO_8 ... MO_64: - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } break; @@ -5783,7 +5783,7 @@ static bool trans_ST_zpri(DisasContext *s, arg_rpri_s= tore *a) } switch (a->esz) { case MO_8 ... MO_64: - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } break; @@ -6525,7 +6525,7 @@ static bool trans_STNT1_zprz(DisasContext *s, arg_ST1= _zprz *a) =20 static bool trans_PRF(DisasContext *s, arg_PRF *a) { - if (!dc_isar_feature(aa64_sve, s)) { + if (!dc_isar_feature(aa64_sme_or_sve, s)) { return false; } /* Prefetch is a nop within QEMU. */ @@ -6535,7 +6535,7 @@ static bool trans_PRF(DisasContext *s, arg_PRF *a) =20 static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a) { - if (a->rm =3D=3D 31 || !dc_isar_feature(aa64_sve, s)) { + if (a->rm =3D=3D 31 || !dc_isar_feature(aa64_sme_or_sve, s)) { return false; } /* Prefetch is a nop within QEMU. */ @@ -6568,39 +6568,39 @@ static bool trans_PRF_ns(DisasContext *s, arg_PRF_n= s *a) * In the meantime, just emit the moves. */ =20 -TRANS_FEAT(MOVPRFX, aa64_sve, do_mov_z, a->rd, a->rn) -TRANS_FEAT(MOVPRFX_m, aa64_sve, do_sel_z, a->rd, a->rn, a->rd, a->pg, a->e= sz) -TRANS_FEAT(MOVPRFX_z, aa64_sve, do_movz_zpz, a->rd, a->rn, a->pg, a->esz, = false) +TRANS_FEAT(MOVPRFX, aa64_sme_or_sve, do_mov_z, a->rd, a->rn) +TRANS_FEAT(MOVPRFX_m, aa64_sme_or_sve, do_sel_z, a->rd, a->rn, a->rd, a->p= g, a->esz) +TRANS_FEAT(MOVPRFX_z, aa64_sme_or_sve, do_movz_zpz, a->rd, a->rn, a->pg, a= ->esz, false) =20 /* * SVE2 Integer Multiply - Unpredicated */ =20 -TRANS_FEAT(MUL_zzz, aa64_sve2, gen_gvec_fn_arg_zzz, tcg_gen_gvec_mul, a) -TRANS_FEAT(SQDMULH_zzz, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_sve2_sqdm= ulh, a) +TRANS_FEAT(MUL_zzz, aa64_sme_or_sve2, gen_gvec_fn_arg_zzz, tcg_gen_gvec_mu= l, a) +TRANS_FEAT(SQDMULH_zzz, aa64_sme_or_sve2, gen_gvec_fn_arg_zzz, gen_gvec_sv= e2_sqdmulh, a) =20 static gen_helper_gvec_3 * const smulh_zzz_fns[4] =3D { gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h, gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d, }; -TRANS_FEAT(SMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SMULH_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, smulh_zzz_fns[a->esz], a, 0) =20 static gen_helper_gvec_3 * const umulh_zzz_fns[4] =3D { gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h, gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d, }; -TRANS_FEAT(UMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UMULH_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, umulh_zzz_fns[a->esz], a, 0) =20 -TRANS_FEAT(PMUL_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(PMUL_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, gen_helper_gvec_pmul_b, a, 0) =20 static gen_helper_gvec_3 * const sqrdmulh_zzz_fns[4] =3D { gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h, gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d, }; -TRANS_FEAT(SQRDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SQRDMULH_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sqrdmulh_zzz_fns[a->esz], a, 0) =20 /* @@ -6611,66 +6611,66 @@ static gen_helper_gvec_4 * const sadlp_fns[4] =3D { NULL, gen_helper_sve2_sadalp_zpzz_h, gen_helper_sve2_sadalp_zpzz_s, gen_helper_sve2_sadalp_zpzz_d, }; -TRANS_FEAT(SADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz, +TRANS_FEAT(SADALP_zpzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzz, sadlp_fns[a->esz], a, 0) =20 static gen_helper_gvec_4 * const uadlp_fns[4] =3D { NULL, gen_helper_sve2_uadalp_zpzz_h, gen_helper_sve2_uadalp_zpzz_s, gen_helper_sve2_uadalp_zpzz_d, }; -TRANS_FEAT(UADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz, +TRANS_FEAT(UADALP_zpzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zpzz, uadlp_fns[a->esz], a, 0) =20 /* * SVE2 integer unary operations (predicated) */ =20 -TRANS_FEAT(URECPE, aa64_sve2, gen_gvec_ool_arg_zpz, +TRANS_FEAT(URECPE, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, a->esz =3D=3D 2 ? gen_helper_sve2_urecpe_s : NULL, a, 0) =20 -TRANS_FEAT(URSQRTE, aa64_sve2, gen_gvec_ool_arg_zpz, +TRANS_FEAT(URSQRTE, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, a->esz =3D=3D 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 0) =20 static gen_helper_gvec_3 * const sqabs_fns[4] =3D { gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h, gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d, }; -TRANS_FEAT(SQABS, aa64_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz], a, 0) +TRANS_FEAT(SQABS, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz= ], a, 0) =20 static gen_helper_gvec_3 * const sqneg_fns[4] =3D { gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h, gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d, }; -TRANS_FEAT(SQNEG, aa64_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0) +TRANS_FEAT(SQNEG, aa64_sme_or_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz= ], a, 0) =20 -DO_ZPZZ(SQSHL, aa64_sve2, sve2_sqshl) -DO_ZPZZ(SQRSHL, aa64_sve2, sve2_sqrshl) -DO_ZPZZ(SRSHL, aa64_sve2, sve2_srshl) +DO_ZPZZ(SQSHL, aa64_sme_or_sve2, sve2_sqshl) +DO_ZPZZ(SQRSHL, aa64_sme_or_sve2, sve2_sqrshl) +DO_ZPZZ(SRSHL, aa64_sme_or_sve2, sve2_srshl) =20 -DO_ZPZZ(UQSHL, aa64_sve2, sve2_uqshl) -DO_ZPZZ(UQRSHL, aa64_sve2, sve2_uqrshl) -DO_ZPZZ(URSHL, aa64_sve2, sve2_urshl) +DO_ZPZZ(UQSHL, aa64_sme_or_sve2, sve2_uqshl) +DO_ZPZZ(UQRSHL, aa64_sme_or_sve2, sve2_uqrshl) +DO_ZPZZ(URSHL, aa64_sme_or_sve2, sve2_urshl) =20 -DO_ZPZZ(SHADD, aa64_sve2, sve2_shadd) -DO_ZPZZ(SRHADD, aa64_sve2, sve2_srhadd) -DO_ZPZZ(SHSUB, aa64_sve2, sve2_shsub) +DO_ZPZZ(SHADD, aa64_sme_or_sve2, sve2_shadd) +DO_ZPZZ(SRHADD, aa64_sme_or_sve2, sve2_srhadd) +DO_ZPZZ(SHSUB, aa64_sme_or_sve2, sve2_shsub) =20 -DO_ZPZZ(UHADD, aa64_sve2, sve2_uhadd) -DO_ZPZZ(URHADD, aa64_sve2, sve2_urhadd) -DO_ZPZZ(UHSUB, aa64_sve2, sve2_uhsub) +DO_ZPZZ(UHADD, aa64_sme_or_sve2, sve2_uhadd) +DO_ZPZZ(URHADD, aa64_sme_or_sve2, sve2_urhadd) +DO_ZPZZ(UHSUB, aa64_sme_or_sve2, sve2_uhsub) =20 -DO_ZPZZ(ADDP, aa64_sve2, sve2_addp) -DO_ZPZZ(SMAXP, aa64_sve2, sve2_smaxp) -DO_ZPZZ(UMAXP, aa64_sve2, sve2_umaxp) -DO_ZPZZ(SMINP, aa64_sve2, sve2_sminp) -DO_ZPZZ(UMINP, aa64_sve2, sve2_uminp) +DO_ZPZZ(ADDP, aa64_sme_or_sve2, sve2_addp) +DO_ZPZZ(SMAXP, aa64_sme_or_sve2, sve2_smaxp) +DO_ZPZZ(UMAXP, aa64_sme_or_sve2, sve2_umaxp) +DO_ZPZZ(SMINP, aa64_sme_or_sve2, sve2_sminp) +DO_ZPZZ(UMINP, aa64_sme_or_sve2, sve2_uminp) =20 -DO_ZPZZ(SQADD_zpzz, aa64_sve2, sve2_sqadd) -DO_ZPZZ(UQADD_zpzz, aa64_sve2, sve2_uqadd) -DO_ZPZZ(SQSUB_zpzz, aa64_sve2, sve2_sqsub) -DO_ZPZZ(UQSUB_zpzz, aa64_sve2, sve2_uqsub) -DO_ZPZZ(SUQADD, aa64_sve2, sve2_suqadd) -DO_ZPZZ(USQADD, aa64_sve2, sve2_usqadd) +DO_ZPZZ(SQADD_zpzz, aa64_sme_or_sve2, sve2_sqadd) +DO_ZPZZ(UQADD_zpzz, aa64_sme_or_sve2, sve2_uqadd) +DO_ZPZZ(SQSUB_zpzz, aa64_sme_or_sve2, sve2_sqsub) +DO_ZPZZ(UQSUB_zpzz, aa64_sme_or_sve2, sve2_uqsub) +DO_ZPZZ(SUQADD, aa64_sme_or_sve2, sve2_suqadd) +DO_ZPZZ(USQADD, aa64_sme_or_sve2, sve2_usqadd) =20 /* * SVE2 Widening Integer Arithmetic @@ -6680,95 +6680,95 @@ static gen_helper_gvec_3 * const saddl_fns[4] =3D { NULL, gen_helper_sve2_saddl_h, gen_helper_sve2_saddl_s, gen_helper_sve2_saddl_d, }; -TRANS_FEAT(SADDLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SADDLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, saddl_fns[a->esz], a, 0) -TRANS_FEAT(SADDLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SADDLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, saddl_fns[a->esz], a, 3) -TRANS_FEAT(SADDLBT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SADDLBT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, saddl_fns[a->esz], a, 2) =20 static gen_helper_gvec_3 * const ssubl_fns[4] =3D { NULL, gen_helper_sve2_ssubl_h, gen_helper_sve2_ssubl_s, gen_helper_sve2_ssubl_d, }; -TRANS_FEAT(SSUBLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SSUBLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubl_fns[a->esz], a, 0) -TRANS_FEAT(SSUBLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SSUBLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubl_fns[a->esz], a, 3) -TRANS_FEAT(SSUBLBT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SSUBLBT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubl_fns[a->esz], a, 2) -TRANS_FEAT(SSUBLTB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SSUBLTB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubl_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const sabdl_fns[4] =3D { NULL, gen_helper_sve2_sabdl_h, gen_helper_sve2_sabdl_s, gen_helper_sve2_sabdl_d, }; -TRANS_FEAT(SABDLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SABDLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sabdl_fns[a->esz], a, 0) -TRANS_FEAT(SABDLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SABDLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sabdl_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const uaddl_fns[4] =3D { NULL, gen_helper_sve2_uaddl_h, gen_helper_sve2_uaddl_s, gen_helper_sve2_uaddl_d, }; -TRANS_FEAT(UADDLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UADDLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uaddl_fns[a->esz], a, 0) -TRANS_FEAT(UADDLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UADDLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uaddl_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const usubl_fns[4] =3D { NULL, gen_helper_sve2_usubl_h, gen_helper_sve2_usubl_s, gen_helper_sve2_usubl_d, }; -TRANS_FEAT(USUBLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(USUBLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, usubl_fns[a->esz], a, 0) -TRANS_FEAT(USUBLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(USUBLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, usubl_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const uabdl_fns[4] =3D { NULL, gen_helper_sve2_uabdl_h, gen_helper_sve2_uabdl_s, gen_helper_sve2_uabdl_d, }; -TRANS_FEAT(UABDLB, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UABDLB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uabdl_fns[a->esz], a, 0) -TRANS_FEAT(UABDLT, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UABDLT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uabdl_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const sqdmull_fns[4] =3D { NULL, gen_helper_sve2_sqdmull_zzz_h, gen_helper_sve2_sqdmull_zzz_s, gen_helper_sve2_sqdmull_zzz_d, }; -TRANS_FEAT(SQDMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SQDMULLB_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sqdmull_fns[a->esz], a, 0) -TRANS_FEAT(SQDMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SQDMULLT_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sqdmull_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const smull_fns[4] =3D { NULL, gen_helper_sve2_smull_zzz_h, gen_helper_sve2_smull_zzz_s, gen_helper_sve2_smull_zzz_d, }; -TRANS_FEAT(SMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SMULLB_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, smull_fns[a->esz], a, 0) -TRANS_FEAT(SMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SMULLT_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, smull_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const umull_fns[4] =3D { NULL, gen_helper_sve2_umull_zzz_h, gen_helper_sve2_umull_zzz_s, gen_helper_sve2_umull_zzz_d, }; -TRANS_FEAT(UMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UMULLB_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, umull_fns[a->esz], a, 0) -TRANS_FEAT(UMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(UMULLT_zzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, umull_fns[a->esz], a, 3) =20 static gen_helper_gvec_3 * const eoril_fns[4] =3D { gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h, gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d, }; -TRANS_FEAT(EORBT, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 2) -TRANS_FEAT(EORTB, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 1) +TRANS_FEAT(EORBT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz= ], a, 2) +TRANS_FEAT(EORTB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz= ], a, 1) =20 static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel) { @@ -6786,36 +6786,36 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr= _esz *a, bool sel) return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel); } =20 -TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false) -TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true) +TRANS_FEAT(PMULLB, aa64_sme_or_sve2, do_trans_pmull, a, false) +TRANS_FEAT(PMULLT, aa64_sme_or_sve2, do_trans_pmull, a, true) =20 static gen_helper_gvec_3 * const saddw_fns[4] =3D { NULL, gen_helper_sve2_saddw_h, gen_helper_sve2_saddw_s, gen_helper_sve2_saddw_d, }; -TRANS_FEAT(SADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, = 0) -TRANS_FEAT(SADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, = 1) +TRANS_FEAT(SADDWB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->es= z], a, 0) +TRANS_FEAT(SADDWT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->es= z], a, 1) =20 static gen_helper_gvec_3 * const ssubw_fns[4] =3D { NULL, gen_helper_sve2_ssubw_h, gen_helper_sve2_ssubw_s, gen_helper_sve2_ssubw_d, }; -TRANS_FEAT(SSUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, = 0) -TRANS_FEAT(SSUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, = 1) +TRANS_FEAT(SSUBWB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->es= z], a, 0) +TRANS_FEAT(SSUBWT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->es= z], a, 1) =20 static gen_helper_gvec_3 * const uaddw_fns[4] =3D { NULL, gen_helper_sve2_uaddw_h, gen_helper_sve2_uaddw_s, gen_helper_sve2_uaddw_d, }; -TRANS_FEAT(UADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, = 0) -TRANS_FEAT(UADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, = 1) +TRANS_FEAT(UADDWB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->es= z], a, 0) +TRANS_FEAT(UADDWT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->es= z], a, 1) =20 static gen_helper_gvec_3 * const usubw_fns[4] =3D { NULL, gen_helper_sve2_usubw_h, gen_helper_sve2_usubw_s, gen_helper_sve2_usubw_d, }; -TRANS_FEAT(USUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, = 0) -TRANS_FEAT(USUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, = 1) +TRANS_FEAT(USUBWB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->es= z], a, 0) +TRANS_FEAT(USUBWT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->es= z], a, 1) =20 static void gen_sshll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t i= mm) { @@ -6935,8 +6935,8 @@ static const GVecGen2i sshll_ops[3] =3D { .fno =3D gen_helper_sve2_sshll_d, .vece =3D MO_64 } }; -TRANS_FEAT(SSHLLB, aa64_sve2, do_shll_tb, a, sshll_ops, false) -TRANS_FEAT(SSHLLT, aa64_sve2, do_shll_tb, a, sshll_ops, true) +TRANS_FEAT(SSHLLB, aa64_sme_or_sve2, do_shll_tb, a, sshll_ops, false) +TRANS_FEAT(SSHLLT, aa64_sme_or_sve2, do_shll_tb, a, sshll_ops, true) =20 static const TCGOpcode ushll_list[] =3D { INDEX_op_shli_vec, INDEX_op_shri_vec, 0 @@ -6958,8 +6958,8 @@ static const GVecGen2i ushll_ops[3] =3D { .fno =3D gen_helper_sve2_ushll_d, .vece =3D MO_64 }, }; -TRANS_FEAT(USHLLB, aa64_sve2, do_shll_tb, a, ushll_ops, false) -TRANS_FEAT(USHLLT, aa64_sve2, do_shll_tb, a, ushll_ops, true) +TRANS_FEAT(USHLLB, aa64_sme_or_sve2, do_shll_tb, a, ushll_ops, false) +TRANS_FEAT(USHLLT, aa64_sme_or_sve2, do_shll_tb, a, ushll_ops, true) =20 static gen_helper_gvec_3 * const bext_fns[4] =3D { gen_helper_sve2_bext_b, gen_helper_sve2_bext_h, @@ -6986,33 +6986,33 @@ static gen_helper_gvec_3 * const cadd_fns[4] =3D { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h, gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d, }; -TRANS_FEAT(CADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(CADD_rot90, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, cadd_fns[a->esz], a, 0) -TRANS_FEAT(CADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(CADD_rot270, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, cadd_fns[a->esz], a, 1) =20 static gen_helper_gvec_3 * const sqcadd_fns[4] =3D { gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h, gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d, }; -TRANS_FEAT(SQCADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SQCADD_rot90, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sqcadd_fns[a->esz], a, 0) -TRANS_FEAT(SQCADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz, +TRANS_FEAT(SQCADD_rot270, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, sqcadd_fns[a->esz], a, 1) =20 static gen_helper_gvec_4 * const sabal_fns[4] =3D { NULL, gen_helper_sve2_sabal_h, gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d, }; -TRANS_FEAT(SABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a,= 0) -TRANS_FEAT(SABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a,= 1) +TRANS_FEAT(SABALB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->e= sz], a, 0) +TRANS_FEAT(SABALT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->e= sz], a, 1) =20 static gen_helper_gvec_4 * const uabal_fns[4] =3D { NULL, gen_helper_sve2_uabal_h, gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d, }; -TRANS_FEAT(UABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a,= 0) -TRANS_FEAT(UABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a,= 1) +TRANS_FEAT(UABALB, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->e= sz], a, 0) +TRANS_FEAT(UABALT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->e= sz], a, 1) =20 static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel) { @@ -7027,18 +7027,18 @@ static bool do_adcl(DisasContext *s, arg_rrrr_esz *= a, bool sel) return gen_gvec_ool_arg_zzzz(s, fns[a->esz & 1], a, (a->esz & 2) | sel= ); } =20 -TRANS_FEAT(ADCLB, aa64_sve2, do_adcl, a, false) -TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true) +TRANS_FEAT(ADCLB, aa64_sme_or_sve2, do_adcl, a, false) +TRANS_FEAT(ADCLT, aa64_sme_or_sve2, do_adcl, a, true) =20 -TRANS_FEAT(SSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ssra, a) -TRANS_FEAT(USRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_usra, a) -TRANS_FEAT(SRSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_srsra, a) -TRANS_FEAT(URSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ursra, a) -TRANS_FEAT(SRI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sri, a) -TRANS_FEAT(SLI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sli, a) +TRANS_FEAT(SSRA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ssra, a) +TRANS_FEAT(USRA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_usra, a) +TRANS_FEAT(SRSRA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_srsra, a) +TRANS_FEAT(URSRA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ursra, a) +TRANS_FEAT(SRI, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sri, a) +TRANS_FEAT(SLI, aa64_sme_or_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sli, a) =20 -TRANS_FEAT(SABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a) -TRANS_FEAT(UABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a) +TRANS_FEAT(SABA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a) +TRANS_FEAT(UABA, aa64_sme_or_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a) =20 static bool do_narrow_extract(DisasContext *s, arg_rri_esz *a, const GVecGen2 ops[3]) @@ -7085,7 +7085,7 @@ static const GVecGen2 sqxtnb_ops[3] =3D { .fno =3D gen_helper_sve2_sqxtnb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQXTNB, aa64_sve2, do_narrow_extract, a, sqxtnb_ops) +TRANS_FEAT(SQXTNB, aa64_sme_or_sve2, do_narrow_extract, a, sqxtnb_ops) =20 static void gen_sqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { @@ -7117,7 +7117,7 @@ static const GVecGen2 sqxtnt_ops[3] =3D { .fno =3D gen_helper_sve2_sqxtnt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQXTNT, aa64_sve2, do_narrow_extract, a, sqxtnt_ops) +TRANS_FEAT(SQXTNT, aa64_sme_or_sve2, do_narrow_extract, a, sqxtnt_ops) =20 static const TCGOpcode uqxtn_list[] =3D { INDEX_op_shli_vec, INDEX_op_umin_vec, 0 @@ -7145,7 +7145,7 @@ static const GVecGen2 uqxtnb_ops[3] =3D { .fno =3D gen_helper_sve2_uqxtnb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(UQXTNB, aa64_sve2, do_narrow_extract, a, uqxtnb_ops) +TRANS_FEAT(UQXTNB, aa64_sme_or_sve2, do_narrow_extract, a, uqxtnb_ops) =20 static void gen_uqxtnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { @@ -7175,7 +7175,7 @@ static const GVecGen2 uqxtnt_ops[3] =3D { .fno =3D gen_helper_sve2_uqxtnt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(UQXTNT, aa64_sve2, do_narrow_extract, a, uqxtnt_ops) +TRANS_FEAT(UQXTNT, aa64_sme_or_sve2, do_narrow_extract, a, uqxtnt_ops) =20 static const TCGOpcode sqxtun_list[] =3D { INDEX_op_shli_vec, INDEX_op_umin_vec, INDEX_op_smax_vec, 0 @@ -7204,7 +7204,7 @@ static const GVecGen2 sqxtunb_ops[3] =3D { .fno =3D gen_helper_sve2_sqxtunb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQXTUNB, aa64_sve2, do_narrow_extract, a, sqxtunb_ops) +TRANS_FEAT(SQXTUNB, aa64_sme_or_sve2, do_narrow_extract, a, sqxtunb_ops) =20 static void gen_sqxtunt_vec(unsigned vece, TCGv_vec d, TCGv_vec n) { @@ -7235,7 +7235,7 @@ static const GVecGen2 sqxtunt_ops[3] =3D { .fno =3D gen_helper_sve2_sqxtunt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQXTUNT, aa64_sve2, do_narrow_extract, a, sqxtunt_ops) +TRANS_FEAT(SQXTUNT, aa64_sme_or_sve2, do_narrow_extract, a, sqxtunt_ops) =20 static bool do_shr_narrow(DisasContext *s, arg_rri_esz *a, const GVecGen2i ops[3]) @@ -7304,7 +7304,7 @@ static const GVecGen2i shrnb_ops[3] =3D { .fno =3D gen_helper_sve2_shrnb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SHRNB, aa64_sve2, do_shr_narrow, a, shrnb_ops) +TRANS_FEAT(SHRNB, aa64_sme_or_sve2, do_shr_narrow, a, shrnb_ops) =20 static void gen_shrnt_i64(unsigned vece, TCGv_i64 d, TCGv_i64 n, int shr) { @@ -7363,21 +7363,21 @@ static const GVecGen2i shrnt_ops[3] =3D { .fno =3D gen_helper_sve2_shrnt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SHRNT, aa64_sve2, do_shr_narrow, a, shrnt_ops) +TRANS_FEAT(SHRNT, aa64_sme_or_sve2, do_shr_narrow, a, shrnt_ops) =20 static const GVecGen2i rshrnb_ops[3] =3D { { .fno =3D gen_helper_sve2_rshrnb_h }, { .fno =3D gen_helper_sve2_rshrnb_s }, { .fno =3D gen_helper_sve2_rshrnb_d }, }; -TRANS_FEAT(RSHRNB, aa64_sve2, do_shr_narrow, a, rshrnb_ops) +TRANS_FEAT(RSHRNB, aa64_sme_or_sve2, do_shr_narrow, a, rshrnb_ops) =20 static const GVecGen2i rshrnt_ops[3] =3D { { .fno =3D gen_helper_sve2_rshrnt_h }, { .fno =3D gen_helper_sve2_rshrnt_s }, { .fno =3D gen_helper_sve2_rshrnt_d }, }; -TRANS_FEAT(RSHRNT, aa64_sve2, do_shr_narrow, a, rshrnt_ops) +TRANS_FEAT(RSHRNT, aa64_sme_or_sve2, do_shr_narrow, a, rshrnt_ops) =20 static void gen_sqshrunb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7407,7 +7407,7 @@ static const GVecGen2i sqshrunb_ops[3] =3D { .fno =3D gen_helper_sve2_sqshrunb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQSHRUNB, aa64_sve2, do_shr_narrow, a, sqshrunb_ops) +TRANS_FEAT(SQSHRUNB, aa64_sme_or_sve2, do_shr_narrow, a, sqshrunb_ops) =20 static void gen_sqshrunt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7444,21 +7444,21 @@ static const GVecGen2i sqshrunt_ops[3] =3D { .fno =3D gen_helper_sve2_sqshrunt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQSHRUNT, aa64_sve2, do_shr_narrow, a, sqshrunt_ops) +TRANS_FEAT(SQSHRUNT, aa64_sme_or_sve2, do_shr_narrow, a, sqshrunt_ops) =20 static const GVecGen2i sqrshrunb_ops[3] =3D { { .fno =3D gen_helper_sve2_sqrshrunb_h }, { .fno =3D gen_helper_sve2_sqrshrunb_s }, { .fno =3D gen_helper_sve2_sqrshrunb_d }, }; -TRANS_FEAT(SQRSHRUNB, aa64_sve2, do_shr_narrow, a, sqrshrunb_ops) +TRANS_FEAT(SQRSHRUNB, aa64_sme_or_sve2, do_shr_narrow, a, sqrshrunb_ops) =20 static const GVecGen2i sqrshrunt_ops[3] =3D { { .fno =3D gen_helper_sve2_sqrshrunt_h }, { .fno =3D gen_helper_sve2_sqrshrunt_s }, { .fno =3D gen_helper_sve2_sqrshrunt_d }, }; -TRANS_FEAT(SQRSHRUNT, aa64_sve2, do_shr_narrow, a, sqrshrunt_ops) +TRANS_FEAT(SQRSHRUNT, aa64_sme_or_sve2, do_shr_narrow, a, sqrshrunt_ops) =20 static void gen_sqshrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7491,7 +7491,7 @@ static const GVecGen2i sqshrnb_ops[3] =3D { .fno =3D gen_helper_sve2_sqshrnb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQSHRNB, aa64_sve2, do_shr_narrow, a, sqshrnb_ops) +TRANS_FEAT(SQSHRNB, aa64_sme_or_sve2, do_shr_narrow, a, sqshrnb_ops) =20 static void gen_sqshrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7529,21 +7529,21 @@ static const GVecGen2i sqshrnt_ops[3] =3D { .fno =3D gen_helper_sve2_sqshrnt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(SQSHRNT, aa64_sve2, do_shr_narrow, a, sqshrnt_ops) +TRANS_FEAT(SQSHRNT, aa64_sme_or_sve2, do_shr_narrow, a, sqshrnt_ops) =20 static const GVecGen2i sqrshrnb_ops[3] =3D { { .fno =3D gen_helper_sve2_sqrshrnb_h }, { .fno =3D gen_helper_sve2_sqrshrnb_s }, { .fno =3D gen_helper_sve2_sqrshrnb_d }, }; -TRANS_FEAT(SQRSHRNB, aa64_sve2, do_shr_narrow, a, sqrshrnb_ops) +TRANS_FEAT(SQRSHRNB, aa64_sme_or_sve2, do_shr_narrow, a, sqrshrnb_ops) =20 static const GVecGen2i sqrshrnt_ops[3] =3D { { .fno =3D gen_helper_sve2_sqrshrnt_h }, { .fno =3D gen_helper_sve2_sqrshrnt_s }, { .fno =3D gen_helper_sve2_sqrshrnt_d }, }; -TRANS_FEAT(SQRSHRNT, aa64_sve2, do_shr_narrow, a, sqrshrnt_ops) +TRANS_FEAT(SQRSHRNT, aa64_sme_or_sve2, do_shr_narrow, a, sqrshrnt_ops) =20 static void gen_uqshrnb_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7572,7 +7572,7 @@ static const GVecGen2i uqshrnb_ops[3] =3D { .fno =3D gen_helper_sve2_uqshrnb_d, .vece =3D MO_64 }, }; -TRANS_FEAT(UQSHRNB, aa64_sve2, do_shr_narrow, a, uqshrnb_ops) +TRANS_FEAT(UQSHRNB, aa64_sme_or_sve2, do_shr_narrow, a, uqshrnb_ops) =20 static void gen_uqshrnt_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t shr) @@ -7607,28 +7607,28 @@ static const GVecGen2i uqshrnt_ops[3] =3D { .fno =3D gen_helper_sve2_uqshrnt_d, .vece =3D MO_64 }, }; -TRANS_FEAT(UQSHRNT, aa64_sve2, do_shr_narrow, a, uqshrnt_ops) +TRANS_FEAT(UQSHRNT, aa64_sme_or_sve2, do_shr_narrow, a, uqshrnt_ops) =20 static const GVecGen2i uqrshrnb_ops[3] =3D { { .fno =3D gen_helper_sve2_uqrshrnb_h }, { .fno =3D gen_helper_sve2_uqrshrnb_s }, { .fno =3D gen_helper_sve2_uqrshrnb_d }, }; -TRANS_FEAT(UQRSHRNB, aa64_sve2, do_shr_narrow, a, uqrshrnb_ops) +TRANS_FEAT(UQRSHRNB, aa64_sme_or_sve2, do_shr_narrow, a, uqrshrnb_ops) =20 static const GVecGen2i uqrshrnt_ops[3] =3D { { .fno =3D gen_helper_sve2_uqrshrnt_h }, { .fno =3D gen_helper_sve2_uqrshrnt_s }, { .fno =3D gen_helper_sve2_uqrshrnt_d }, }; -TRANS_FEAT(UQRSHRNT, aa64_sve2, do_shr_narrow, a, uqrshrnt_ops) +TRANS_FEAT(UQRSHRNT, aa64_sme_or_sve2, do_shr_narrow, a, uqrshrnt_ops) =20 #define DO_SVE2_ZZZ_NARROW(NAME, name) \ static gen_helper_gvec_3 * const name##_fns[4] =3D { = \ NULL, gen_helper_sve2_##name##_h, \ gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \ }; \ - TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzz, \ + TRANS_FEAT(NAME, aa64_sme_or_sve2, gen_gvec_ool_arg_zzz, = \ name##_fns[a->esz], a, 0) =20 DO_SVE2_ZZZ_NARROW(ADDHNB, addhnb) @@ -7660,11 +7660,11 @@ TRANS_FEAT_NONSTREAMING(HISTCNT, aa64_sve2, gen_gve= c_ool_arg_zpzz, TRANS_FEAT_NONSTREAMING(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz, a->esz =3D=3D 0 ? gen_helper_sve2_histseg : NULL, = a, 0) =20 -DO_ZPZZ_FP(FADDP, aa64_sve2, sve2_faddp_zpzz) -DO_ZPZZ_FP(FMAXNMP, aa64_sve2, sve2_fmaxnmp_zpzz) -DO_ZPZZ_FP(FMINNMP, aa64_sve2, sve2_fminnmp_zpzz) -DO_ZPZZ_FP(FMAXP, aa64_sve2, sve2_fmaxp_zpzz) -DO_ZPZZ_FP(FMINP, aa64_sve2, sve2_fminp_zpzz) +DO_ZPZZ_FP(FADDP, aa64_sme_or_sve2, sve2_faddp_zpzz) +DO_ZPZZ_FP(FMAXNMP, aa64_sme_or_sve2, sve2_fmaxnmp_zpzz) +DO_ZPZZ_FP(FMINNMP, aa64_sme_or_sve2, sve2_fminnmp_zpzz) +DO_ZPZZ_FP(FMAXP, aa64_sme_or_sve2, sve2_fmaxp_zpzz) +DO_ZPZZ_FP(FMINP, aa64_sme_or_sve2, sve2_fminp_zpzz) =20 static bool do_fmmla(DisasContext *s, arg_rrrr_esz *a, gen_helper_gvec_4_ptr *fn) @@ -7690,92 +7690,92 @@ static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[]= =3D { NULL, gen_helper_sve2_sqdmlal_zzzw_h, gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d, }; -TRANS_FEAT(SQDMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLALB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlal_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(SQDMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLALT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlal_zzzw_fns[a->esz], a, 3) -TRANS_FEAT(SQDMLALBT, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLALBT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlal_zzzw_fns[a->esz], a, 2) =20 static gen_helper_gvec_4 * const sqdmlsl_zzzw_fns[] =3D { NULL, gen_helper_sve2_sqdmlsl_zzzw_h, gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d, }; -TRANS_FEAT(SQDMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLSLB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlsl_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(SQDMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLSLT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlsl_zzzw_fns[a->esz], a, 3) -TRANS_FEAT(SQDMLSLBT, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQDMLSLBT, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqdmlsl_zzzw_fns[a->esz], a, 2) =20 static gen_helper_gvec_4 * const sqrdmlah_fns[] =3D { gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h, gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d, }; -TRANS_FEAT(SQRDMLAH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQRDMLAH_zzzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqrdmlah_fns[a->esz], a, 0) =20 static gen_helper_gvec_4 * const sqrdmlsh_fns[] =3D { gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h, gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d, }; -TRANS_FEAT(SQRDMLSH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SQRDMLSH_zzzz, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, sqrdmlsh_fns[a->esz], a, 0) =20 static gen_helper_gvec_4 * const smlal_zzzw_fns[] =3D { NULL, gen_helper_sve2_smlal_zzzw_h, gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d, }; -TRANS_FEAT(SMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SMLALB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, smlal_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(SMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SMLALT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, smlal_zzzw_fns[a->esz], a, 1) =20 static gen_helper_gvec_4 * const umlal_zzzw_fns[] =3D { NULL, gen_helper_sve2_umlal_zzzw_h, gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d, }; -TRANS_FEAT(UMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(UMLALB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, umlal_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(UMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(UMLALT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, umlal_zzzw_fns[a->esz], a, 1) =20 static gen_helper_gvec_4 * const smlsl_zzzw_fns[] =3D { NULL, gen_helper_sve2_smlsl_zzzw_h, gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d, }; -TRANS_FEAT(SMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SMLSLB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, smlsl_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(SMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(SMLSLT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, smlsl_zzzw_fns[a->esz], a, 1) =20 static gen_helper_gvec_4 * const umlsl_zzzw_fns[] =3D { NULL, gen_helper_sve2_umlsl_zzzw_h, gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d, }; -TRANS_FEAT(UMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(UMLSLB_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, umlsl_zzzw_fns[a->esz], a, 0) -TRANS_FEAT(UMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(UMLSLT_zzzw, aa64_sme_or_sve2, gen_gvec_ool_arg_zzzz, umlsl_zzzw_fns[a->esz], a, 1) =20 static gen_helper_gvec_4 * const cmla_fns[] =3D { gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h, gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d, }; -TRANS_FEAT(CMLA_zzzz, aa64_sve2, gen_gvec_ool_zzzz, +TRANS_FEAT(CMLA_zzzz, aa64_sme_or_sve2, gen_gvec_ool_zzzz, cmla_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) =20 static gen_helper_gvec_4 * const cdot_fns[] =3D { NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d }; -TRANS_FEAT(CDOT_zzzz, aa64_sve2, gen_gvec_ool_zzzz, +TRANS_FEAT(CDOT_zzzz, aa64_sme_or_sve2, gen_gvec_ool_zzzz, cdot_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) =20 static gen_helper_gvec_4 * const sqrdcmlah_fns[] =3D { gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h, gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d, }; -TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz, +TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sme_or_sve2, gen_gvec_ool_zzzz, sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) =20 TRANS_FEAT(USDOT_zzzz_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, @@ -7813,30 +7813,30 @@ static bool trans_RAX1(DisasContext *s, arg_RAX1 *a) return gen_gvec_fn_arg_zzz(s, gen_gvec_rax1, a); } =20 -TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTNT_sh, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64) -TRANS_FEAT(FCVTNT_ds, aa64_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTNT_ds, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64) =20 TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvtnt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 -TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTLT_hs, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtlt_hs, a, 0, FPST_A64) -TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(FCVTLT_sd, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtlt_sd, a, 0, FPST_A64) =20 -TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a, +TRANS_FEAT(FCVTX_ds, aa64_sme_or_sve2, do_frint_mode, a, FPROUNDING_ODD, gen_helper_sve_fcvt_ds) -TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a, +TRANS_FEAT(FCVTXNT_ds, aa64_sme_or_sve2, do_frint_mode, a, FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds) =20 static gen_helper_gvec_3_ptr * const flogb_fns[] =3D { NULL, gen_helper_flogb_h, gen_helper_flogb_s, gen_helper_flogb_d }; -TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz], +TRANS_FEAT(FLOGB, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->es= z], a, 0, a->esz =3D=3D MO_16 ? FPST_A64_F16 : FPST_A64) =20 static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool= sel) @@ -7846,10 +7846,10 @@ static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr= _esz *a, bool sub, bool sel) (sel << 1) | sub, tcg_env); } =20 -TRANS_FEAT(FMLALB_zzzw, aa64_sve2, do_FMLAL_zzzw, a, false, false) -TRANS_FEAT(FMLALT_zzzw, aa64_sve2, do_FMLAL_zzzw, a, false, true) -TRANS_FEAT(FMLSLB_zzzw, aa64_sve2, do_FMLAL_zzzw, a, true, false) -TRANS_FEAT(FMLSLT_zzzw, aa64_sve2, do_FMLAL_zzzw, a, true, true) +TRANS_FEAT(FMLALB_zzzw, aa64_sme_or_sve2, do_FMLAL_zzzw, a, false, false) +TRANS_FEAT(FMLALT_zzzw, aa64_sme_or_sve2, do_FMLAL_zzzw, a, false, true) +TRANS_FEAT(FMLSLB_zzzw, aa64_sme_or_sve2, do_FMLAL_zzzw, a, true, false) +TRANS_FEAT(FMLSLT_zzzw, aa64_sme_or_sve2, do_FMLAL_zzzw, a, true, true) =20 static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool= sel) { @@ -7858,10 +7858,10 @@ static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr= _esz *a, bool sub, bool sel) (a->index << 3) | (sel << 1) | sub, tcg_env); } =20 -TRANS_FEAT(FMLALB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, false) -TRANS_FEAT(FMLALT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, true) -TRANS_FEAT(FMLSLB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, false) -TRANS_FEAT(FMLSLT_zzxw, aa64_sve2, do_FMLAL_zzxw, a, true, true) +TRANS_FEAT(FMLALB_zzxw, aa64_sme_or_sve2, do_FMLAL_zzxw, a, false, false) +TRANS_FEAT(FMLALT_zzxw, aa64_sme_or_sve2, do_FMLAL_zzxw, a, false, true) +TRANS_FEAT(FMLSLB_zzxw, aa64_sme_or_sve2, do_FMLAL_zzxw, a, true, false) +TRANS_FEAT(FMLSLT_zzxw, aa64_sme_or_sve2, do_FMLAL_zzxw, a, true, true) =20 TRANS_FEAT_NONSTREAMING(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, gen_helper_gvec_smmla_b, a, 0) --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497431; cv=none; d=zohomail.com; s=zohoarc; b=S7lsBgNphtg0S31Li/EK0YG7YZKZBcuuFT6N+AVv9LOl4ZeWmjIizyIR1+y6VJEq+46H8GR+E0eRa6sDWynGxbgPV8YNmujKYPeMhvMkpyF6lhtFGmQ11yqMi515MXnH7NauMT4WehsiX9QJihZMJLnEPyEY6AXlbUrExqy5Wuk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497431; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=f1C6jaV9rVPZltyegP5pK+FRYZqGt2KdDwkRHXIZajo=; b=f+eJkKp8J4IM8+cVeWbNj6hErzzbP+rTv1e6zaPZD38xhsslvcAye33lxSEqDAbyd49vICmaTeTl97W1diXn+xzFe8TNZ/PJqNGBDqC5fWixZeBYmegJDAYyqq6wULIVeJAuiL45YVM2ozEinlCC1SBqlQcIL9P4jeMgI3/Ripc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497431980761.5561225273622; Thu, 19 Feb 2026 02:37:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mj-0007MD-Rp; Thu, 19 Feb 2026 05:34:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1Mf-0007IC-W5 for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:34 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MX-00064g-2S for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:28 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-43621bf67ceso533049f8f.2 for ; Thu, 19 Feb 2026 02:34:18 -0800 (PST) Received: from lanath.. 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Currently we assume that it is only set for FEAT_SVE. Update the feature checks: * we rename the existing feature check function to sve_sme_i8mm to indicate that it is true for either SVE or SME I8MM * we add a new check function for FEAT_SVE && FEAT_I8MM (giving it the sve_i8mm name that the old function used to have) * the instructions which are (SVE || SME) && I8MM need their checks updating to sve_sme_i8mm: these are SUDOT, USDOT * instructions which are SVE && I8MM (i.e. really SVE-only) stay unchanged with sve_i8mm: these are SMMLA, USMMLA, UMMLA Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260202133353.2231685-12-peter.maydell@linaro.org --- target/arm/cpu-features.h | 8 +++++++- target/arm/tcg/translate-sve.c | 6 +++--- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 6935ef2f78..40eb8cef17 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1464,7 +1464,8 @@ static inline bool isar_feature_aa64_sve2_sm4(const A= RMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, SM4) !=3D 0; } =20 -static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) +/* Note that this is true if either SVE or SME are implemented with I8MM */ +static inline bool isar_feature_aa64_sme_sve_i8mm(const ARMISARegisters *i= d) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, I8MM) !=3D 0; } @@ -1557,6 +1558,11 @@ static inline bool isar_feature_aa64_sme2_f64f64(con= st ARMISARegisters *id) return isar_feature_aa64_sme2(id) && isar_feature_aa64_sme_f64f64(id); } =20 +static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id) +{ + return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 44eda7b07d..53d35f6de9 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -3758,9 +3758,9 @@ TRANS_FEAT(UDOT_zzxw_4s, aa64_sme_or_sve, gen_gvec_oo= l_arg_zzxz, TRANS_FEAT(UDOT_zzxw_4d, aa64_sme_or_sve, gen_gvec_ool_arg_zzxz, gen_helper_gvec_udot_idx_4h, a) =20 -TRANS_FEAT(SUDOT_zzxw_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(SUDOT_zzxw_4s, aa64_sme_sve_i8mm, gen_gvec_ool_arg_zzxz, gen_helper_gvec_sudot_idx_4b, a) -TRANS_FEAT(USDOT_zzxw_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz, +TRANS_FEAT(USDOT_zzxw_4s, aa64_sme_sve_i8mm, gen_gvec_ool_arg_zzxz, gen_helper_gvec_usdot_idx_4b, a) =20 TRANS_FEAT(SDOT_zzxw_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzxz, @@ -7778,7 +7778,7 @@ static gen_helper_gvec_4 * const sqrdcmlah_fns[] =3D { TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sme_or_sve2, gen_gvec_ool_zzzz, sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot) =20 -TRANS_FEAT(USDOT_zzzz_4s, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz, +TRANS_FEAT(USDOT_zzzz_4s, aa64_sme_sve_i8mm, gen_gvec_ool_arg_zzzz, gen_helper_gvec_usdot_4b, a, 0) =20 TRANS_FEAT(SDOT_zzzz_2s, aa64_sme2_or_sve2p1, gen_gvec_ool_arg_zzzz, --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497258; x=1772102058; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=axcHvld9isZneOoWqSbrQxic/Tw4drSb949eZLUQ3O8=; b=MdJHfmh+GaSerBopOYbFhngb2YdY6LjRMSajhEJz8FfexQ4rd/RXGCOTm9MUANJr0E cBqP0rNnqBf4jk1Ilda/vUYMFPeA94gqAl6nhm9oUIwaB5Od6NFym4WaH8fGB5+xjkdb tFK0WGnQ1l6LlUhOfpFErvkTNDnsETl0xGcR7QQVVcrG4UhA/AY8kccSzDAy6itWa+n1 0b6e3Ug9O6gRRrZhFn3RX4icelUJOedsC6y7uVXzZ37Vtfldq0gKt+nWJkeAWXaImRh6 Jn95yJwZdiY2jcDcRTe8j+p/8k3jpma7HIIeKjFrpqRYfhMSUBgMUVrsYPoVPJogBn43 Uc9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497258; x=1772102058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=axcHvld9isZneOoWqSbrQxic/Tw4drSb949eZLUQ3O8=; b=j1b7BM93AAs4/HXgeAFmHSeEHJVGQdUNAqGG8+MWZjTOIO0lOMpvdVoNPmBE2MdvM9 VzyUEuDgJbjmDuyeAYkJfNb5uSyROpXiTzL1HEIUC6isSebHAlyJGQPpEV3iSjoJrMNn yMyqaEAVUxmkGcS/8dGWhOSxVE0I7Lk1cbGESq5HCAkkxJWH0vhqgZroFCG8fpZfAS+T 7sIP7Eho21INLLyMb5rc2RGHClRB3qhWHledGxZxCyqeESszthfyaHtD5artmFOw0PF1 3CCMbiAsR+BNmJGsMVI54hMINmn2+X0n8Z75sBrlycvq/MyIHjGLst8DQ5zxpyaqjWs3 ND7A== X-Gm-Message-State: AOJu0YyojvI/klchFYHe0TZ2rnMB0cRhCogRqVv7VOJ9HYArpmv8lp/8 42idyk1eqc8rh4gzrzGyResS6ifCfaBwg8PFFad5dkh9QuD/vj7VeiTcwDd3tqwdDEeJARnhmtW jCmDk X-Gm-Gg: AZuq6aKxQWQbbvLF/p2ncI0/UWOKI/S/Ku/0e9TxIsDTwtxRL/GbohyoM2XzYzaTf82 a+pme3JMEuLcRiaruQjTCSKbUGsklIHkzDPxyfu1jXMMXoOPOvGIXr7x1Ttsn+LDzsXPooJ5q50 M4iOkvqqJRq9vmh7O9TGbbdhLBZjDk0hFpEuP1lOvaah3h3DCY4Dm70sbZ2xVdcUP7g8cReZag6 JrmupuPKOusITxLrmF6iG1cwG9zkERa7kWb8YfzfJ1uS7DSGR06Wib+CeJKzieqQgt+M+32ieDl wpywNMKJWQP9FBXBn0vx9wvao5CsytMnwZ+Rfv/rAAw2Bn8Bw8e3xh4PSjN5L73D47GsvjYp1g4 bQu7zfKIWPxs1obQYMPFbQV+coTxOb9elwiThi9/T3Qb4OB/4ZIx6UHn8Se3jPd+vGfbUmQSZQ4 0KOCH5Qc2tP3tE/wj9W8qtbijB/q2SEe/Q22xV9kBTn6iyULiXear7D1u6QO/3EiF8rxCGBUx+e yfQA+J8cyuLHSaryDPVG4RYXus/L0NXEDmgbgRIDQ== X-Received: by 2002:a05:600c:4eca:b0:47e:e87f:4bba with SMTP id 5b1f17b1804b1-48379bfc3bamr286819495e9.29.1771497258311; Thu, 19 Feb 2026 02:34:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/32] target/arm/tcg: Correct SVE/SME BF16 checks Date: Thu, 19 Feb 2026 10:33:45 +0000 Message-ID: <20260219103405.3793357-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497373591154100 Content-Type: text/plain; charset="utf-8" As with I8MM, the BF16 field of ID_AA64ZFR0_EL1 is set when the CPU implements FEAT_BF16 and either FEAT_SVE or FEAT_SME, so we need to have separate checks for "(SVE || SME) && BF16" and "SVE && BF16". Follow the same pattern as with I8MM: * aa64_sve_sme_bf16 means (SVE || SME) && BF16 * aa64_sve_bf16 means (SVE && BF16) BFMMLA is the only SVE BF16 insn that isn't in SME. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260202133353.2231685-13-peter.maydell@linaro.org --- target/arm/cpu-features.h | 7 ++++++- target/arm/tcg/translate-sve.c | 16 ++++++++-------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 40eb8cef17..83db3fd950 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -1449,7 +1449,7 @@ static inline bool isar_feature_aa64_sve2_bitperm(con= st ARMISARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BITPERM) !=3D 0; } =20 -static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) +static inline bool isar_feature_aa64_sme_sve_bf16(const ARMISARegisters *i= d) { return FIELD_EX64_IDREG(id, ID_AA64ZFR0, BFLOAT16) !=3D 0; } @@ -1563,6 +1563,11 @@ static inline bool isar_feature_aa64_sve_i8mm(const = ARMISARegisters *id) return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id); } =20 +static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id) +{ + return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_bf16(id); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 53d35f6de9..956ddee123 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -4430,7 +4430,7 @@ TRANS_FEAT(FCVT_sh, aa64_sme_or_sve, gen_gvec_fpst_ar= g_zpz, TRANS_FEAT(FCVT_hs, aa64_sme_or_sve, gen_gvec_fpst_arg_zpz, gen_helper_sve_fcvt_hs, a, 0, FPST_A64_F16) =20 -TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(BFCVT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 @@ -7818,7 +7818,7 @@ TRANS_FEAT(FCVTNT_sh, aa64_sme_or_sve2, gen_gvec_fpst= _arg_zpz, TRANS_FEAT(FCVTNT_ds, aa64_sme_or_sve2, gen_gvec_fpst_arg_zpz, gen_helper_sve2_fcvtnt_ds, a, 0, FPST_A64) =20 -TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz, +TRANS_FEAT(BFCVTNT, aa64_sme_sve_bf16, gen_gvec_fpst_arg_zpz, gen_helper_sve_bfcvtnt, a, 0, s->fpcr_ah ? FPST_AH : FPST_A64) =20 @@ -7875,9 +7875,9 @@ TRANS_FEAT(FDOT_zzzz, aa64_sme2_or_sve2p1, gen_gvec_e= nv_arg_zzzz, TRANS_FEAT(FDOT_zzxz, aa64_sme2_or_sve2p1, gen_gvec_env_arg_zzxz, gen_helper_sme2_fdot_idx_h, a) =20 -TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_env_arg_zzzz, +TRANS_FEAT(BFDOT_zzzz, aa64_sme_sve_bf16, gen_gvec_env_arg_zzzz, gen_helper_gvec_bfdot, a, 0) -TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_env_arg_zzxz, +TRANS_FEAT(BFDOT_zzxz, aa64_sme_sve_bf16, gen_gvec_env_arg_zzxz, gen_helper_gvec_bfdot_idx, a) =20 TRANS_FEAT_NONSTREAMING(BFMMLA, aa64_sve_bf16, gen_gvec_env_arg_zzzz, @@ -7890,8 +7890,8 @@ static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_= esz *a, bool sel) s->fpcr_ah ? FPST_AH : FPST_A64); } =20 -TRANS_FEAT(BFMLALB_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, false) -TRANS_FEAT(BFMLALT_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, true) +TRANS_FEAT(BFMLALB_zzzw, aa64_sme_sve_bf16, do_BFMLAL_zzzw, a, false) +TRANS_FEAT(BFMLALT_zzzw, aa64_sme_sve_bf16, do_BFMLAL_zzzw, a, true) =20 static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel) { @@ -7901,8 +7901,8 @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_= esz *a, bool sel) s->fpcr_ah ? FPST_AH : FPST_A64); } =20 -TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false) -TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true) +TRANS_FEAT(BFMLALB_zzxw, aa64_sme_sve_bf16, do_BFMLAL_zzxw, a, false) +TRANS_FEAT(BFMLALT_zzxw, aa64_sme_sve_bf16, do_BFMLAL_zzxw, a, true) =20 static bool do_BFMLSL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel) { --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497282; cv=none; d=zohomail.com; s=zohoarc; b=XbMNE7ZVjjJmYgFNE3kgQcwrotwzKP5wDeGDIDVfbESZOlrbNJRs5+r0/kairOQjwaAU3KCPE9p8wu8CGnXiw8TwgBHcp+04tQ1FFGFWtK5g9Id682uKYTlM09jk5ltJoez+0KEKyYoU/LjLT/YtykhooCncixFctOu4efxgLTg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497282; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ohMJCnxM63AagK7D0igHWCyyjIwb/ZPxENrfJ55pD20=; b=bBLh2ahot0VJG83wGfk4cwk5GuKWP9tvyCofUi9n76XBFIXAVEHM39bxY4a8da79gpagoKyOt05lF/Ut+QYQQ/COT7/a0ax5q/WxMfSdtn4/XQJHZQfCjlgOvKv0idylOa9B5Ambs0TNcE908uG0X54Z3saSwzxIMUUT95t7gaM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497282672921.5792754269526; Thu, 19 Feb 2026 02:34:42 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Me-0007Dz-AK; Thu, 19 Feb 2026 05:34:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MX-00078d-Ow for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:26 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MT-00064s-TB for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:25 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-483a2338616so1762605e9.0 for ; Thu, 19 Feb 2026 02:34:20 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497259; x=1772102059; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ohMJCnxM63AagK7D0igHWCyyjIwb/ZPxENrfJ55pD20=; b=Qcr0RFWic02MHJFpcOnFSVYqryyaAM/A4cb3sJ75n8xBScomDbIu3haOCj2R3PU60r kEPCUAZzNWKRJdrqxJ/XRX/wVYFWH90QzKcV0bt6YdKbWZxHsdakseOugufoi8RXlgwy f6iuZ5hYw2tpkyA3FFoshq0EyIdyDAy1YVlp0GcuwHt/IYyQ92l7lIK0Ch1PfDPhBGnK /OYPkfZdFvx2as9D/iC0583OB+GDZafR0z5n2tvuuvYr1vrJ49+yru+bn+oRPopQpAkI iQrCw6rlyACTMFw9TVeSPB5Lr2ImsNARfxg607Z2TXDc/nrlKyd8mfTKESp0Qy6RLY39 IzLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497259; x=1772102059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ohMJCnxM63AagK7D0igHWCyyjIwb/ZPxENrfJ55pD20=; b=qW2huDTzZXcYtvVLkfdsrAnWQKcsqgcTDOL9geJaYTwRNNGSEQJ191BnpYjhkEmqdv rvYLOJmrIKRGjjf1uhWOpU7W12/F2GCJtCy7EuB/XnAlDP40Gc6oc7QXHZ6CtC5xh3J+ OCSx1u1oZZnbgVVSYJL/AfrsbxkfLd3OZ4dV8QS5eykeJqtxDgWqyyUsa5K/vHraHThx JI5TnzPorc+85c3TcVMIfE2lzoD6noxtRTf9wcHzeKq7DOKvNTfxNHHqs4gQZ+PJ+E+y sTAV3gn+XGeRBhi/cAHRPHNt/yWhALMImJJ5Ydo5lC33f2XSvJVt8DuOxq06GKA996xA C9kQ== X-Gm-Message-State: AOJu0YwrFKFsK3hurl72arggauessGWiUhT1sizfG7WXbek0OAYN/Tur tV8RCKHJdoZYpBimNalsg8yRc5I8w1Y/Ooc+Qu4uNjx6DoirIrbRWCt9iHmd4KZvLV3uSdUh8Vs RAtV/ X-Gm-Gg: AZuq6aIG40l+G5VjpwWeeDwjJgGdF6WvHa7SseCx/4Ze0pd73wtHZ5WJ/WDnyvBWEMH QyX9SsMUOm594w8dB5c2pzcc9CRUngPk5o+DC3lf9JBKoGWsmIG7D3bF4ZKrLLbimGsSiDlcVHU hBmfXN0RgYIqxy5rG2BjyP6YI+uXXAqhPAESL4lP9Ul1KgBjBI+ZGWYiRhSd4S35XXuiSKMc2Rd cPtKt4AfjLFY+Y795uNOYbNyU0VCZNzxiNDz1tAr/X0uKqCJ61rR0CWus8PIrRZ5WP4XKyPxSGQ L7wnvVo38/ipn8ePFh2wz9E2W54MBjmO/5iHv8NMKm7bX86lJ/gt4E1PoNZA8LrsUvK0I4hApv7 B956BCmV/w6s7ZDhAExnq31A1pvE50ENBcbpAfDb/jo0WjGeRLUej3Usak1Zkz+AMuREUa+brwx 8VEyAFf/rYIXjY6W/VDxiRPxZJFuLaYMg+jX19S8PpmYAD/7GB+2ILhpMIeXRoQv5exH9numkBD tzfdohs40OaG9vdRyI1/Int+9OPEms= X-Received: by 2002:a05:600c:198a:b0:480:20f1:7aa6 with SMTP id 5b1f17b1804b1-48398b5e372mr75019275e9.21.1771497259153; Thu, 19 Feb 2026 02:34:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/32] target/arm: Don't squash all ID_AA64ZFR0_EL1 fields for non-SVE Date: Thu, 19 Feb 2026 10:33:46 +0000 Message-ID: <20260219103405.3793357-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497284160158500 Content-Type: text/plain; charset="utf-8" The ID register ID_AA64ZFR0_EL1's fields are not all for SVE exclusive features; some are also used to describe SME on an SME-only CPU: SVE-only fields: * F64MM, F32MM, F16MM, SM4, B16B16, SVEVer Fields used for SVE and SME (in some cases there is also a field for SME in ID_AA64SMFR0_EL1, but it is just a "present or absent" single bit flag and the ZFR0 field then tells you what level of support is present): * I8MM, SHA3, BF16, BitPerm, EltPerm, AES Currently we zero the whole ID_AA64ZFR0_EL1 register in arm_cpu_sve_finalize() if SVE is not present, which wipes also the fields we need for SME. Only clear the fields which are SVE-specific here, and clear the rest in arm_cpu_sme_finalize() if we have neither SME nor SVE. This requires us to update our ID_AA64ZFR0 field definitions to match the rev M.a.a Arm ARM, as the F16MM SVE-only field is not one we had a definition for previously. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260202133353.2231685-14-peter.maydell@linaro.org --- target/arm/cpu-features.h | 2 ++ target/arm/cpu64.c | 16 ++++++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 83db3fd950..b683c9551a 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -368,12 +368,14 @@ FIELD(ID_AA64DFR0, HPMN0, 60, 4) =20 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) FIELD(ID_AA64ZFR0, AES, 4, 4) +FIELD(ID_AA64ZFR0, ELTPERM, 12, 4) FIELD(ID_AA64ZFR0, BITPERM, 16, 4) FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) FIELD(ID_AA64ZFR0, B16B16, 24, 4) FIELD(ID_AA64ZFR0, SHA3, 32, 4) FIELD(ID_AA64ZFR0, SM4, 40, 4) FIELD(ID_AA64ZFR0, I8MM, 44, 4) +FIELD(ID_AA64ZFR0, F16MM, 48, 4) FIELD(ID_AA64ZFR0, F32MM, 52, 4) FIELD(ID_AA64ZFR0, F64MM, 56, 4) =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4d316f5a71..b2be8c9fba 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -136,9 +136,17 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) if (!cpu_isar_feature(aa64_sve, cpu)) { /* * SVE is disabled and so are all vector lengths. Good. - * Disable all SVE extensions as well. + * Disable all SVE extensions as well. Note that some ZFR0 + * fields are used also by SME so must not be wiped in + * an SME-no-SVE config. We will clear the rest in + * arm_cpu_sme_finalize() if necessary. */ - SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F64MM, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F32MM, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, F16MM, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, SM4, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, B16B16, 0); + FIELD_DP64_IDREG(&cpu->isar, ID_AA64ZFR0, SVEVER, 0); return; } =20 @@ -338,6 +346,10 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) if (vq_map =3D=3D 0) { if (!cpu_isar_feature(aa64_sme, cpu)) { SET_IDREG(&cpu->isar, ID_AA64SMFR0, 0); + if (!cpu_isar_feature(aa64_sve, cpu)) { + /* This clears the "SVE or SME" fields in ZFR0 */ + SET_IDREG(&cpu->isar, ID_AA64ZFR0, 0); + } return; } =20 --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497296; cv=none; d=zohomail.com; s=zohoarc; b=N8sI8DpbHL8RGFFJqQXasbAj5lE1GUmymwiTiEVkVFGq3+mr282o5MjKOBsr21YARVpbsUaLEn0G9ttTA58jOIMQmIdKcgDpQ2RW5l4w2szU5vdHYVv7F7WAP2Qd0OX3DUuWTiOGFcSDZn+ySWiHgmG0S80/d5Kj8KsLOZ5SOho= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497296; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=idmqccAZl4RtO4Py9HrXUW9aAh/kXz8DSEMvWdQRhy4=; b=CycP9wbp+py+vZEIGVrtB7FpTgiNDUX7xDxjoLMxrDYtQVlyftObL+illlCyR9mhk6LrGsjPtxv5m+pAK7Fc3sjUvMLvq53nr1eGd7e08kr3H0/VB2jI0dfA9dvcRxkJ9dCixkkMC+ZCdNFQZ1aQUKIPw97oejSfUMYADNCaRuA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497296358707.9709856243409; Thu, 19 Feb 2026 02:34:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mj-0007ME-SP; Thu, 19 Feb 2026 05:34:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MZ-0007AT-5t for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:27 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MV-00064w-2H for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:26 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4837634de51so3849345e9.1 for ; Thu, 19 Feb 2026 02:34:21 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497260; x=1772102060; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=idmqccAZl4RtO4Py9HrXUW9aAh/kXz8DSEMvWdQRhy4=; b=PGRZYbrL2yepq+NH3JxXYlerFjp5ZoY1kO7SDW5UhbYdu19QpTUpCmCXjHenDpW7Oa 9VBYlNmv7Oz8HtIxjM93mmpvsI6dVttVW1xcf4I3p/1duqYa/0DY2xewswudMXKNTxM9 aktVR/T4/8ytfiKMuUehQoXrJ7IkgjwFzUjUmMIVmQx5G6JfBKfBZKFCxwlL57q3YJPH yDmpU8V3B9No6RoE1tRMbBnya43WWjFJOYlBX5K+JB0o7ZwtGZaf08UIIKlTSjIdFh+y 6XMNCrewvR+t2qMOOFPf2C3tgkJP7Sc5fcrVrUzwN2O541Wz37vMOS1OlkES9mi3xKJu X58Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497260; x=1772102060; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=idmqccAZl4RtO4Py9HrXUW9aAh/kXz8DSEMvWdQRhy4=; b=wLhrXaRoAgMp3TACY9Z8RvhNX1+UTss/a4cZ5rQ4utg4lGFoImhg3E/KllDkIlsLva 2MEtSn/e1mihG2QDwXvHSJR0EtghDc+U22GqLXkksuRg83hihdko2D7fyIzQC+Sdyy9w ZEQ5b6v2nASpX1JJXAr8aKnqCzBoBB9Jv6c/dUCF8VljOPE801Hjibx39RhZrLBWRG8e 7U6NglxoMiKisEKL7Kto3htyu7N8WnFLeiaV7VzwyWROX/AyStGW4tBd3+CKZe7tJAfl C4S6lJDMjc/qDE6XYAPxj6wHpq1txj4sXinr8NkW8Suq97oBpJmKAWd4bQFaRaIDIXnE Vtlg== X-Gm-Message-State: AOJu0YxqXptHk3afTdenax8vd7TuzEZpsJiiwLh5K8TJp8ykop2ZZsEJ uepXGpHwP3DritW5sAuUzDq4mEoEqOSNvRKAbbYdk/KIsGOrVpldNGnB0m2ZexOCSJPyE118D42 grEhc X-Gm-Gg: AZuq6aJ8s2ir0/ClL3QY/O+qY0354TXcblVgCig+DGgZ2RRgCk6juhL9YXXHsdMXhxu 9NU2YfuggEyDwVoJEz8q9Ud4VCr2xYcAR7dwT5NFxx686s/KUxOZeIxVsv/vj7gU3GckimVR/+O WmfmcgdVPiE19YxBpyybh2SkzbxuOfFxiN96vypuep/R1LfFsUrufsZ/YVSuh3jjKaWrBOwFd6l sE394aFsB/DyXjjD6FHlQPRPy4G27mOs2C16dnhruCET+XGplIQNLkKNXMN9mfbDRtzLqbs6A39 8uETAymovzolSJr4TRsRBkg3cWpoVkCLXVeY5IPKDIZUzYnUmpQhhf65GbjN1gbz2xER/9CnjaW kyPPRXLUmhqvwdYXUdu569A2oSFDs9OepGuxEZCVSS1LXn/9m7oMZ58eP5dlVJCDwSZ7eQJ/ud2 WM/s94ZDC1yEuknGhc0rxI1D3/n3DAyzU+zlsiaJ42Ygmg3kidNqiEhw5sDjoCOv9KTMcIxJbLS gbo1liU+8pV7nNp3uawry6sQtnaDdw= X-Received: by 2002:a05:600c:314b:b0:482:eec4:772 with SMTP id 5b1f17b1804b1-483710962c5mr280635165e9.32.1771497259969; Thu, 19 Feb 2026 02:34:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/32] target/arm: Squash FEAT_SME_FA64 if FEAT_SVE is not present Date: Thu, 19 Feb 2026 10:33:47 +0000 Message-ID: <20260219103405.3793357-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497298628154100 Content-Type: text/plain; charset="utf-8" FEAT_SME_FA64 allows Streaming SVE code to access the whole SVE instruction set; it requires FEAT_SVE to be present. If we have a CPU with SME but not SVE, squash the FA64 bit in arm_cpu_sme_finalize(). This doesn't have any effect at the moment because we don't let the user create an SME-without-SVE CPU, but we are about to lift that restriction. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20260202133353.2231685-15-peter.maydell@linaro.org --- target/arm/cpu64.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index b2be8c9fba..dec430c48b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -388,6 +388,11 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) /* SME2 or better */ FIELD_DP64_IDREG(&cpu->isar, ID_AA64PFR1, SME, 2); } + + if (!cpu_isar_feature(aa64_sve, cpu)) { + /* FEAT_SME_FA64 requires SVE, not just SME */ + FIELD_DP64_IDREG(&cpu->isar, ID_AA64SMFR0, FA64, 0); + } } =20 static bool cpu_arm_get_sme(Object *obj, Error **errp) --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497353; cv=none; d=zohomail.com; s=zohoarc; b=Tzsu9BieQegYx/+uLpbAZyTwjt6xa12tKQXpQIJtRn3UsIVrJcJI+CiRJz1v/hN0sYPLG5FK7Q+TTp1fNVKr1xVUcs1BcrvghcfismvC/cMJ9S4mFiwouSibFp+mPDaA/k8+sTro6ZxxXuv9YP+mJfW7o12JAfPiccbxIE1tcyk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497353; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=UzzJHiP4Ww50cmlpD5s1nBOWMQn5ZNOxnnLL7RIFj0M=; b=VDUUzqJEvgybGlRuofTKCj8Dsa4FV5yY0f5gWYHOXiGpNUZphSL7faD4ZhuDkVKGix9EYobgzeRExjPCZ8ip2Zkl39cj1yyKm5YCu0TmkdPyRlFldCSGVGZtIgwmGbjbC06DXMOybfc9idVkSOGbsEZv61iBhmGLMNw9aKxYoEk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497353940238.62548396410557; Thu, 19 Feb 2026 02:35:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mh-0007JQ-4t; Thu, 19 Feb 2026 05:34:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MZ-0007B5-BJ for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:27 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MW-00065J-PS for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:27 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4836f363d0dso6899345e9.3 for ; Thu, 19 Feb 2026 02:34:21 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497261; x=1772102061; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UzzJHiP4Ww50cmlpD5s1nBOWMQn5ZNOxnnLL7RIFj0M=; b=zWNhNe3OgheL1ChsjxqgCT/oRi/DR/i9biBiYST/TG7UFNYn7mg0j0cU8fXa5x2pF2 3sDM/sw/r1xchUI50Mr2cljIYwU+A9m1Kjq32DPjFZ9nlS5iM/ic9T9J1+tFUxm7gZ4b R7z+Zx075e+AWXdjQjnYMF6Runz8b99WL4zAf/zfHwXvlZN/8MVm3gMO1WYpzs3orTAo rtmOhSvA5lCisFFw1zBSwUl4yjKcFqRDOxDL9YuKvC4xWXeaR6+4YhUfa/QLFESt7mMQ aUl0hzTGPijmezISEna40ayvIGFqu1qDuonuDzYa1vse+fRCifR//oDlRePfA3drCho7 KQPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497261; x=1772102061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=UzzJHiP4Ww50cmlpD5s1nBOWMQn5ZNOxnnLL7RIFj0M=; b=cE0pXtBZ8U1BCcqvd9ksZLcD1YdZDh44jXSnoQKZsye75YKiemXPtr2TeBroOddKEc kaHAdxRrY4bDoU0HL15wF7HWyq6emD1rxb+A1hjNQQwlBTN1mOxSTRwSAZJaMhc7SwFf E6IWKSlKJ3o4dsG0UPZUW5U+pn4pdUkNeTsl+p0G3BXTmqajFS+W2buFRpZbX//ioPdb pAsmQnOvUOyeFvCAFtOcyOYRtWLHnYIXrYsFOBv4zHZ8D9iIInoo5n5JYwIVxplt+ira QC+2d33PDjaKyCm3FEuy0VHDBUGMYPHxYUzw4a4dCUEnXVzJ27HhEnX1WhnsXxPDvUux Jq+A== X-Gm-Message-State: AOJu0YwmKvNkapdGLpsRitf+ZAzmAzSu4xTY0nVLiZGxyvFNVwrk9we+ WMsk1EeCnAKMdNr9EM9vX4Umrb9mo40HuKlSpgCRdOoJEyTyM443qB5jZ0KTBoKyaoWhGGLmsBi ztZ70 X-Gm-Gg: AZuq6aIvaAf6JEWNTDhXkXrsHiIKDGgB0ANsym2h9shBHmEMjzCZrFe82pNHHC7zxuu Ug9ZiyOkVNAUHN1Upfpjoh242filS3yzktIvI+q1BLiGUJzzqopGuv9IcIRQFc6V/xxKxoZ0J8B fTXkoYi80OREoFm2Gkh6APnahL/cQG2zGj/OfT2dYK5yv6ROKMXETzO4l08hkE0mHO+/jEPAGwg E7mKq281h6GYmQhyd4y21P7r11UV//tQxsWCYFNoRPyz9jw2QyLWyR7grENLYl/4amnZkaxNx9I HJCnoXMMDcnjneaOhvBIPB0G2c5DlKm2dFJGQcDzAycBrTCwjI38T0bQZvshwTILfCpBxHyDa4g 6rtx5r0F58Xf0Tgsm2aAr5rp6uMlU4hWsXMHTh2gUSPqGFnXQGMaFFY3JtXyO3Klb+8RKT2OhwW YYRXhWxhA+4KlVhYPpbn2xB8AvDJazYU478fDdiWQoA5yAcpyKRuBbmb3Xk2gKZObQLa9IFGXJS d7YOS/yk85zzp4531WwZCUFiFt+KqU= X-Received: by 2002:a05:600c:8b84:b0:483:4bbc:89ea with SMTP id 5b1f17b1804b1-48379c42db1mr290411605e9.37.1771497260764; Thu, 19 Feb 2026 02:34:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/32] target/arm: Permit configurations with SME but not SVE Date: Thu, 19 Feb 2026 10:33:48 +0000 Message-ID: <20260219103405.3793357-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497354319158500 In commit f7767ca30179 ("target/arm: Disable SME if SVE is disabled") we added code that forces SME to be disabled if SVE is disabled. This was something we did in the run-up to a release to avoid an assertion failure in smcr_write() if the user disabled SVE on the 'max' CPU without disabling SME also. Now that we have corrected the code so that it doesn't assert in an SME-without-SVE setup, we can let users select it. This effectively reverts f7767ca30179. Note that this now means that command lines like "-cpu max,sve=3Doff" which used to turn off SME and SVE will now give you a CPU with SME but not SVE. This is permitted by our loose "max can always give you extra stuff" rules, but may be unexpected to users. Mention this in the CPU property documentation. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Peter Maydell Message-id: 20260202133353.2231685-16-peter.maydell@linaro.org --- docs/system/arm/cpu-features.rst | 10 ++++++++-- target/arm/cpu.c | 10 ---------- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 024119449c..3db1f19401 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -323,12 +323,18 @@ SVE CPU Property Parsing Semantics enable SVE2). There are not generally any lower-level controls for disabling specific SVE sub-features. =20 + 11) Disabling SVE does not automatically disable SME. If you want to + disable both you must use ``sve=3Doff,sme=3Doff``. In particular, + for the ``max`` CPU, ``sve=3Doff`` alone will give you a CPU with + SME only (and which therefore still has the SVE vector registers). + Most users will want to disable both at once. + SVE CPU Property Examples ------------------------- =20 - 1) Disable SVE:: + 1) Disable SVE and SME:: =20 - $ qemu-system-aarch64 -M virt -cpu max,sve=3Doff + $ qemu-system-aarch64 -M virt -cpu max,sve=3Doff,sme=3Doff =20 2) Implicitly enable all vector lengths for the ``max`` CPU type:: =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7542444b18..10f8280eef 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1580,16 +1580,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **= errp) return; } =20 - /* - * FEAT_SME is not architecturally dependent on FEAT_SVE (unless - * FEAT_SME_FA64 is present). However our implementation currently - * assumes it, so if the user asked for sve=3Doff then turn off SM= E also. - * (KVM doesn't currently support SME at all.) - */ - if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve,= cpu)) { - object_property_set_bool(OBJECT(cpu), "sme", false, &error_abo= rt); - } - arm_cpu_sme_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497467; cv=none; d=zohomail.com; s=zohoarc; b=OJ3TfRARXACsxRHHY0RbImjQQED9RhMxGvZDn7e4X7KLUg4/VrnDlG+Cdxp1F+3bDkJ+E/SJytwP78AjAVuu4bJsCB6olFFrcAxqpOqYXAWzeHjgnJQVpf48hSCSAE/PCyaw+A0XYfRlU+jHvGTqUSYwgBGsKGM0aDRmU/6+Mks= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497467; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=M31IU/68Ir/y3L9oSFn7MeWv0qnqpBZFnVrNA/xiATA=; b=j97zE/gzDZcztr4K339yK2S6ssNJGepJSz51rJRclaW4x1nSkGxdLPvGxX+/5qi4sqvibQxm93WfkrinhYGyWIrMpVBhi5G8fRT8EUY4B4qX5jU/KBD32p74ZKxfwrypSvc1kvK2RYOXxFzPUk5QxpK8AiYs5bxsAM1A6oR72Vc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497466997742.9002385342365; Thu, 19 Feb 2026 02:37:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mi-0007Jk-00; Thu, 19 Feb 2026 05:34:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1Mg-0007IO-23 for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:34 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MX-00065k-2R for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:28 -0500 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-483487335c2so7589175e9.2 for ; Thu, 19 Feb 2026 02:34:22 -0800 (PST) Received: from lanath.. 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This fixes usb-audio on mac99,via=3Dpmu with MacOS 9. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3274 Signed-off-by: BALATON Zoltan Tested-by: Elisey Konstantinov Message-id: 20260212185425.2F854596A29@zero.eik.bme.hu [PMM: added brief comment, tweaked commit message] Signed-off-by: Peter Maydell Reviewed-by: Peter Maydell --- hw/usb/hcd-ohci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index c7e9c71903..1aeed9286f 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -1246,6 +1246,10 @@ static void ohci_frame_boundary(void *opaque) hcca.frame =3D cpu_to_le16(ohci->frame_number); /* When the HC updates frame number, set pad to 0. Ref OHCI Spec 4.4.1= */ hcca.pad =3D 0; + /* FrameNumberOverflow happens when bit 15 of frame number changes */ + if (ohci->frame_number =3D=3D 0x8000 || ohci->frame_number =3D=3D 0) { + ohci_set_interrupt(ohci, OHCI_INTR_FNO); + } =20 if (ohci->done_count =3D=3D 0 && !(ohci->intr_status & OHCI_INTR_WD)) { if (!ohci->done) { --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497353; cv=none; d=zohomail.com; s=zohoarc; b=bFdvEWJ4BZmBbna3igw6mIpSrC43szEu3AC8rdJqQjTURolOCX5bT0YrHDK5BDjwU7pc1pxj56D/QXnOR5zCYReEDegU2nZ0z0fKAV83DUCMsXwdePWfp+3bn+sVxMrGEpcWR165VJfgmoxZnSt5sP50rSikurTDsobTB8mKub0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497353; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=2piwW7x7xa0tuREr3tdoIgKbLpIosN9QvpX7ZD6Am+E=; b=k89hAwijPAbGWhMJPUDyPSeyWkgdetWa7o8Q8elq2YtTyu3wvYM+G2pSLr5BG96bN7cHDhMwauncINqruVTdNFeV7LeLjLI8ns7pJwITQe5vaQYBqyK1LDHRiQoqLyUpUdcOjhtTe/7ZMWRl2OFCH7vLIbyLcqf0dRDyY9ZutDw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497353867864.4993523553321; Thu, 19 Feb 2026 02:35:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mh-0007Je-P5; Thu, 19 Feb 2026 05:34:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1MZ-0007Ai-84 for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:27 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MX-000664-0z for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:26 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-48375f1defeso5741295e9.0 for ; Thu, 19 Feb 2026 02:34:23 -0800 (PST) Received: from lanath.. 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Thu, 19 Feb 2026 02:34:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/32] whpx: remove duplicate include Date: Thu, 19 Feb 2026 10:33:50 +0000 Message-ID: <20260219103405.3793357-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497355278154100 Content-Type: text/plain; charset="utf-8" From: Osama Abdelkader cpu.h is included twice Signed-off-by: Osama Abdelkader Message-id: 20260217204754.101223-1-osama.abdelkader@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/whpx/whpx-all.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 36c5e30a03..b0602266af 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -27,7 +27,6 @@ #include =20 #include "syndrome.h" -#include "cpu.h" #include "target/arm/cpregs.h" #include "internals.h" =20 --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497398; cv=none; d=zohomail.com; s=zohoarc; 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Thu, 19 Feb 2026 02:34:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/32] whpx: fix FP register loop Date: Thu, 19 Feb 2026 10:33:51 +0000 Message-ID: <20260219103405.3793357-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497400475158500 From: Osama Abdelkader In whpx_get_registers and whpx_set_registers the loops over FP registers were using whpx_reg_match[i].reg instead of whpx_fpreg_match[i].reg Signed-off-by: Osama Abdelkader Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Mohamed Mediouni > Message-id: 20260217210805.104427-1-osama.abdelkader@gmail.com Signed-off-by: Peter Maydell --- target/arm/whpx/whpx-all.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index b0602266af..40ada2d5b6 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -554,7 +554,7 @@ void whpx_get_registers(CPUState *cpu) } =20 for (i =3D 0; i < ARRAY_SIZE(whpx_fpreg_match); i++) { - whpx_get_reg(cpu, whpx_reg_match[i].reg, &val); + whpx_get_reg(cpu, whpx_fpreg_match[i].reg, &val); memcpy((char *)env + whpx_fpreg_match[i].offset, &val, sizeof(val.= Reg128)); } =20 @@ -605,7 +605,7 @@ void whpx_set_registers(CPUState *cpu, int level) =20 for (i =3D 0; i < ARRAY_SIZE(whpx_fpreg_match); i++) { memcpy(&val.Reg128, (char *)env + whpx_fpreg_match[i].offset, size= of(val.Reg128)); - whpx_set_reg(cpu, whpx_reg_match[i].reg, val); + whpx_set_reg(cpu, whpx_fpreg_match[i].reg, val); } =20 clean_whv_register_value(&val); --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497403; cv=none; d=zohomail.com; s=zohoarc; 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497265; x=1772102065; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mfCDIFdRUVutujvkRIe+imF240VJMOiVp5FL3KJ7/zY=; b=BQjQjrI4OSfNR56Dg4Uc9yzTxPwwIMzsPCLqackCJGTo6ghZZhhBbbDC807Gs7aI9j 3woIk3UnesIh9aRKgkCKu3WqapS6RjvhmsQU9PDSO8ql+rd75gREQowRu6VKnp1DiNp2 Yzzk5Q76IX3unD/YHH4AKR/LpfVWURjxm5hD/7heXRbaYOHh6YuHEuNOn4aKvZc1UIoJ R8B5kxACBsZGlzuz19rkoirnS2pg3H2nyQ392ufI69A4r19n77TPbRCl37j9qmbsNAKb Mtof98Vo8OOh1y2JHoL/bFf0L9wBz80LYP9WRj5lfLA0mJinWmBH1fyVXuGJqNTvo01Q d/vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497265; x=1772102065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=mfCDIFdRUVutujvkRIe+imF240VJMOiVp5FL3KJ7/zY=; b=DmbkqSVRXeltc6gi1+103+8CrP/jvKzjqAGWXAO4Dd4bLU2+iHzhL7fkCOZo4hWnjX 5VEDbuJyuIWIwgGDPbsjC61WTju/FtC17+p0XlQ51lJr/YmRB1k/nu4f97AAoIugTqI3 uIY5kdcxjO+xnkdNetV8SzG+JaCL93/2Juak63niJnCA1nZw3ivTNJjH6qU5+8DqNztQ 66QQnYd863gN4yLT3eV3vBAAe0YJ+GK/F73eHyGsy6MPZj6W4f7DUMKvLdVkaGxXvrmJ tGnnJz/5MajeTc1R+lvEKFx79to3WtYdKszc3KcC4pjeCo8bRWrQVAYYKQDlk32R4fYZ gAiQ== X-Gm-Message-State: AOJu0Yw3A7c8ZL+obTGlndyBgcNXsq28wpNvguAa9c4Tt+jogusxjr84 yvGwy5Ng3guMIIM8jpGX0cTNoOFszFxdfXsMHGW/6N23c+YtnG8a9FQpqUg9V5K4Z/stnCnTfc3 YRH2Q X-Gm-Gg: AZuq6aK5atIrbqhAaTpdDKLPKnDEhkNILOA62SaoiVoajeKVKuOfOmktW7ySaVSRXHi PTYbkaFJkrbWODHie9Xn7ejqz7cT4NIQgmVQEVl8iO2sIum5aY1x9pDk+ZBHJfDSlHAIrqs+GUb BnPRc4P4fZWivJT776S+UYF5obfoSUq15yjj3ztHQQYphwQ1FkbfFuGowKZFO4rltAVFXbPDOEN JAUaqfdHII806w5xlwrRtW2LFJHxXnwcpnioujsu8VwXiOH1b6CUY5lo0b0AFhBt1i4w4jEljYd 0dTFLZOW4qaB2MqiVfDH334iynPq9aLAt/eDFfXDgle4BYOh1WauCNPlyY3HHvO2J9XG6xCgUW4 UikMyARKEc9a2TOKbEDisrfCXR4Y4nKCX0PEnijs4wg5xg8baho13coGoV1BPBFukRTgeP7IDSU dhmxYDPXRQ0cmXo6ysyvw3cXE850rSy+q+NJNjmj4NyvxS/dChs2IO5xDO3ODiQ/BfRsz1XIbDE RYKcls1g/AmyW+kj+PxsrtBYJ/+tJs= X-Received: by 2002:a05:600c:620d:b0:480:3bba:1cac with SMTP id 5b1f17b1804b1-48371043046mr306802735e9.6.1771497264194; Thu, 19 Feb 2026 02:34:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/32] target/arm: Move TCG-specific code out of debug_helper.c Date: Thu, 19 Feb 2026 10:33:52 +0000 Message-ID: <20260219103405.3793357-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497406126154100 Content-Type: text/plain; charset="utf-8" The target/arm/debug_helper.c file has some code which we need for non-TCG accelerators, but quite a lot which is guarded by a CONFIG_TCG ifdef. Move all this TCG-only code out to a new file target/arm/tcg/debug.c. In particular all the code requiring access to the TCG helper function prototypes is in the moved code, so we can drop the use of tcg/helper.h from debug_helper.c. Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/debug_helper.c | 769 --------------------- target/arm/{debug_helper.c =3D> tcg/debug.c} | 544 +-------------- target/arm/tcg/meson.build | 2 + 3 files changed, 4 insertions(+), 1311 deletions(-) copy target/arm/{debug_helper.c =3D> tcg/debug.c} (53%) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 579516e154..352c8e5c8e 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -14,775 +14,6 @@ #include "exec/watchpoint.h" #include "system/tcg.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - -#ifdef CONFIG_TCG -/* Return the Exception Level targeted by debug exceptions. */ -static int arm_debug_target_el(CPUARMState *env) -{ - bool secure =3D arm_is_secure(env); - bool route_to_el2 =3D false; - - if (arm_feature(env, ARM_FEATURE_M)) { - return 1; - } - - if (arm_is_el2_enabled(env)) { - route_to_el2 =3D env->cp15.hcr_el2 & HCR_TGE || - env->cp15.mdcr_el2 & MDCR_TDE; - } - - if (route_to_el2) { - return 2; - } else if (arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && secure) { - return 3; - } else { - return 1; - } -} - -/* - * Raise an exception to the debug target el. - * Modify syndrome to indicate when origin and target EL are the same. - */ -G_NORETURN static void -raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome) -{ - int debug_el =3D arm_debug_target_el(env); - int cur_el =3D arm_current_el(env); - - /* - * If singlestep is targeting a lower EL than the current one, then - * DisasContext.ss_active must be false and we can never get here. - * Similarly for watchpoint and breakpoint matches. - */ - assert(debug_el >=3D cur_el); - syndrome |=3D (debug_el =3D=3D cur_el) << ARM_EL_EC_SHIFT; - raise_exception(env, excp, syndrome, debug_el); -} - -/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ -static bool aa64_generate_debug_exceptions(CPUARMState *env) -{ - int cur_el =3D arm_current_el(env); - int debug_el; - - if (cur_el =3D=3D 3) { - return false; - } - - /* MDCR_EL3.SDD disables debug events from Secure state */ - if (arm_is_secure_below_el3(env) - && extract32(env->cp15.mdcr_el3, 16, 1)) { - return false; - } - - /* - * Same EL to same EL debug exceptions need MDSCR_KDE enabled - * while not masking the (D)ebug bit in DAIF. - */ - debug_el =3D arm_debug_target_el(env); - - if (cur_el =3D=3D debug_el) { - return extract32(env->cp15.mdscr_el1, 13, 1) - && !(env->daif & PSTATE_D); - } - - /* Otherwise the debug target needs to be a higher EL */ - return debug_el > cur_el; -} - -static bool aa32_generate_debug_exceptions(CPUARMState *env) -{ - int el =3D arm_current_el(env); - - if (el =3D=3D 0 && arm_el_is_aa64(env, 1)) { - return aa64_generate_debug_exceptions(env); - } - - if (arm_is_secure(env)) { - int spd; - - if (el =3D=3D 0 && (env->cp15.sder & 1)) { - /* - * SDER.SUIDEN means debug exceptions from Secure EL0 - * are always enabled. Otherwise they are controlled by - * SDCR.SPD like those from other Secure ELs. - */ - return true; - } - - spd =3D extract32(env->cp15.mdcr_el3, 14, 2); - switch (spd) { - case 1: - /* SPD =3D=3D 0b01 is reserved, but behaves as 0b00. */ - case 0: - /* - * For 0b00 we return true if external secure invasive debug - * is enabled. On real hardware this is controlled by external - * signals to the core. QEMU always permits debug, and behaves - * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. - */ - return true; - case 2: - return false; - case 3: - return true; - } - } - - return el !=3D 2; -} - -/* - * Return true if debugging exceptions are currently enabled. - * This corresponds to what in ARM ARM pseudocode would be - * if UsingAArch32() then - * return AArch32.GenerateDebugExceptions() - * else - * return AArch64.GenerateDebugExceptions() - * We choose to push the if() down into this function for clarity, - * since the pseudocode has it at all callsites except for the one in - * CheckSoftwareStep(), where it is elided because both branches would - * always return the same value. - */ -bool arm_generate_debug_exceptions(CPUARMState *env) -{ - if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) { - return false; - } - if (is_a64(env)) { - return aa64_generate_debug_exceptions(env); - } else { - return aa32_generate_debug_exceptions(env); - } -} - -/* - * Is single-stepping active? (Note that the "is EL_D AArch64?" check - * implicitly means this always returns false in pre-v8 CPUs.) - */ -bool arm_singlestep_active(CPUARMState *env) -{ - return extract32(env->cp15.mdscr_el1, 0, 1) - && arm_el_is_aa64(env, arm_debug_target_el(env)) - && arm_generate_debug_exceptions(env); -} - -/* Return true if the linked breakpoint entry lbn passes its checks */ -static bool linked_bp_matches(ARMCPU *cpu, int lbn) -{ - CPUARMState *env =3D &cpu->env; - uint64_t bcr =3D env->cp15.dbgbcr[lbn]; - int brps =3D arm_num_brps(cpu); - int ctx_cmps =3D arm_num_ctx_cmps(cpu); - int bt; - uint32_t contextidr; - uint64_t hcr_el2; - - /* - * Links to unimplemented or non-context aware breakpoints are - * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or - * as if linked to an UNKNOWN context-aware breakpoint (in which - * case DBGWCR_EL1.LBN must indicate that breakpoint). - * We choose the former. - */ - if (lbn >=3D brps || lbn < (brps - ctx_cmps)) { - return false; - } - - bcr =3D env->cp15.dbgbcr[lbn]; - - if (extract64(bcr, 0, 1) =3D=3D 0) { - /* Linked breakpoint disabled : generate no events */ - return false; - } - - bt =3D extract64(bcr, 20, 4); - hcr_el2 =3D arm_hcr_el2_eff(env); - - switch (bt) { - case 3: /* linked context ID match */ - switch (arm_current_el(env)) { - default: - /* Context matches never fire in AArch64 EL3 */ - return false; - case 2: - if (!(hcr_el2 & HCR_E2H)) { - /* Context matches never fire in EL2 without E2H enabled. = */ - return false; - } - contextidr =3D env->cp15.contextidr_el[2]; - break; - case 1: - contextidr =3D env->cp15.contextidr_el[1]; - break; - case 0: - if ((hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)= ) { - contextidr =3D env->cp15.contextidr_el[2]; - } else { - contextidr =3D env->cp15.contextidr_el[1]; - } - break; - } - break; - - case 7: /* linked contextidr_el1 match */ - contextidr =3D env->cp15.contextidr_el[1]; - break; - case 13: /* linked contextidr_el2 match */ - contextidr =3D env->cp15.contextidr_el[2]; - break; - - case 9: /* linked VMID match (reserved if no EL2) */ - case 11: /* linked context ID and VMID match (reserved if no EL2) */ - case 15: /* linked full context ID match */ - default: - /* - * Links to Unlinked context breakpoints must generate no - * events; we choose to do the same for reserved values too. - */ - return false; - } - - /* - * We match the whole register even if this is AArch32 using the - * short descriptor format (in which case it holds both PROCID and ASI= D), - * since we don't implement the optional v7 context ID masking. - */ - return contextidr =3D=3D (uint32_t)env->cp15.dbgbvr[lbn]; -} - -static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) -{ - CPUARMState *env =3D &cpu->env; - uint64_t cr; - int pac, hmc, ssc, wt, lbn; - /* - * Note that for watchpoints the check is against the CPU security - * state, not the S/NS attribute on the offending data access. - */ - bool is_secure =3D arm_is_secure(env); - int access_el =3D arm_current_el(env); - - if (is_wp) { - CPUWatchpoint *wp =3D env->cpu_watchpoint[n]; - - if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) { - return false; - } - cr =3D env->cp15.dbgwcr[n]; - if (wp->hitattrs.user) { - /* - * The LDRT/STRT/LDT/STT "unprivileged access" instructions sh= ould - * match watchpoints as if they were accesses done at EL0, eve= n if - * the CPU is at EL1 or higher. - */ - access_el =3D 0; - } - } else { - uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; - - if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc !=3D pc)= { - return false; - } - cr =3D env->cp15.dbgbcr[n]; - } - /* - * The WATCHPOINT_HIT flag guarantees us that the watchpoint is - * enabled and that the address and access type match; for breakpoints - * we know the address matched; check the remaining fields, including - * linked breakpoints. We rely on WCR and BCR having the same layout - * for the LBN, SSC, HMC, PAC/PMC and is-linked fields. - * Note that some combinations of {PAC, HMC, SSC} are reserved and - * must act either like some valid combination or as if the watchpoint - * were disabled. We choose the former, and use this together with - * the fact that EL3 must always be Secure and EL2 must always be - * Non-Secure to simplify the code slightly compared to the full - * table in the ARM ARM. - */ - pac =3D FIELD_EX64(cr, DBGWCR, PAC); - hmc =3D FIELD_EX64(cr, DBGWCR, HMC); - ssc =3D FIELD_EX64(cr, DBGWCR, SSC); - - switch (ssc) { - case 0: - break; - case 1: - case 3: - if (is_secure) { - return false; - } - break; - case 2: - if (!is_secure) { - return false; - } - break; - } - - switch (access_el) { - case 3: - case 2: - if (!hmc) { - return false; - } - break; - case 1: - if (extract32(pac, 0, 1) =3D=3D 0) { - return false; - } - break; - case 0: - if (extract32(pac, 1, 1) =3D=3D 0) { - return false; - } - break; - default: - g_assert_not_reached(); - } - - wt =3D FIELD_EX64(cr, DBGWCR, WT); - lbn =3D FIELD_EX64(cr, DBGWCR, LBN); - - if (wt && !linked_bp_matches(cpu, lbn)) { - return false; - } - - return true; -} - -static bool check_watchpoints(ARMCPU *cpu) -{ - CPUARMState *env =3D &cpu->env; - int n; - - /* - * If watchpoints are disabled globally or we can't take debug - * exceptions here then watchpoint firings are ignored. - */ - if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 - || !arm_generate_debug_exceptions(env)) { - return false; - } - - for (n =3D 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) { - if (bp_wp_matches(cpu, n, true)) { - return true; - } - } - return false; -} - -bool arm_debug_check_breakpoint(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - vaddr pc; - int n; - - /* - * If breakpoints are disabled globally or we can't take debug - * exceptions here then breakpoint firings are ignored. - */ - if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 - || !arm_generate_debug_exceptions(env)) { - return false; - } - - /* - * Single-step exceptions have priority over breakpoint exceptions. - * If single-step state is active-pending, suppress the bp. - */ - if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { - return false; - } - - /* - * PC alignment faults have priority over breakpoint exceptions. - */ - pc =3D is_a64(env) ? env->pc : env->regs[15]; - if ((is_a64(env) || !env->thumb) && (pc & 3) !=3D 0) { - return false; - } - - /* - * Instruction aborts have priority over breakpoint exceptions. - * TODO: We would need to look up the page for PC and verify that - * it is present and executable. - */ - - for (n =3D 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { - if (bp_wp_matches(cpu, n, false)) { - return true; - } - } - return false; -} - -bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) -{ - /* - * Called by core code when a CPU watchpoint fires; need to check if t= his - * is also an architectural watchpoint match. - */ - ARMCPU *cpu =3D ARM_CPU(cs); - - return check_watchpoints(cpu); -} - -/* - * Return the FSR value for a debug exception (watchpoint, hardware - * breakpoint or BKPT insn) targeting the specified exception level. - */ -static uint32_t arm_debug_exception_fsr(CPUARMState *env) -{ - ARMMMUFaultInfo fi =3D { .type =3D ARMFault_Debug }; - int target_el =3D arm_debug_target_el(env); - bool using_lpae; - - if (arm_feature(env, ARM_FEATURE_M)) { - using_lpae =3D false; - } else if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el)) { - using_lpae =3D true; - } else if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V8)) { - using_lpae =3D true; - } else if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { - using_lpae =3D true; - } else { - using_lpae =3D false; - } - - if (using_lpae) { - return arm_fi_to_lfsc(&fi); - } else { - return arm_fi_to_sfsc(&fi); - } -} - -void arm_debug_excp_handler(CPUState *cs) -{ - /* - * Called by core code when a watchpoint or breakpoint fires; - * need to check which one and raise the appropriate exception. - */ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - CPUWatchpoint *wp_hit =3D cs->watchpoint_hit; - - if (wp_hit) { - if (wp_hit->flags & BP_CPU) { - bool wnr =3D (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) !=3D 0; - - cs->watchpoint_hit =3D NULL; - - env->exception.fsr =3D arm_debug_exception_fsr(env); - env->exception.vaddress =3D wp_hit->hitaddr; - raise_exception_debug(env, EXCP_DATA_ABORT, - syn_watchpoint(0, 0, wnr)); - } - } else { - uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; - - /* - * (1) GDB breakpoints should be handled first. - * (2) Do not raise a CPU exception if no CPU breakpoint has fired, - * since singlestep is also done by generating a debug internal - * exception. - */ - if (cpu_breakpoint_test(cs, pc, BP_GDB) - || !cpu_breakpoint_test(cs, pc, BP_CPU)) { - return; - } - - env->exception.fsr =3D arm_debug_exception_fsr(env); - /* - * FAR is UNKNOWN: clear vaddress to avoid potentially exposing - * values to the guest that it shouldn't be able to see at its - * exception/security level. - */ - env->exception.vaddress =3D 0; - raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); - } -} - -/* - * Raise an EXCP_BKPT with the specified syndrome register value, - * targeting the correct exception level for debug exceptions. - */ -void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) -{ - int debug_el =3D arm_debug_target_el(env); - int cur_el =3D arm_current_el(env); - - /* FSR will only be used if the debug target EL is AArch32. */ - env->exception.fsr =3D arm_debug_exception_fsr(env); - /* - * FAR is UNKNOWN: clear vaddress to avoid potentially exposing - * values to the guest that it shouldn't be able to see at its - * exception/security level. - */ - env->exception.vaddress =3D 0; - /* - * Other kinds of architectural debug exception are ignored if - * they target an exception level below the current one (in QEMU - * this is checked by arm_generate_debug_exceptions()). Breakpoint - * instructions are special because they always generate an exception - * to somewhere: if they can't go to the configured debug exception - * level they are taken to the current exception level. - */ - if (debug_el < cur_el) { - debug_el =3D cur_el; - } - raise_exception(env, EXCP_BKPT, syndrome, debug_el); -} - -void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) -{ - raise_exception_debug(env, EXCP_UDEF, syndrome); -} - -void hw_watchpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - vaddr len =3D 0; - vaddr wvr =3D env->cp15.dbgwvr[n]; - uint64_t wcr =3D env->cp15.dbgwcr[n]; - int mask; - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; - - if (env->cpu_watchpoint[n]) { - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); - env->cpu_watchpoint[n] =3D NULL; - } - - if (!FIELD_EX64(wcr, DBGWCR, E)) { - /* E bit clear : watchpoint disabled */ - return; - } - - switch (FIELD_EX64(wcr, DBGWCR, LSC)) { - case 0: - /* LSC 00 is reserved and must behave as if the wp is disabled */ - return; - case 1: - flags |=3D BP_MEM_READ; - break; - case 2: - flags |=3D BP_MEM_WRITE; - break; - case 3: - flags |=3D BP_MEM_ACCESS; - break; - } - - /* - * Attempts to use both MASK and BAS fields simultaneously are - * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, - * thus generating a watchpoint for every byte in the masked region. - */ - mask =3D FIELD_EX64(wcr, DBGWCR, MASK); - if (mask =3D=3D 1 || mask =3D=3D 2) { - /* - * Reserved values of MASK; we must act as if the mask value was - * some non-reserved value, or as if the watchpoint were disabled. - * We choose the latter. - */ - return; - } else if (mask) { - /* Watchpoint covers an aligned area up to 2GB in size */ - len =3D 1ULL << mask; - /* - * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE - * whether the watchpoint fires when the unmasked bits match; we o= pt - * to generate the exceptions. - */ - wvr &=3D ~(len - 1); - } else { - /* Watchpoint covers bytes defined by the byte address select bits= */ - int bas =3D FIELD_EX64(wcr, DBGWCR, BAS); - int basstart; - - if (extract64(wvr, 2, 1)) { - /* - * Deprecated case of an only 4-aligned address. BAS[7:4] are - * ignored, and BAS[3:0] define which bytes to watch. - */ - bas &=3D 0xf; - } - - if (bas =3D=3D 0) { - /* This must act as if the watchpoint is disabled */ - return; - } - - /* - * The BAS bits are supposed to be programmed to indicate a contig= uous - * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er - * we fire for each byte in the word/doubleword addressed by the W= VR. - * We choose to ignore any non-zero bits after the first range of = 1s. - */ - basstart =3D ctz32(bas); - len =3D cto32(bas >> basstart); - wvr +=3D basstart; - } - - cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, - &env->cpu_watchpoint[n]); -} - -void hw_watchpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* - * Completely clear out existing QEMU watchpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { - hw_watchpoint_update(cpu, i); - } -} - -void hw_breakpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - uint64_t bvr =3D env->cp15.dbgbvr[n]; - uint64_t bcr =3D env->cp15.dbgbcr[n]; - vaddr addr; - int bt; - int flags =3D BP_CPU; - - if (env->cpu_breakpoint[n]) { - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); - env->cpu_breakpoint[n] =3D NULL; - } - - if (!extract64(bcr, 0, 1)) { - /* E bit clear : watchpoint disabled */ - return; - } - - bt =3D extract64(bcr, 20, 4); - - switch (bt) { - case 4: /* unlinked address mismatch (reserved if AArch64) */ - case 5: /* linked address mismatch (reserved if AArch64) */ - qemu_log_mask(LOG_UNIMP, - "arm: address mismatch breakpoint types not implemen= ted\n"); - return; - case 0: /* unlinked address match */ - case 1: /* linked address match */ - { - /* - * Bits [1:0] are RES0. - * - * It is IMPLEMENTATION DEFINED whether bits [63:49] - * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit - * of the VA field ([48] or [52] for FEAT_LVA), or whether the - * value is read as written. It is CONSTRAINED UNPREDICTABLE - * whether the RESS bits are ignored when comparing an address. - * Therefore we are allowed to compare the entire register, which - * lets us avoid considering whether FEAT_LVA is actually enabled. - * - * The BAS field is used to allow setting breakpoints on 16-bit - * wide instructions; it is CONSTRAINED UNPREDICTABLE whether - * a bp will fire if the addresses covered by the bp and the addre= sses - * covered by the insn overlap but the insn doesn't start at the - * start of the bp address range. We choose to require the insn and - * the bp to have the same address. The constraints on writing to - * BAS enforced in dbgbcr_write mean we have only four cases: - * 0b0000 =3D> no breakpoint - * 0b0011 =3D> breakpoint on addr - * 0b1100 =3D> breakpoint on addr + 2 - * 0b1111 =3D> breakpoint on addr - * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). - */ - int bas =3D extract64(bcr, 5, 4); - addr =3D bvr & ~3ULL; - if (bas =3D=3D 0) { - return; - } - if (bas =3D=3D 0xc) { - addr +=3D 2; - } - break; - } - case 2: /* unlinked context ID match */ - case 8: /* unlinked VMID match (reserved if no EL2) */ - case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ - qemu_log_mask(LOG_UNIMP, - "arm: unlinked context breakpoint types not implemen= ted\n"); - return; - case 9: /* linked VMID match (reserved if no EL2) */ - case 11: /* linked context ID and VMID match (reserved if no EL2) */ - case 3: /* linked context ID match */ - default: - /* - * We must generate no events for Linked context matches (unless - * they are linked to by some other bp/wp, which is handled in - * updates for the linking bp/wp). We choose to also generate no e= vents - * for reserved values. - */ - return; - } - - cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); -} - -void hw_breakpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* - * Completely clear out existing QEMU breakpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { - hw_breakpoint_update(cpu, i); - } -} - -#if !defined(CONFIG_USER_ONLY) - -vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* - * In BE32 system mode, target memory is stored byteswapped (on a - * little-endian host system), and by the time we reach here (via an - * opcode helper) the addresses of subword accesses have been adjusted - * to account for that, which means that watchpoints will not match. - * Undo the adjustment here. - */ - if (arm_sctlr_b(env)) { - if (len =3D=3D 1) { - addr ^=3D 3; - } else if (len =3D=3D 2) { - addr ^=3D 2; - } - } - - return addr; -} - -#endif /* !CONFIG_USER_ONLY */ -#endif /* CONFIG_TCG */ - /* * Check for traps to "powerdown debug" registers, which are controlled * by MDCR.TDOSA diff --git a/target/arm/debug_helper.c b/target/arm/tcg/debug.c similarity index 53% copy from target/arm/debug_helper.c copy to target/arm/tcg/debug.c index 579516e154..7dfb291a9b 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/tcg/debug.c @@ -1,5 +1,5 @@ /* - * ARM debug helpers. + * ARM debug helpers used by TCG * * This code is licensed under the GNU GPL v2 or later. * @@ -17,7 +17,6 @@ #define HELPER_H "tcg/helper.h" #include "exec/helper-proto.h.inc" =20 -#ifdef CONFIG_TCG /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) { @@ -47,7 +46,7 @@ static int arm_debug_target_el(CPUARMState *env) * Raise an exception to the debug target el. * Modify syndrome to indicate when origin and target EL are the same. */ -G_NORETURN static void +static G_NORETURN void raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome) { int debug_el =3D arm_debug_target_el(env); @@ -781,542 +780,3 @@ vaddr arm_adjust_watchpoint_address(CPUState *cs, vad= dr addr, int len) } =20 #endif /* !CONFIG_USER_ONLY */ -#endif /* CONFIG_TCG */ - -/* - * Check for traps to "powerdown debug" registers, which are controlled - * by MDCR.TDOSA - */ -static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - bool mdcr_el2_tdosa =3D (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TD= E) || - (arm_hcr_el2_eff(env) & HCR_TGE); - - if (el < 2 && mdcr_el2_tdosa) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -/* - * Check for traps to "debug ROM" registers, which are controlled - * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. - */ -static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - bool mdcr_el2_tdra =3D (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE)= || - (arm_hcr_el2_eff(env) & HCR_TGE); - - if (el < 2 && mdcr_el2_tdra) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -/* - * Check for traps to general debug registers, which are controlled - * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. - */ -static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - bool mdcr_el2_tda =3D (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || - (arm_hcr_el2_eff(env) & HCR_TGE); - - if (el < 2 && mdcr_el2_tda) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -static CPAccessResult access_dbgvcr32(CPUARMState *env, const ARMCPRegInfo= *ri, - bool isread) -{ - /* MCDR_EL3.TDMA doesn't apply for FEAT_NV traps */ - if (arm_current_el(env) =3D=3D 2 && (env->cp15.mdcr_el3 & MDCR_TDA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -/* - * Check for traps to Debug Comms Channel registers. If FEAT_FGT - * is implemented then these are controlled by MDCR_EL2.TDCC for - * EL2 and MDCR_EL3.TDCC for EL3. They are also controlled by - * the general debug access trap bits MDCR_EL2.TDA and MDCR_EL3.TDA. - * For EL0, they are also controlled by MDSCR_EL1.TDCC. - */ -static CPAccessResult access_tdcc(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - bool mdscr_el1_tdcc =3D extract32(env->cp15.mdscr_el1, 12, 1); - bool mdcr_el2_tda =3D (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || - (arm_hcr_el2_eff(env) & HCR_TGE); - bool mdcr_el2_tdcc =3D cpu_isar_feature(aa64_fgt, env_archcpu(env)) && - (mdcr_el2 & MDCR_TDCC); - bool mdcr_el3_tdcc =3D cpu_isar_feature(aa64_fgt, env_archcpu(env)) && - (env->cp15.mdcr_el3 & MDCR_TDCC); - - if (el < 1 && mdscr_el1_tdcc) { - return CP_ACCESS_TRAP_EL1; - } - if (el < 2 && (mdcr_el2_tda || mdcr_el2_tdcc)) { - return CP_ACCESS_TRAP_EL2; - } - if (!arm_is_el3_or_mon(env) && - ((env->cp15.mdcr_el3 & MDCR_TDA) || mdcr_el3_tdcc)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Writes to OSLAR_EL1 may update the OS lock status, which can be - * read via a bit in OSLSR_EL1. - */ - int oslock; - - if (ri->state =3D=3D ARM_CP_STATE_AA32) { - oslock =3D (value =3D=3D 0xC5ACCE55); - } else { - oslock =3D value & 1; - } - - env->cp15.oslsr_el1 =3D deposit32(env->cp15.oslsr_el1, 1, 1, oslock); -} - -static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - /* - * Only defined bit is bit 0 (DLK); if Feat_DoubleLock is not - * implemented this is RAZ/WI. - */ - if(arm_feature(env, ARM_FEATURE_AARCH64) - ? cpu_isar_feature(aa64_doublelock, cpu) - : cpu_isar_feature(aa32_doublelock, cpu)) { - env->cp15.osdlr_el1 =3D value & 1; - } -} - -static void dbgclaimset_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.dbgclaim |=3D (value & 0xFF); -} - -static uint64_t dbgclaimset_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* CLAIM bits are RAO */ - return 0xFF; -} - -static void dbgclaimclr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.dbgclaim &=3D ~(value & 0xFF); -} - -static CPAccessResult access_bogus(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - /* Always UNDEF, as if this cpreg didn't exist */ - return CP_ACCESS_UNDEFINED; -} - -static const ARMCPRegInfo debug_cp_reginfo[] =3D { - /* - * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped - * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; - * unlike DBGDRAR it is never accessible from EL0. - * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AAr= ch64 - * accessor. - */ - { .name =3D "DBGDRAR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue =3D 0 }, - { .name =3D "MDRAR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "DBGDSAR", .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue =3D 0 }, - /* Monitor debug system control register; the 32-bit alias is DBGDSCRe= xt. */ - { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fgt =3D FGT_MDSCR_EL1, - .nv2_redirect_offset =3D 0x158, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), - .resetvalue =3D 0 }, - /* - * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external - * Debug Communication Channel is not implemented. - */ - { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tdcc, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* - * These registers belong to the Debug Communications Channel, - * which is not implemented. However we implement RAZ/WI behaviour - * with trapping to prevent spurious SIGILLs if the guest OS does - * access them as the support cannot be probed for. - */ - { .name =3D "OSDTRRX_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, - .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tdcc, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "OSDTRTX_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, - .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tdcc, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* Architecturally DBGDTRTX is named DBGDTRRX when used for reads */ - { .name =3D "DBGDTRTX_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 5, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D access_tdcc, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "DBGDTRTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 14, - .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D access_tdcc, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* This is AArch64-only and is a combination of DBGDTRTX and DBGDTRRX = */ - { .name =3D "DBGDTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 4, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D access_tdcc, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* - * This is not a real AArch32 register. We used to incorrectly expose - * this due to a QEMU bug; to avoid breaking migration compatibility we - * need to continue to provide it so that we don't fail the inbound - * migration when it tells us about a sysreg that we don't have. - * We set an always-fails .accessfn, which means that the guest doesn't - * actually see this register (it will always UNDEF, identically to if - * there were no cpreg definition for it other than that we won't print - * a LOG_UNIMP message about it), and we set the ARM_CP_NO_GDB flag so= the - * gdbstub won't see it either. - * (We can't just set .access =3D 0, because add_cpreg_to_hashtable() - * helpfully ignores cpregs which aren't accessible to the highest - * implemented EL.) - * - * TODO: implement a system for being able to describe "this register - * can be ignored if it appears in the inbound stream"; then we can - * remove this temporary hack. - */ - { .name =3D "BOGUS_DBGDTR_EL0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 14, .opc1 =3D 3, .crn =3D 0, .crm =3D 5, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D access_bogus, - .type =3D ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue =3D 0 }, - /* - * OSECCR_EL1 provides a mechanism for an operating system - * to access the contents of EDECCR. EDECCR is not implemented though, - * as is the rest of external device mechanism. - */ - { .name =3D "OSECCR_EL1", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, - .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fgt =3D FGT_OSECCR_EL1, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* - * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as - * it is unlikely a guest will care. - * We don't implement the configurable EL0 access. - */ - { .name =3D "DBGDSCRint", .state =3D ARM_CP_STATE_AA32, - .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, - .type =3D ARM_CP_ALIAS, - .access =3D PL1_R, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), }, - { .name =3D "OSLAR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 = =3D 4, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .accessfn =3D access_tdosa, - .fgt =3D FGT_OSLAR_EL1, - .writefn =3D oslar_write }, - { .name =3D "OSLSR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 = =3D 4, - .access =3D PL1_R, .resetvalue =3D 10, - .accessfn =3D access_tdosa, - .fgt =3D FGT_OSLSR_EL1, - .fieldoffset =3D offsetof(CPUARMState, cp15.oslsr_el1) }, - /* Dummy OSDLR_EL1: 32-bit Linux will read this */ - { .name =3D "OSDLR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, - .access =3D PL1_RW, .accessfn =3D access_tdosa, - .fgt =3D FGT_OSDLR_EL1, - .writefn =3D osdlr_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.osdlr_el1) }, - /* - * Dummy DBGVCR: Linux wants to clear this on startup, but we don't - * implement vector catch debug events yet. - */ - { .name =3D "DBGVCR", - .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* - * Dummy MDCCINT_EL1, since we don't implement the Debug Communications - * Channel but Linux may try to access this register. The 32-bit - * alias is DBGDCCINT. - */ - { .name =3D "MDCCINT_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tdcc, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* - * Dummy DBGCLAIM registers. - * "The architecture does not define any functionality for the CLAIM t= ag bits.", - * so we only keep the raw bits - */ - { .name =3D "DBGCLAIMSET_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 = =3D 6, - .type =3D ARM_CP_ALIAS, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fgt =3D FGT_DBGCLAIM, - .writefn =3D dbgclaimset_write, .readfn =3D dbgclaimset_read }, - { .name =3D "DBGCLAIMCLR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 = =3D 6, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fgt =3D FGT_DBGCLAIM, - .writefn =3D dbgclaimclr_write, .raw_writefn =3D raw_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgclaim) }, -}; - -/* These are present only when EL1 supports AArch32 */ -static const ARMCPRegInfo debug_aa32_el1_reginfo[] =3D { - /* - * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor - * to save and restore a 32-bit guest's DBGVCR) - */ - { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D access_dbgvcr32, - .type =3D ARM_CP_CONST | ARM_CP_EL3_NO_EL2_KEEP, - .resetvalue =3D 0 }, -}; - -static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { - /* 64 bit access versions of the (dummy) debug registers */ - { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT | ARM_CP_NO= _GDB, - .resetvalue =3D 0 }, - { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_64BIT | ARM_CP_NO= _GDB, - .resetvalue =3D 0 }, -}; - -static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - /* - * Bits [1:0] are RES0. - * - * It is IMPLEMENTATION DEFINED whether [63:49] ([63:53] with FEAT_LVA) - * are hardwired to the value of bit [48] ([52] with FEAT_LVA), or if - * they contain the value written. It is CONSTRAINED UNPREDICTABLE - * whether the RESS bits are ignored when comparing an address. - * - * Therefore we are allowed to compare the entire register, which lets - * us avoid considering whether or not FEAT_LVA is actually enabled. - */ - value &=3D ~3ULL; - - raw_write(env, ri, value); - if (tcg_enabled()) { - hw_watchpoint_update(cpu, i); - } -} - -static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - raw_write(env, ri, value); - if (tcg_enabled()) { - hw_watchpoint_update(cpu, i); - } -} - -static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - raw_write(env, ri, value); - if (tcg_enabled()) { - hw_breakpoint_update(cpu, i); - } -} - -static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - /* - * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only - * copy of BAS[0]. - */ - value =3D deposit64(value, 6, 1, extract64(value, 5, 1)); - value =3D deposit64(value, 8, 1, extract64(value, 7, 1)); - - raw_write(env, ri, value); - if (tcg_enabled()) { - hw_breakpoint_update(cpu, i); - } -} - -void define_debug_regs(ARMCPU *cpu) -{ - /* - * Define v7 and v8 architectural debug registers. - * These are just dummy implementations for now. - */ - int i; - int wrps, brps, ctx_cmps; - - /* - * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot - * use AArch32. Given that bit 15 is RES1, if the value is 0 then - * the register must not exist for this cpu. - */ - if (cpu->isar.dbgdidr !=3D 0) { - ARMCPRegInfo dbgdidr =3D { - .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, - .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.dbgdidr, - }; - define_one_arm_cp_reg(cpu, &dbgdidr); - } - - /* - * DBGDEVID is present in the v7 debug architecture if - * DBGDIDR.DEVID_imp is 1 (bit 15); from v7.1 and on it is - * mandatory (and bit 15 is RES1). DBGDEVID1 and DBGDEVID2 exist - * from v7.1 of the debug architecture. Because no fields have yet - * been defined in DBGDEVID2 (and quite possibly none will ever - * be) we don't define an ARMISARegisters field for it. - * These registers exist only if EL1 can use AArch32, but that - * happens naturally because they are only PL1 accessible anyway. - */ - if (extract32(cpu->isar.dbgdidr, 15, 1)) { - ARMCPRegInfo dbgdevid =3D { - .name =3D "DBGDEVID", - .cp =3D 14, .opc1 =3D 0, .crn =3D 7, .opc2 =3D 2, .crn =3D 7, - .access =3D PL1_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.dbgdevid, - }; - define_one_arm_cp_reg(cpu, &dbgdevid); - } - if (cpu_isar_feature(aa32_debugv7p1, cpu)) { - ARMCPRegInfo dbgdevid12[] =3D { - { - .name =3D "DBGDEVID1", - .cp =3D 14, .opc1 =3D 0, .crn =3D 7, .opc2 =3D 1, .crn =3D= 7, - .access =3D PL1_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.dbgdevid= 1, - }, { - .name =3D "DBGDEVID2", - .cp =3D 14, .opc1 =3D 0, .crn =3D 7, .opc2 =3D 0, .crn =3D= 7, - .access =3D PL1_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D 0, - }, - }; - define_arm_cp_regs(cpu, dbgdevid12); - } - - brps =3D arm_num_brps(cpu); - wrps =3D arm_num_wrps(cpu); - ctx_cmps =3D arm_num_ctx_cmps(cpu); - - assert(ctx_cmps <=3D brps); - - define_arm_cp_regs(cpu, debug_cp_reginfo); - if (cpu_isar_feature(aa64_aa32_el1, cpu)) { - define_arm_cp_regs(cpu, debug_aa32_el1_reginfo); - } - - if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { - define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); - } - - for (i =3D 0; i < brps; i++) { - char *dbgbvr_el1_name =3D g_strdup_printf("DBGBVR%d_EL1", i); - char *dbgbcr_el1_name =3D g_strdup_printf("DBGBCR%d_EL1", i); - ARMCPRegInfo dbgregs[] =3D { - { .name =3D dbgbvr_el1_name, .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fgt =3D FGT_DBGBVRN_EL1, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbvr[i]), - .writefn =3D dbgbvr_write, .raw_writefn =3D raw_write - }, - { .name =3D dbgbcr_el1_name, .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 5, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fgt =3D FGT_DBGBCRN_EL1, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), - .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write - }, - }; - define_arm_cp_regs(cpu, dbgregs); - g_free(dbgbvr_el1_name); - g_free(dbgbcr_el1_name); - } - - for (i =3D 0; i < wrps; i++) { - char *dbgwvr_el1_name =3D g_strdup_printf("DBGWVR%d_EL1", i); - char *dbgwcr_el1_name =3D g_strdup_printf("DBGWCR%d_EL1", i); - ARMCPRegInfo dbgregs[] =3D { - { .name =3D dbgwvr_el1_name, .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fgt =3D FGT_DBGWVRN_EL1, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwvr[i]), - .writefn =3D dbgwvr_write, .raw_writefn =3D raw_write - }, - { .name =3D dbgwcr_el1_name, .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 7, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fgt =3D FGT_DBGWCRN_EL1, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), - .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write - }, - }; - define_arm_cp_regs(cpu, dbgregs); - g_free(dbgwvr_el1_name); - g_free(dbgwcr_el1_name); - } -} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 1b115656c4..6e9aed3e5d 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -65,6 +65,7 @@ arm_common_ss.add(files( =20 arm_common_system_ss.add(files( 'cpregs-at.c', + 'debug.c', 'hflags.c', 'neon_helper.c', 'tlb_helper.c', @@ -72,6 +73,7 @@ arm_common_system_ss.add(files( 'vfp_helper.c', )) arm_user_ss.add(files( + 'debug.c', 'hflags.c', 'neon_helper.c', 'tlb_helper.c', --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497408; cv=none; d=zohomail.com; s=zohoarc; b=g0hYdGwl9BLMVFAr1X++AGU+aGOdBdfrE1jwgG8gELKCB9T4ikCoCPwSZn938s5FdxM8XaI2hgdp48s6Je8dofWq5mjWrdTZ+wU/0TYP4B0NuWuaQTpx/XUrWZSAU118r+eTkqK1EDXXkQ2Y3ijEB3TcnF7ZpBssU1m/RRH4Pow= ARC-Message-Signature: i=1; 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We don't actually need to do this -- because we have already written the new EL into pstate and updated env->aarch64, we can call aarch64_rebuild_hflags() to achieve the same effect. This is the function we use everywhere else in this file to update hflags. Switch to aarch64_rebuild_hflags() and drop the include of the TCG helper headers. Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e12b2455d3..6bfab90981 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -36,9 +36,6 @@ #include "target/arm/gtimer.h" #include "qemu/plugin.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - static void switch_mode(CPUARMState *env, int mode); =20 int compare_u64(const void *a, const void *b) @@ -9479,7 +9476,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) aarch64_restore_sp(env, new_el); =20 if (tcg_enabled()) { - helper_rebuild_hflags_a64(env, new_el); + arm_rebuild_hflags(env); } =20 env->pc =3D addr; --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497531; cv=none; d=zohomail.com; s=zohoarc; b=kK5x3hbTIsLLAcqG2ZercJQwYBMGaPkdSMu47bnHftNqHs7ojhM7m0KDL9rzb2AmMn0YXWyNrAkEK4JbDwf338jg5eg6ikrIAOgOHwgPFHay3e+IXhIE4NuQn2PMi1mZkpA6/XZYyZJaeI3IymWQJBjok8LbfkD0Xk7egluiY/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497531; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=m8XAwLErH5Rcrg8uudfF2MM7yDSTJj5Y5UUFSlFxuTA=; b=HbQEo7xp1Kcr1oOBss2mTCz+n4VUAJUTC74+UKWbSu8y8umbKYbGdjuu+f5b8uISs/SHK/Ah0HUGuVnjOoGMtKqIbp8Ph9x8ho85ShWoTYSBVkBMSLS5iu3vXX2hxznYCPP3x8Y601Ec6Yvrk79uChtcDSDh7vF/JHtzzWYaTSU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497531828803.9305839438525; Thu, 19 Feb 2026 02:38:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mi-0007K2-6h; Thu, 19 Feb 2026 05:34:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1Mg-0007IP-2Y for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:34 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1MZ-00067A-OQ for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:33 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4807068eacbso6916565e9.2 for ; Thu, 19 Feb 2026 02:34:27 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497266; x=1772102066; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=m8XAwLErH5Rcrg8uudfF2MM7yDSTJj5Y5UUFSlFxuTA=; b=XcGPTiiTd3faOn8bIRSRd4AG4trlt74Tdq4eZAIoLRRjYtjAT8XR1s8f0FjBJyZWGa c2fMJQhvzsHrkeAYryM1azAL5iM1cmnqYOJSfioRUd9bU8DiMr7/UBiqLAcSoC1EH7V7 kQ9WRNeWyKXmg8rUr3roKVsc2ZqONfRwkdS/3Lx86L+NKOyyX7B5+lD8Zx2YQO8J1FMa 32tl/Z5RuC0qOCKunEyZ3bqXYKl6zeDJB3eVgdkGpoHDnj0jezJe8GGYqKb0DvDBGtIm Lii5nK/S3SnMW1TmZh455JtcFOjv6RXOrNy+79feoa8LDPwp6YL0yKU86GcqiR0ZuZKn cOog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497266; x=1772102066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=m8XAwLErH5Rcrg8uudfF2MM7yDSTJj5Y5UUFSlFxuTA=; b=n2Fr0BPO8jPEzS0swI9Aq/cZcVAub0ahDb9yprt5fG4RDTgvucwhyyPaRFdW8+cu9Z bl0xqfx2aVgIi32CwOjdMnSfnJf8uezase0NXz3SLRMEGRFbKTHzhZJw90Vi71FKHOPK wja1WhjybXYPrZbruQLNEM6XHVWA+4YmUqxjme1poaofFCXuDaSXgc7vGO2lu0s+E0NF cngoOedOspGoUyUDqIz9Qu79oS4pCPOFUX1MOcnANI0+kNEpRn672eN0KOScxAIg2ex4 LpPgZrZZQmapWwdOficraGVYrvFZ97vRrdvLkx39/AgP/Zuv8ORhBuW8K0y5bbui50rx nQrg== X-Gm-Message-State: AOJu0YySrK8mjdcjTkMJ4BbhHxap7+Fa6qHtgp4HeASZ2mSjeUUpKsRR lQ2lnsRFfFj+TzlRL4MapVHGuDTnq13qHbvdvuLWYYIkc+KU1Lk1pL0hZC1Ll/DILeDlsow1toY 37dKx X-Gm-Gg: AZuq6aL5pe2+/6HXV4rYSm5IYnvEMlb+kCTuot/kXmD2zkOHo44pa/NgdADJvqUuQz1 /xcbeekGSmKabG8eeISECOvCBKe97l5yuES+BU2fcXMzWE4Ifuok2kNIH9eYavdg1BW5sOHSrHW r3LikYOO2YZWVmGd1nkj4zCLhbEUD7eAwcKyQTuuCOhP0toMn3ueZQq1LUgRpOJAqdAlgBAdKgI SIO+aip2VlSonoeghLuveNIUfIEsqGPvN+SDpGfOfaRJsTx/yAwUFOr66IlsjgBeEtIYJ2gMzZi rjuP05gWXglO6NAGIzQ/G7hAA9qcM+O8DbPJ/LeBPt8nGWqkDiNrqqGuuNz1ZsZq4Qx+YKVwYRP QObSF9tguxUzzLOFMOcsgJIyhIUgDB+kzUbvInqDeh2vS4RcEOUq1GbIqtvxjzXcIxynxWOChU4 tjFNnhOaYs4meOwOBwZwOKEpgQD8Df7/S4k2v4sQcq166tEL+gGQxHFub7kYNXNqMsNGdFUZ6Gi 7EUon9wKdrwUQpIElrprkqfVcxyqZU= X-Received: by 2002:a05:600c:c176:b0:483:6a8d:b2fc with SMTP id 5b1f17b1804b1-48398a425bbmr68682385e9.8.1771497265864; Thu, 19 Feb 2026 02:34:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/32] target/arm: extract helper-mve.h from helper.h Date: Thu, 19 Feb 2026 10:33:54 +0000 Message-ID: <20260219103405.3793357-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497533045158500 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier A few points to mention: - We mix helper prototypes and gen_helper definitions in a single header for convenience and to avoid headers boilerplate. - We rename existing tcg/helper-mve.h to helper-mve-defs.h to avoid conflict when including helper-mve.h. - We move mve helper_info definitions to tcg/mve_helper.c We'll repeat the same for other helpers. This allow to get rid of TARGET_AARCH64 in target/arm/helper.h. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-4-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 14 ++++++++++++++ target/arm/helper.h | 2 -- target/arm/tcg/{helper-mve.h =3D> helper-mve-defs.h} | 0 target/arm/tcg/mve_helper.c | 4 ++++ target/arm/tcg/translate-mve.c | 1 + target/arm/tcg/translate.c | 1 + 6 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 target/arm/helper-mve.h rename target/arm/tcg/{helper-mve.h =3D> helper-mve-defs.h} (100%) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h new file mode 100644 index 0000000000..32ef3f6466 --- /dev/null +++ b/target/arm/helper-mve.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_MVE_H +#define HELPER_MVE_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-mve-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_MVE_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index f340a49a28..44c7f3ed75 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -7,5 +7,3 @@ #include "tcg/helper-sve.h" #include "tcg/helper-sme.h" #endif - -#include "tcg/helper-mve.h" diff --git a/target/arm/tcg/helper-mve.h b/target/arm/tcg/helper-mve-defs.h similarity index 100% rename from target/arm/tcg/helper-mve.h rename to target/arm/tcg/helper-mve-defs.h diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 63ddcf3fec..f33642df1f 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper-mve.h" #include "internals.h" #include "vec_internal.h" #include "exec/helper-proto.h" @@ -27,6 +28,9 @@ #include "fpu/softfloat.h" #include "crypto/clmul.h" =20 +#define HELPER_H "tcg/helper-mve-defs.h" +#include "exec/helper-info.c.inc" + static uint16_t mve_eci_mask(CPUARMState *env) { /* diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index b1a8d6a65c..4ca88f4d3a 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "helper-mve.h" #include "translate.h" #include "translate-a32.h" =20 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index c90b0106f7..580ec86c68 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -28,6 +28,7 @@ #include "cpregs.h" #include "exec/helper-proto.h" #include "exec/target_page.h" +#include "helper-mve.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 19 Feb 2026 02:34:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/32] target/arm: extract helper-a64.h from helper.h Date: Thu, 19 Feb 2026 10:33:55 +0000 Message-ID: <20260219103405.3793357-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497537037158500 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-5-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-a64.h | 14 ++++++++++++++ target/arm/helper.h | 1 - target/arm/tcg/{helper-a64.h =3D> helper-a64-defs.h} | 0 target/arm/tcg/helper-a64.c | 4 ++++ target/arm/tcg/mte_helper.c | 1 + target/arm/tcg/pauth_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/vec_helper.c | 1 + 9 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 target/arm/helper-a64.h rename target/arm/tcg/{helper-a64.h =3D> helper-a64-defs.h} (100%) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h new file mode 100644 index 0000000000..cda7e039b7 --- /dev/null +++ b/target/arm/helper-a64.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_A64_H +#define HELPER_A64_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-a64-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_A64_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 44c7f3ed75..79f8de1e16 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -3,7 +3,6 @@ #include "tcg/helper.h" =20 #ifdef TARGET_AARCH64 -#include "tcg/helper-a64.h" #include "tcg/helper-sve.h" #include "tcg/helper-sme.h" #endif diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64-defs.h similarity index 100% rename from target/arm/tcg/helper-a64.h rename to target/arm/tcg/helper-a64-defs.h diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index e4d2c2e392..07ddfb895d 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" +#include "helper-a64.h" #include "qemu/host-utils.h" #include "qemu/log.h" #include "qemu/main-loop.h" @@ -43,6 +44,9 @@ #endif #include "vec_internal.h" =20 +#define HELPER_H "tcg/helper-a64-defs.h" +#include "exec/helper-info.c.inc" + /* C2.4.7 Multiply and divide */ /* special cases for 0 and LLONG_MIN are mandated by the standard */ uint64_t HELPER(udiv64)(uint64_t num, uint64_t den) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 08b8e7176a..01b7f099f4 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -31,6 +31,7 @@ #endif #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" +#include "helper-a64.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index c591c3052c..5a20117ae8 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -22,6 +22,7 @@ #include "internals.h" #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" +#include "helper-a64.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index c442fcb540..0600eea47c 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" +#include "helper-a64.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 7a8cd99e00..1a54337b6a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "exec/target_page.h" +#include "helper-a64.h" #include "translate.h" #include "translate-a64.h" #include "qemu/log.h" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 33a136b90a..7451a283ef 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "helper-a64.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 19 Feb 2026 02:34:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/32] target/arm: extract helper-sve.h from helper.h Date: Thu, 19 Feb 2026 10:33:56 +0000 Message-ID: <20260219103405.3793357-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497531048158500 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-6-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-sve.h | 14 ++++++++++++++ target/arm/helper.h | 1 - target/arm/tcg/gengvec64.c | 3 ++- target/arm/tcg/{helper-sve.h =3D> helper-sve-defs.h} | 0 target/arm/tcg/sve_helper.c | 3 +++ target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/translate-sme.c | 2 ++ target/arm/tcg/translate-sve.c | 2 ++ target/arm/tcg/vec_helper.c | 1 + 9 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 target/arm/helper-sve.h rename target/arm/tcg/{helper-sve.h =3D> helper-sve-defs.h} (100%) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h new file mode 100644 index 0000000000..ae4f46c70a --- /dev/null +++ b/target/arm/helper-sve.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_SVE_H +#define HELPER_SVE_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-sve-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_SVE_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 79f8de1e16..2f724643d3 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -3,6 +3,5 @@ #include "tcg/helper.h" =20 #ifdef TARGET_AARCH64 -#include "tcg/helper-sve.h" #include "tcg/helper-sme.h" #endif diff --git a/target/arm/tcg/gengvec64.c b/target/arm/tcg/gengvec64.c index c425d2b149..c7bdd1ea82 100644 --- a/target/arm/tcg/gengvec64.c +++ b/target/arm/tcg/gengvec64.c @@ -18,10 +18,11 @@ */ =20 #include "qemu/osdep.h" +#include "cpu.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" =20 - static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) { tcg_gen_rotli_i64(d, m, 1); diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve-defs.h similarity index 100% rename from target/arm/tcg/helper-sve.h rename to target/arm/tcg/helper-sve-defs.h diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 0600eea47c..16e528e41a 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -25,6 +25,7 @@ #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "helper-a64.h" +#include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" @@ -38,6 +39,8 @@ #include "user/page-protection.h" #endif =20 +#define HELPER_H "tcg/helper-sve-defs.h" +#include "exec/helper-info.c.inc" =20 /* Return a value for NZCV as per the ARM PredTest pseudofunction. * diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1a54337b6a..31fb2ea9cc 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "exec/target_page.h" #include "helper-a64.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" #include "qemu/log.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 091c56da4f..463ece97ab 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -18,6 +18,8 @@ */ =20 #include "qemu/osdep.h" +#include "cpu.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" =20 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 956ddee123..bd6be68d81 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -18,6 +18,8 @@ */ =20 #include "qemu/osdep.h" +#include "cpu.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 7451a283ef..bc64c8ff37 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "helper-a64.h" +#include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 19 Feb 2026 02:34:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/32] target/arm: extract helper-sme.h from helper.h Date: Thu, 19 Feb 2026 10:33:57 +0000 Message-ID: <20260219103405.3793357-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497396498158500 Content-Type: text/plain; charset="utf-8" From: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-7-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-sme.h | 14 ++++++++++++++ target/arm/helper.h | 4 ---- target/arm/tcg/{helper-sme.h =3D> helper-sme-defs.h} | 0 target/arm/tcg/sme_helper.c | 3 +++ target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/translate-sme.c | 1 + target/arm/tcg/translate-sve.c | 1 + target/arm/tcg/vec_helper.c | 1 + 8 files changed, 21 insertions(+), 4 deletions(-) create mode 100644 target/arm/helper-sme.h rename target/arm/tcg/{helper-sme.h =3D> helper-sme-defs.h} (100%) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h new file mode 100644 index 0000000000..27c85fdeef --- /dev/null +++ b/target/arm/helper-sme.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_SME_H +#define HELPER_SME_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-sme-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_SME_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 2f724643d3..b1e83196b3 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1,7 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ =20 #include "tcg/helper.h" - -#ifdef TARGET_AARCH64 -#include "tcg/helper-sme.h" -#endif diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme-defs.h similarity index 100% rename from target/arm/tcg/helper-sme.h rename to target/arm/tcg/helper-sme-defs.h diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 075360d8b8..7729732369 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -22,6 +22,7 @@ #include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "helper-sme.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" @@ -29,6 +30,8 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" =20 +#define HELPER_H "tcg/helper-sme-defs.h" +#include "exec/helper-info.c.inc" =20 static bool vectors_overlap(ARMVectorReg *x, unsigned nx, ARMVectorReg *y, unsigned ny) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 31fb2ea9cc..5d261a5e32 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "exec/target_page.h" #include "helper-a64.h" +#include "helper-sme.h" #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 463ece97ab..7d25ac5a51 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper-sme.h" #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index bd6be68d81..5bace3fda1 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper-sme.h" #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index bc64c8ff37..a070ac9057 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "helper-a64.h" +#include "helper-sme.h" #include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Our new helper pattern always include helper-*-common.h, which ends up including include/tcg/tcg.h, which contains one occurrence of CONFIG_USER_ONLY. Thus, common files not being duplicated between system and target relying on helpers will fail to compile. Existing occurrences are: - target/arm/tcg/arith_helper.c - target/arm/tcg/crypto_helper.c This occurrence of CONFIG_USER_ONLY is for defining variable tcg_use_softmmu, and we rely on dead code elimination with it in various tcg-target.c.inc. Thus, move its definition to tcg/tcg-internal.h, so helpers can be included by common files. Also, change it to a define, as it has fixed values for now. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-8-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- include/tcg/tcg.h | 6 ------ tcg/tcg-internal.h | 6 ++++++ tcg/tcg.c | 4 ---- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 60942ce05c..45c7e118c3 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -445,12 +445,6 @@ static inline bool temp_readonly(TCGTemp *ts) return ts->kind >=3D TEMP_FIXED; } =20 -#ifdef CONFIG_USER_ONLY -extern bool tcg_use_softmmu; -#else -#define tcg_use_softmmu true -#endif - extern __thread TCGContext *tcg_ctx; extern const void *tcg_code_gen_epilogue; extern uintptr_t tcg_splitwx_diff; diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 2cbfb5d5ca..2615684612 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -34,6 +34,12 @@ extern TCGContext **tcg_ctxs; extern unsigned int tcg_cur_ctxs; extern unsigned int tcg_max_ctxs; =20 +#ifdef CONFIG_USER_ONLY +#define tcg_use_softmmu false +#else +#define tcg_use_softmmu true +#endif + void tcg_region_init(size_t tb_size, int splitwx, unsigned max_threads); bool tcg_region_alloc(TCGContext *s); void tcg_region_initial_alloc(TCGContext *s); diff --git a/tcg/tcg.c b/tcg/tcg.c index e7bf4dad4e..3111e1f426 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -236,10 +236,6 @@ static TCGAtomAlign atom_and_align_for_opc(TCGContext = *s, MemOp opc, MemOp host_atom, bool allow_two= _ops) __attribute__((unused)); =20 -#ifdef CONFIG_USER_ONLY -bool tcg_use_softmmu; -#endif - TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; =20 --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497498; cv=none; d=zohomail.com; s=zohoarc; b=KURwm+bev8jJeYly9kIyGBJK6l5FiJoAuNwJ+jviHcJ0UtVtMRWn3GiPG9A9owJMSGT0hTCpNtCPh8lJMWHdFRYKKJuXqf9KAaIrnN0JgkEn+Lje3F13URofq6pysh1GQSTptoTcZv8RxVmsJ1VRzv/vzMbfTPf65HPDXrfTvUs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497498; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Vt5oT7ghhA4hiP2MKIWnryipV1YbDZfQDKUwm/lTTPo=; b=nnSMSqW30tOMZH3bA84wnPh+aIGT3CoC/yCi+C8JZt/iNLY1pVAbYIHDdspFPt4+OXkYQQCpZ5ZOTHtFw3nfvpnu0lf9Bz9MYqvjl31Vtas/5GLkfnUn/6cXN9nnT/iuqt1yZ692vCJF44rxqRqtfi+kAV/IHHWwT15zdAcmXKY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497498288145.83504335455132; Thu, 19 Feb 2026 02:38:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mm-0007Nh-6L; Thu, 19 Feb 2026 05:34:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1Mj-0007LZ-DH for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:37 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1Mf-00068J-IL for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:37 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4807068eacbso6917145e9.2 for ; Thu, 19 Feb 2026 02:34:31 -0800 (PST) Received: from lanath.. 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This way, all helpers use the same pattern, and helper include details are limited to those headers. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-9-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 13 ++++++++++++- target/arm/tcg/arith_helper.c | 4 +--- target/arm/tcg/crypto_helper.c | 4 +--- target/arm/tcg/debug.c | 4 +--- target/arm/tcg/helper-a64.c | 2 +- target/arm/tcg/{helper.h =3D> helper-defs.h} | 0 target/arm/tcg/hflags.c | 4 +--- target/arm/tcg/m_helper.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/mve_helper.c | 2 +- target/arm/tcg/neon_helper.c | 4 +--- target/arm/tcg/op_helper.c | 2 +- target/arm/tcg/pauth_helper.c | 2 +- target/arm/tcg/psci.c | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/sve_helper.c | 2 +- target/arm/tcg/tlb_helper.c | 4 +--- target/arm/tcg/translate.c | 9 ++++----- target/arm/tcg/translate.h | 2 +- target/arm/tcg/vec_helper.c | 2 +- target/arm/tcg/vfp_helper.c | 4 +--- 21 files changed, 34 insertions(+), 38 deletions(-) rename target/arm/tcg/{helper.h =3D> helper-defs.h} (100%) diff --git a/target/arm/helper.h b/target/arm/helper.h index b1e83196b3..b1c26c180e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1,3 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#include "tcg/helper.h" +#ifndef HELPER__H +#define HELPER__H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER__H */ diff --git a/target/arm/tcg/arith_helper.c b/target/arm/tcg/arith_helper.c index 97c6362992..cc081c8f96 100644 --- a/target/arm/tcg/arith_helper.c +++ b/target/arm/tcg/arith_helper.c @@ -8,11 +8,9 @@ #include "qemu/osdep.h" #include "qemu/bswap.h" #include "qemu/crc32c.h" +#include "helper.h" #include /* for crc32 */ =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* * Note that signed overflow is undefined in C. The following routines are * careful to use unsigned types where modulo arithmetic is required. diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 3428bd1bf0..11977cb772 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -15,11 +15,9 @@ #include "tcg/tcg-gvec-desc.h" #include "crypto/aes-round.h" #include "crypto/sm4.h" +#include "helper.h" #include "vec_internal.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - union CRYPTO_STATE { uint8_t bytes[16]; uint32_t words[4]; diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 7dfb291a9b..5214e3c08a 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -8,15 +8,13 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "cpregs.h" #include "exec/watchpoint.h" #include "system/tcg.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) { diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 07ddfb895d..2dec587d38 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -21,7 +21,7 @@ #include "qemu/units.h" #include "cpu.h" #include "gdbstub/helpers.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "helper-a64.h" #include "qemu/host-utils.h" #include "qemu/log.h" diff --git a/target/arm/tcg/helper.h b/target/arm/tcg/helper-defs.h similarity index 100% rename from target/arm/tcg/helper.h rename to target/arm/tcg/helper-defs.h diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 5c9b9bec3b..7e6f8d3647 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -7,15 +7,13 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" #include "cpregs.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - static inline bool fgt_svc(CPUARMState *env, int el) { /* diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 0c3832a47f..a0cb8cb021 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -8,10 +8,10 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "gdbstub/helpers.h" -#include "exec/helper-proto.h" #include "qemu/main-loop.h" #include "qemu/bitops.h" #include "qemu/log.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 01b7f099f4..a9fb979f63 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "exec/target_page.h" #include "exec/page-protection.h" @@ -32,7 +33,6 @@ #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "helper-a64.h" -#include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" #include "qapi/error.h" diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index f33642df1f..a67d90d6c7 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -19,10 +19,10 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "helper-mve.h" #include "internals.h" #include "vec_internal.h" -#include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" #include "tcg/tcg.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index 8d288f3a70..69147969b2 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -9,13 +9,11 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "vec_internal.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) =20 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index c7ab462d1d..4d70863506 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "exec/target_page.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 5a20117ae8..67c0d59d9e 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -19,11 +19,11 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" #include "helper-a64.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" =20 diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 2d40930157..bca6058e41 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -18,7 +18,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "kvm-consts.h" #include "qemu/main-loop.h" #include "system/runstate.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 7729732369..ab5999c592 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "internals.h" #include "tcg/tcg-gvec-desc.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "helper-sme.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/helper-retaddr.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 16e528e41a..062d8881bd 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -21,9 +21,9 @@ #include "cpu.h" #include "internals.h" #include "exec/page-protection.h" -#include "exec/helper-proto.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" +#include "helper.h" #include "helper-a64.h" #include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 5c689d3b69..565954269f 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -7,12 +7,10 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* * Returns true if the stage 1 translation regime is using LPAE format page * tables. Used when raising alignment exceptions, whose FSR changes depen= ding diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 580ec86c68..3f57006f9d 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -26,14 +26,10 @@ #include "arm_ldst.h" #include "semihosting/semihost.h" #include "cpregs.h" -#include "exec/helper-proto.h" #include "exec/target_page.h" +#include "helper.h" #include "helper-mve.h" =20 -#define HELPER_H "helper.h" -#include "exec/helper-info.c.inc" -#undef HELPER_H - #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ @@ -45,6 +41,9 @@ #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7) #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) =20 +#define HELPER_H "tcg/helper-defs.h" +#include "exec/helper-info.c.inc" + /* These are TCG globals which alias CPUARMState fields */ static TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 1e30d7c77c..027769271c 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -6,7 +6,7 @@ #include "tcg/tcg-op-gvec.h" #include "exec/translator.h" #include "exec/translation-block.h" -#include "exec/helper-gen.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" =20 diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index a070ac9057..1223b843bf 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "helper-a64.h" #include "helper-sme.h" #include "helper-sve.h" diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c index e156e3774a..45f2eb0930 100644 --- a/target/arm/tcg/vfp_helper.c +++ b/target/arm/tcg/vfp_helper.c @@ -19,14 +19,12 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "fpu/softfloat.h" #include "qemu/log.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* * Set the float_status behaviour to match the Arm defaults: * * tininess-before-rounding --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497316; cv=none; d=zohomail.com; s=zohoarc; b=JbiX99/XgkWZfwy2eRJw1QVibG8K1mG779LeJxggnl9oBy0R9NyyvOPVr8h8alQ6dt73TJrJIl8ePZTeiEcc1ooKjvp/AXWZbIVhRXEon+74jSdf8zyaugVk2V0nJK3ofrILSzikukM5kIOnqFwy6KPA22vdm9WJdEgkPHdCYmE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497316; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Tl1QTdBu/A3YjP4FZP2qrs7CaNqhB3P7oxPurKt73ug=; b=NtAlABk1S9IOnrRXKl10g+O/SBwdgkPVFbmoZqUPmHJy0cZFfe8LySoAQW2xP8KJeso+97ZSgyl8Nx3fXjLFdUwnMbWBJDdOV+G+kTi/HkD929ccdOOS3slxBX/YrEnz76xJGjYhvOVKkErRzGKG/ciE4MkWcrJMro+oEHI1rqg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497316687335.36839383952486; Thu, 19 Feb 2026 02:35:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Mo-0007O5-8p; Thu, 19 Feb 2026 05:34:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1Mi-0007Kp-WF for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:37 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1Mf-00068N-IQ for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:36 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-48371119eacso7373875e9.2 for ; Thu, 19 Feb 2026 02:34:32 -0800 (PST) Received: from lanath.. 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Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-10-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/meson.build | 5 +---- target/arm/tcg/psci.c | 2 +- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 6e9aed3e5d..85277dba8d 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -49,10 +49,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sve_helper.c', )) =20 -arm_system_ss.add(files( - 'psci.c', -)) - arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) =20 @@ -68,6 +64,7 @@ arm_common_system_ss.add(files( 'debug.c', 'hflags.c', 'neon_helper.c', + 'psci.c', 'tlb_helper.c', 'tlb-insns.c', 'vfp_helper.c', diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index bca6058e41..56754bde95 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -68,7 +68,7 @@ void arm_handle_psci_call(ARMCPU *cpu) CPUARMState *env =3D &cpu->env; uint64_t param[4]; uint64_t context_id, mpidr; - target_ulong entry; + uint64_t entry; int32_t ret =3D 0; int i; =20 --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497504; cv=none; d=zohomail.com; s=zohoarc; b=Fv6uPGp/VUvvqRARK/uTqfCspsiZBqgKllPY9eCQ+XlCllR4brrOIavEJuR/0+j9gMylrn2UDzVdXs4BDrYlVKRP4TWsnPaCc5ZDS+ZarCTsis3Gz2MBOOl2frfxSuGfhxArK5iXankw5wFz9g8oYrfQSt8cmD/GkSuNYhgR+UA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497504; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=uewsi/mPGL3ids9kCkc0fCnRUOxmgBIwrJlT0/lGETM=; b=NYxUZSCh9EHGGmWFmCBOULA6x5uz8wOA4lU8tTBiMR+XzdsYQKaco4vJZTvhXgJ183seUZ3S5fyZDAv01UFh5G/WksNcQv1noZNNT0WSctgfDO+aLpFZTNX48MM8iLE1RfyI2aMIb4Tv+HpLJgVUaNGds0gYfdExtvXYEb57TH8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177149750399361.247798267445205; Thu, 19 Feb 2026 02:38:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1Ml-0007Mq-39; Thu, 19 Feb 2026 05:34:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1Mj-0007Kq-02 for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:37 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1Mf-00068R-JH for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:36 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-4806ce0f97bso5838885e9.0 for ; Thu, 19 Feb 2026 02:34:32 -0800 (PST) Received: from lanath.. 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Thu, 19 Feb 2026 02:34:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/32] target/arm/tcg/cpu-v7m.c: make compilation unit common Date: Thu, 19 Feb 2026 10:34:01 +0000 Message-ID: <20260219103405.3793357-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497504985158500 From: Pierrick Bouvier Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-11-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 85277dba8d..cabf65e623 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -49,7 +49,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sve_helper.c', )) =20 -arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) +arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c= ')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) =20 arm_common_ss.add(zlib) --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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As well, DO_3OP_PAIR was defined twice, so rename the second variant to DO_3OP_PAIR_NO_STATUS to reflect what it does. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-12-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/meson.build | 4 +- target/arm/tcg/vec_helper.c | 225 +++------------------------------- target/arm/tcg/vec_helper64.c | 142 +++++++++++++++++++++ target/arm/tcg/vec_internal.h | 49 ++++++++ 4 files changed, 212 insertions(+), 208 deletions(-) create mode 100644 target/arm/tcg/vec_helper64.c diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index cabf65e623..5f59156055 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -33,7 +33,6 @@ arm_ss.add(files( 'm_helper.c', 'mve_helper.c', 'op_helper.c', - 'vec_helper.c', )) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( @@ -47,6 +46,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'pauth_helper.c', 'sme_helper.c', 'sve_helper.c', + 'vec_helper64.c', )) =20 arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c= ')) @@ -67,6 +67,7 @@ arm_common_system_ss.add(files( 'psci.c', 'tlb_helper.c', 'tlb-insns.c', + 'vec_helper.c', 'vfp_helper.c', )) arm_user_ss.add(files( @@ -74,5 +75,6 @@ arm_user_ss.add(files( 'hflags.c', 'neon_helper.c', 'tlb_helper.c', + 'vec_helper.c', 'vfp_helper.c', )) diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 1223b843bf..91e98d28ae 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -20,9 +20,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "helper.h" -#include "helper-a64.h" -#include "helper-sme.h" -#include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" @@ -1458,18 +1455,6 @@ static float32 float32_rsqrts_nf(float32 op1, float3= 2 op2, float_status *stat) return float32_div(op1, float32_two, stat); } =20 -#define DO_3OP(NAME, FUNC, TYPE) \ -void HELPER(NAME)(void *vd, void *vn, void *vm, = \ - float_status *stat, uint32_t desc) = \ -{ = \ - intptr_t i, oprsz =3D simd_oprsz(desc); = \ - TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ - for (i =3D 0; i < oprsz / sizeof(TYPE); i++) { = \ - d[i] =3D FUNC(n[i], m[i], stat); = \ - } = \ - clear_tail(d, oprsz, simd_maxsz(desc)); = \ -} - DO_3OP(gvec_fadd_b16, bfloat16_add, float16) DO_3OP(gvec_fadd_h, float16_add, float16) DO_3OP(gvec_fadd_s, float32_add, float32) @@ -1541,49 +1526,6 @@ DO_3OP(gvec_recps_nf_s, float32_recps_nf, float32) DO_3OP(gvec_rsqrts_nf_h, float16_rsqrts_nf, float16) DO_3OP(gvec_rsqrts_nf_s, float32_rsqrts_nf, float32) =20 -#ifdef TARGET_AARCH64 -DO_3OP(gvec_fdiv_h, float16_div, float16) -DO_3OP(gvec_fdiv_s, float32_div, float32) -DO_3OP(gvec_fdiv_d, float64_div, float64) - -DO_3OP(gvec_fmulx_h, helper_advsimd_mulxh, float16) -DO_3OP(gvec_fmulx_s, helper_vfp_mulxs, float32) -DO_3OP(gvec_fmulx_d, helper_vfp_mulxd, float64) - -DO_3OP(gvec_recps_h, helper_recpsf_f16, float16) -DO_3OP(gvec_recps_s, helper_recpsf_f32, float32) -DO_3OP(gvec_recps_d, helper_recpsf_f64, float64) - -DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16) -DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32) -DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64) - -DO_3OP(gvec_ah_recps_h, helper_recpsf_ah_f16, float16) -DO_3OP(gvec_ah_recps_s, helper_recpsf_ah_f32, float32) -DO_3OP(gvec_ah_recps_d, helper_recpsf_ah_f64, float64) - -DO_3OP(gvec_ah_rsqrts_h, helper_rsqrtsf_ah_f16, float16) -DO_3OP(gvec_ah_rsqrts_s, helper_rsqrtsf_ah_f32, float32) -DO_3OP(gvec_ah_rsqrts_d, helper_rsqrtsf_ah_f64, float64) - -DO_3OP(gvec_ah_fmax_h, helper_vfp_ah_maxh, float16) -DO_3OP(gvec_ah_fmax_s, helper_vfp_ah_maxs, float32) -DO_3OP(gvec_ah_fmax_d, helper_vfp_ah_maxd, float64) - -DO_3OP(gvec_ah_fmin_h, helper_vfp_ah_minh, float16) -DO_3OP(gvec_ah_fmin_s, helper_vfp_ah_mins, float32) -DO_3OP(gvec_ah_fmin_d, helper_vfp_ah_mind, float64) - -DO_3OP(gvec_fmax_b16, bfloat16_max, bfloat16) -DO_3OP(gvec_fmin_b16, bfloat16_min, bfloat16) -DO_3OP(gvec_fmaxnum_b16, bfloat16_maxnum, bfloat16) -DO_3OP(gvec_fminnum_b16, bfloat16_minnum, bfloat16) -DO_3OP(gvec_ah_fmax_b16, helper_sme2_ah_fmax_b16, bfloat16) -DO_3OP(gvec_ah_fmin_b16, helper_sme2_ah_fmin_b16, bfloat16) - -#endif -#undef DO_3OP - /* Non-fused multiply-add (unlike float16_muladd etc, which are fused) */ static float16 float16_muladd_nf(float16 dest, float16 op1, float16 op2, float_status *stat) @@ -1769,23 +1711,6 @@ DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, H8) =20 #undef DO_MLA_IDX =20 -#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) = \ -void HELPER(NAME)(void *vd, void *vn, void *vm, = \ - float_status *stat, uint32_t desc) = \ -{ = \ - intptr_t i, j, oprsz =3D simd_oprsz(desc); = \ - intptr_t segment =3D MIN(16, oprsz) / sizeof(TYPE); = \ - intptr_t idx =3D simd_data(desc); = \ - TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ - for (i =3D 0; i < oprsz / sizeof(TYPE); i +=3D segment) { = \ - TYPE mm =3D m[H(i + idx)]; = \ - for (j =3D 0; j < segment; j++) { = \ - d[i + j] =3D ADD(d[i + j], MUL(n[i + j], mm, stat), stat); = \ - } = \ - } = \ - clear_tail(d, oprsz, simd_maxsz(desc)); = \ -} - #define nop(N, M, S) (M) =20 DO_FMUL_IDX(gvec_fmul_idx_b16, nop, bfloat16_mul, float16, H2) @@ -1793,14 +1718,6 @@ DO_FMUL_IDX(gvec_fmul_idx_h, nop, float16_mul, float= 16, H2) DO_FMUL_IDX(gvec_fmul_idx_s, nop, float32_mul, float32, H4) DO_FMUL_IDX(gvec_fmul_idx_d, nop, float64_mul, float64, H8) =20 -#ifdef TARGET_AARCH64 - -DO_FMUL_IDX(gvec_fmulx_idx_h, nop, helper_advsimd_mulxh, float16, H2) -DO_FMUL_IDX(gvec_fmulx_idx_s, nop, helper_vfp_mulxs, float32, H4) -DO_FMUL_IDX(gvec_fmulx_idx_d, nop, helper_vfp_mulxd, float64, H8) - -#endif - #undef nop =20 /* @@ -1812,8 +1729,6 @@ DO_FMUL_IDX(gvec_fmla_nf_idx_s, float32_add, float32_= mul, float32, H4) DO_FMUL_IDX(gvec_fmls_nf_idx_h, float16_sub, float16_mul, float16, H2) DO_FMUL_IDX(gvec_fmls_nf_idx_s, float32_sub, float32_mul, float32, H4) =20 -#undef DO_FMUL_IDX - #define DO_FMLA_IDX(NAME, TYPE, H, NEGX, NEGF) = \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, = \ float_status *stat, uint32_t desc) = \ @@ -2530,31 +2445,6 @@ void HELPER(neon_pmull_h)(void *vd, void *vn, void *= vm, uint32_t desc) clear_tail(d, 16, simd_maxsz(desc)); } =20 -#ifdef TARGET_AARCH64 -void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) -{ - int shift =3D simd_data(desc) * 8; - intptr_t i, opr_sz =3D simd_oprsz(desc); - uint64_t *d =3D vd, *n =3D vn, *m =3D vm; - - for (i =3D 0; i < opr_sz / 8; ++i) { - d[i] =3D clmul_8x4_even(n[i] >> shift, m[i] >> shift); - } -} - -void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, uint32_t desc) -{ - intptr_t sel =3D H4(simd_data(desc)); - intptr_t i, opr_sz =3D simd_oprsz(desc); - uint32_t *n =3D vn, *m =3D vm; - uint64_t *d =3D vd; - - for (i =3D 0; i < opr_sz / 8; ++i) { - d[i] =3D clmul_32(n[2 * i + sel], m[2 * i + sel]); - } -} -#endif - #define DO_CMP0(NAME, TYPE, OP) \ void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ { \ @@ -2628,26 +2518,6 @@ DO_ABA(gvec_uaba_d, uint64_t) =20 #undef DO_ABA =20 -#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ -void HELPER(NAME)(void *vd, void *vn, void *vm, = \ - float_status *stat, uint32_t desc) = \ -{ = \ - ARMVectorReg scratch; = \ - intptr_t oprsz =3D simd_oprsz(desc); = \ - intptr_t half =3D oprsz / sizeof(TYPE) / 2; = \ - TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ - if (unlikely(d =3D=3D m)) { = \ - m =3D memcpy(&scratch, m, oprsz); = \ - } = \ - for (intptr_t i =3D 0; i < half; ++i) { = \ - d[H(i)] =3D FUNC(n[H(i * 2)], n[H(i * 2 + 1)], stat); = \ - } = \ - for (intptr_t i =3D 0; i < half; ++i) { = \ - d[H(i + half)] =3D FUNC(m[H(i * 2)], m[H(i * 2 + 1)], stat); = \ - } = \ - clear_tail(d, oprsz, simd_maxsz(desc)); = \ -} - DO_3OP_PAIR(gvec_faddp_h, float16_add, float16, H2) DO_3OP_PAIR(gvec_faddp_s, float32_add, float32, H4) DO_3OP_PAIR(gvec_faddp_d, float64_add, float64, ) @@ -2668,19 +2538,7 @@ DO_3OP_PAIR(gvec_fminnump_h, float16_minnum, float16= , H2) DO_3OP_PAIR(gvec_fminnump_s, float32_minnum, float32, H4) DO_3OP_PAIR(gvec_fminnump_d, float64_minnum, float64, ) =20 -#ifdef TARGET_AARCH64 -DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2) -DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4) -DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, ) - -DO_3OP_PAIR(gvec_ah_fminp_h, helper_vfp_ah_minh, float16, H2) -DO_3OP_PAIR(gvec_ah_fminp_s, helper_vfp_ah_mins, float32, H4) -DO_3OP_PAIR(gvec_ah_fminp_d, helper_vfp_ah_mind, float64, ) -#endif - -#undef DO_3OP_PAIR - -#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ +#define DO_3OP_PAIR_NO_STATUS(NAME, FUNC, TYPE, H) \ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ { \ ARMVectorReg scratch; \ @@ -2700,29 +2558,29 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uin= t32_t desc) \ } =20 #define ADD(A, B) (A + B) -DO_3OP_PAIR(gvec_addp_b, ADD, uint8_t, H1) -DO_3OP_PAIR(gvec_addp_h, ADD, uint16_t, H2) -DO_3OP_PAIR(gvec_addp_s, ADD, uint32_t, H4) -DO_3OP_PAIR(gvec_addp_d, ADD, uint64_t, ) +DO_3OP_PAIR_NO_STATUS(gvec_addp_b, ADD, uint8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_addp_h, ADD, uint16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_addp_s, ADD, uint32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_addp_d, ADD, uint64_t, /**/) #undef ADD =20 -DO_3OP_PAIR(gvec_smaxp_b, MAX, int8_t, H1) -DO_3OP_PAIR(gvec_smaxp_h, MAX, int16_t, H2) -DO_3OP_PAIR(gvec_smaxp_s, MAX, int32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_smaxp_b, MAX, int8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_smaxp_h, MAX, int16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_smaxp_s, MAX, int32_t, H4) =20 -DO_3OP_PAIR(gvec_umaxp_b, MAX, uint8_t, H1) -DO_3OP_PAIR(gvec_umaxp_h, MAX, uint16_t, H2) -DO_3OP_PAIR(gvec_umaxp_s, MAX, uint32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_umaxp_b, MAX, uint8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_umaxp_h, MAX, uint16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_umaxp_s, MAX, uint32_t, H4) =20 -DO_3OP_PAIR(gvec_sminp_b, MIN, int8_t, H1) -DO_3OP_PAIR(gvec_sminp_h, MIN, int16_t, H2) -DO_3OP_PAIR(gvec_sminp_s, MIN, int32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_sminp_b, MIN, int8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_sminp_h, MIN, int16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_sminp_s, MIN, int32_t, H4) =20 -DO_3OP_PAIR(gvec_uminp_b, MIN, uint8_t, H1) -DO_3OP_PAIR(gvec_uminp_h, MIN, uint16_t, H2) -DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_uminp_b, MIN, uint8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_uminp_h, MIN, uint16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_uminp_s, MIN, uint32_t, H4) =20 -#undef DO_3OP_PAIR +#undef DO_3OP_PAIR_NO_STATUS =20 #define DO_VCVT_FIXED(NAME, FUNC, TYPE) \ void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t des= c) \ @@ -2797,53 +2655,6 @@ DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32= _t) =20 #undef DO_VRINT_RMODE =20 -#ifdef TARGET_AARCH64 -void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc) -{ - const uint8_t *indices =3D vm; - size_t oprsz =3D simd_oprsz(desc); - uint32_t rn =3D extract32(desc, SIMD_DATA_SHIFT, 5); - bool is_tbx =3D extract32(desc, SIMD_DATA_SHIFT + 5, 1); - uint32_t table_len =3D desc >> (SIMD_DATA_SHIFT + 6); - union { - uint8_t b[16]; - uint64_t d[2]; - } result; - - /* - * We must construct the final result in a temp, lest the output - * overlaps the input table. For TBL, begin with zero; for TBX, - * begin with the original register contents. Note that we always - * copy 16 bytes here to avoid an extra branch; clearing the high - * bits of the register for oprsz =3D=3D 8 is handled below. - */ - if (is_tbx) { - memcpy(&result, vd, 16); - } else { - memset(&result, 0, 16); - } - - for (size_t i =3D 0; i < oprsz; ++i) { - uint32_t index =3D indices[H1(i)]; - - if (index < table_len) { - /* - * Convert index (a byte offset into the virtual table - * which is a series of 128-bit vectors concatenated) - * into the correct register element, bearing in mind - * that the table can wrap around from V31 to V0. - */ - const uint8_t *table =3D (const uint8_t *) - aa64_vfp_qreg(env, (rn + (index >> 4)) % 32); - result.b[H1(i)] =3D table[H1(index % 16)]; - } - } - - memcpy(vd, &result, 16); - clear_tail(vd, oprsz, simd_maxsz(desc)); -} -#endif - /* * NxN -> N highpart multiply * diff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c new file mode 100644 index 0000000000..249a257177 --- /dev/null +++ b/target/arm/tcg/vec_helper64.c @@ -0,0 +1,142 @@ +/* + * ARM AdvSIMD / SVE Vector Operations + * + * Copyright (c) 2026 Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "helper.h" +#include "helper-a64.h" +#include "helper-sme.h" +#include "helper-sve.h" +#include "tcg/tcg-gvec-desc.h" +#include "fpu/softfloat.h" +#include "qemu/int128.h" +#include "crypto/clmul.h" +#include "vec_internal.h" + +DO_3OP(gvec_fdiv_h, float16_div, float16) +DO_3OP(gvec_fdiv_s, float32_div, float32) +DO_3OP(gvec_fdiv_d, float64_div, float64) + +DO_3OP(gvec_fmulx_h, helper_advsimd_mulxh, float16) +DO_3OP(gvec_fmulx_s, helper_vfp_mulxs, float32) +DO_3OP(gvec_fmulx_d, helper_vfp_mulxd, float64) + +DO_3OP(gvec_recps_h, helper_recpsf_f16, float16) +DO_3OP(gvec_recps_s, helper_recpsf_f32, float32) +DO_3OP(gvec_recps_d, helper_recpsf_f64, float64) + +DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16) +DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32) +DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64) + +DO_3OP(gvec_ah_recps_h, helper_recpsf_ah_f16, float16) +DO_3OP(gvec_ah_recps_s, helper_recpsf_ah_f32, float32) +DO_3OP(gvec_ah_recps_d, helper_recpsf_ah_f64, float64) + +DO_3OP(gvec_ah_rsqrts_h, helper_rsqrtsf_ah_f16, float16) +DO_3OP(gvec_ah_rsqrts_s, helper_rsqrtsf_ah_f32, float32) +DO_3OP(gvec_ah_rsqrts_d, helper_rsqrtsf_ah_f64, float64) + +DO_3OP(gvec_ah_fmax_h, helper_vfp_ah_maxh, float16) +DO_3OP(gvec_ah_fmax_s, helper_vfp_ah_maxs, float32) +DO_3OP(gvec_ah_fmax_d, helper_vfp_ah_maxd, float64) + +DO_3OP(gvec_ah_fmin_h, helper_vfp_ah_minh, float16) +DO_3OP(gvec_ah_fmin_s, helper_vfp_ah_mins, float32) +DO_3OP(gvec_ah_fmin_d, helper_vfp_ah_mind, float64) + +DO_3OP(gvec_fmax_b16, bfloat16_max, bfloat16) +DO_3OP(gvec_fmin_b16, bfloat16_min, bfloat16) +DO_3OP(gvec_fmaxnum_b16, bfloat16_maxnum, bfloat16) +DO_3OP(gvec_fminnum_b16, bfloat16_minnum, bfloat16) +DO_3OP(gvec_ah_fmax_b16, helper_sme2_ah_fmax_b16, bfloat16) +DO_3OP(gvec_ah_fmin_b16, helper_sme2_ah_fmin_b16, bfloat16) + +#define nop(N, M, S) (M) + +DO_FMUL_IDX(gvec_fmulx_idx_h, nop, helper_advsimd_mulxh, float16, H2) +DO_FMUL_IDX(gvec_fmulx_idx_s, nop, helper_vfp_mulxs, float32, H4) +DO_FMUL_IDX(gvec_fmulx_idx_d, nop, helper_vfp_mulxd, float64, H8) + +#undef nop + +void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + int shift =3D simd_data(desc) * 8; + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 8; ++i) { + d[i] =3D clmul_8x4_even(n[i] >> shift, m[i] >> shift); + } +} + +void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t sel =3D H4(simd_data(desc)); + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint32_t *n =3D vn, *m =3D vm; + uint64_t *d =3D vd; + + for (i =3D 0; i < opr_sz / 8; ++i) { + d[i] =3D clmul_32(n[2 * i + sel], m[2 * i + sel]); + } +} + +DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2) +DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4) +DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, /**/) + +DO_3OP_PAIR(gvec_ah_fminp_h, helper_vfp_ah_minh, float16, H2) +DO_3OP_PAIR(gvec_ah_fminp_s, helper_vfp_ah_mins, float32, H4) +DO_3OP_PAIR(gvec_ah_fminp_d, helper_vfp_ah_mind, float64, /**/) + +void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc) +{ + const uint8_t *indices =3D vm; + size_t oprsz =3D simd_oprsz(desc); + uint32_t rn =3D extract32(desc, SIMD_DATA_SHIFT, 5); + bool is_tbx =3D extract32(desc, SIMD_DATA_SHIFT + 5, 1); + uint32_t table_len =3D desc >> (SIMD_DATA_SHIFT + 6); + union { + uint8_t b[16]; + uint64_t d[2]; + } result; + + /* + * We must construct the final result in a temp, lest the output + * overlaps the input table. For TBL, begin with zero; for TBX, + * begin with the original register contents. Note that we always + * copy 16 bytes here to avoid an extra branch; clearing the high + * bits of the register for oprsz =3D=3D 8 is handled below. + */ + if (is_tbx) { + memcpy(&result, vd, 16); + } else { + memset(&result, 0, 16); + } + + for (size_t i =3D 0; i < oprsz; ++i) { + uint32_t index =3D indices[H1(i)]; + + if (index < table_len) { + /* + * Convert index (a byte offset into the virtual table + * which is a series of 128-bit vectors concatenated) + * into the correct register element, bearing in mind + * that the table can wrap around from V31 to V0. + */ + const uint8_t *table =3D (const uint8_t *) + aa64_vfp_qreg(env, (rn + (index >> 4)) % 32); + result.b[H1(i)] =3D table[H1(index % 16)]; + } + } + + memcpy(vd, &result, 16); + clear_tail(vd, oprsz, simd_maxsz(desc)); +} diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index cf41b03dbc..4edd2b4fc1 100644 --- a/target/arm/tcg/vec_internal.h +++ b/target/arm/tcg/vec_internal.h @@ -450,4 +450,53 @@ static inline void depositn(uint64_t *p, unsigned pos, } } =20 +#define DO_3OP(NAME, FUNC, TYPE) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, = \ + float_status * stat, uint32_t desc) = \ +{ = \ + intptr_t i, oprsz =3D simd_oprsz(desc); = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + for (i =3D 0; i < oprsz / sizeof(TYPE); i++) { = \ + d[i] =3D FUNC(n[i], m[i], stat); = \ + } = \ + clear_tail(d, oprsz, simd_maxsz(desc)); = \ +} + +#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, = \ + float_status * stat, uint32_t desc) = \ +{ = \ + ARMVectorReg scratch; = \ + intptr_t oprsz =3D simd_oprsz(desc); = \ + intptr_t half =3D oprsz / sizeof(TYPE) / 2; = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + if (unlikely(d =3D=3D m)) { = \ + m =3D memcpy(&scratch, m, oprsz); = \ + } = \ + for (intptr_t i =3D 0; i < half; ++i) { = \ + d[H(i)] =3D FUNC(n[H(i * 2)], n[H(i * 2 + 1)], stat); = \ + } = \ + for (intptr_t i =3D 0; i < half; ++i) { = \ + d[H(i + half)] =3D FUNC(m[H(i * 2)], m[H(i * 2 + 1)], stat); = \ + } = \ + clear_tail(d, oprsz, simd_maxsz(desc)); = \ +} + +#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) = \ +void HELPER(NAME)(void *vd, void *vn, void *vm, = \ + float_status * stat, uint32_t desc) = \ +{ = \ + intptr_t i, j, oprsz =3D simd_oprsz(desc); = \ + intptr_t segment =3D MIN(16, oprsz) / sizeof(TYPE); = \ + intptr_t idx =3D simd_data(desc); = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + for (i =3D 0; i < oprsz / sizeof(TYPE); i +=3D segment) { = \ + TYPE mm =3D m[H(i + idx)]; = \ + for (j =3D 0; j < segment; j++) { = \ + d[i + j] =3D ADD(d[i + j], MUL(n[i + j], mm, stat), stat); = \ + } = \ + } = \ + clear_tail(d, oprsz, simd_maxsz(desc)); = \ +} + #endif /* TARGET_ARM_VEC_INTERNAL_H */ --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497381; cv=none; d=zohomail.com; s=zohoarc; b=YKq7qelHqW58EQ/zOzh6Ywdoy+bjbdfPiT7kbqjXtZBqfyvHaTDli5TRiY7kVYXf3Ht6lqfdWj1I2gPmx5QYvCTmW70xoZR39kX8fow/4j5HRC37uDk9FeeQGiFXt1hveZ0nUnEKc3VCnxjbW6WV+I5nMbuyZ64wfqyVsQBana8= ARC-Message-Signature: i=1; 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For convenience, the @@ -56,8 +56,8 @@ typedef struct DisasContext { * pc_save contains -1 to indicate that relative updates are no * longer possible. */ - target_ulong pc_save; - target_ulong page_start; + vaddr pc_save; + vaddr page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497373; cv=none; d=zohomail.com; s=zohoarc; b=U/BZ2q4lTmPG+zPt4sF3/UVfIL8ieq8aOkvW78XuM9D0sYaIxT+B55evvIpdOHClq7+b7Bw+rtxAWiT9QmAx1HIStda2W8X6v6DbfVOOlaM5WbkPAuJfdPxIRElknn3Go1cf40kSzHpMOZQiLmRauXUH3sO/M4JkvZKZrvL6aHI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497373; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=xR5QBMtIJ7RHzFIkSy3EPbY45TMgkx+1i2QYsMhumRY=; b=kZaXOANuXMteDyOV6H4N1VwDH91KtmQodbCaJTctYQQzt+yXSaAJMERcjgTzS4T3TTA4H1tnKS6jC5CH/Lk9kc+cimwvYoM6VNYT2GzOpIxIWjGz4iaCdaUzAY96Ufc3hRh65aikPzbikip4kZt9Owm+W5/YQYrJsA0BsJBFfXc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497373910363.8973978803672; Thu, 19 Feb 2026 02:36:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1NL-0007sW-MG; Thu, 19 Feb 2026 05:35:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1Mk-0007Md-Pb for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:38 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1Mi-00069l-NB for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:38 -0500 Received: by mail-wm1-x341.google.com with SMTP id 5b1f17b1804b1-4833115090dso7659325e9.3 for ; Thu, 19 Feb 2026 02:34:35 -0800 (PST) Received: from lanath.. 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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd34sm697630795e9.7.2026.02.19.02.34.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Feb 2026 02:34:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771497274; x=1772102074; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xR5QBMtIJ7RHzFIkSy3EPbY45TMgkx+1i2QYsMhumRY=; b=AkV0c7/zegn53grst/XGE3n90qszGQRVmpnqCkDcAUZYus33ScooDq5j52c8Lx+lfR dYcpF+7kBI40TGWwrHE6Z1qNYNoJwcoHp5EK1FxoXlJN5pEMxvUfSNlIvLsO2iiPeKwk dNPErIxtU5Ejxia60qLxR/mBlciLbX6HWtF6JgEma3JqYkwKMpEN32YCUHI4yOACZg1C GH9l3qTgYRRfp17pqpislEvbXxD/bWsHZYmfwYKKDr1eoj1CEeyuylPNJJg6Uu+LZLNP pg0N+KDz+Tov2QXHRbg+HOP1AGc/PPEkL1xw4Ny6UF2sKhl69XWf4JTfYXABBRz+/4Ah zXMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771497274; x=1772102074; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=xR5QBMtIJ7RHzFIkSy3EPbY45TMgkx+1i2QYsMhumRY=; b=K3a3tAh+vO5FwgGsiRKmEaKHgbzw+qmVEEir+ik23v0s0Oji2haWHOv+WZBJPmruPf 76hNsxwOCcB31Jmi/hLEpVo75s/IdhPnyGbyNRGfbrmOAMbGL6GN8lGGhVksbTi1mD/8 Bl8xromEZQM+cQUn7tZ4gb8fj46gdHcB+IlrJUNBs74i90Jy8jLu0l4s+BoGA3f4ZAeC pXL0DuB9dAC8s+O2ZzIZ54y13P5rNRexNcTjrRpgTPYU8TxJJoYLHDEW4LpfuA94JgZq JLBOmiTonlwzckpDcXOPXtw6851RMqlXp/lai4gK4lghQraFotBOyQSmq5DSsBtvL6n+ cApg== X-Gm-Message-State: AOJu0YwQdzpgGaN9OO6qonyHS2w7LM6ZsNfqm/T6Z2jGhZyiRt2efb/d 1bIgI96t2CdgE/+PNfo+NSImSvQi6OeuBvhxZkeQe0XyBEWXJAHdHx01VgSWRSR2P0Foub2ROnj +BGR2aes= X-Gm-Gg: AZuq6aJY1eXbiHnO1X3T2sM5SbzeJ6hJCeKdNGrFYdk0tXtmLt8wwhGX92D6Kk2iwSI NS6ZfNFPn4ESTX3OeEaHqgUU8DtvdcPcViWTvT8YDP5hgKIhDQyl+MDWDQPx7KGiH1qGpAL+0un fQIU7iFevvgoYjE2qGun2KYu40bYD+88/EUpJRS0xs0cvEBU3/gIeLufDL8BeR854ZqJC7kFSHk mdMHGa+1baKMFJsYlM9ECg6pmEW/X4s+NvonlZsBjNA3Muidd6cmAf/dfSKhrLZjRorxDjJigzu X4x3K6Yek9bkKjgTyShsvmhGz9GeSJinsjl/za/GKDD5NIQHFg+HKs08jnZnlx/darygjjN/D5h t39NSLjP8fc+vQql1ubWzggGCrH60bvNlVbB5u4G9k47B4J0fnREkmOLqGOqNyDDlwKjept4set AMoNBCGb2a9SgvvuqLZ/JOBhyyp/4SitN4Xh/ZDhpW9VHCJRIanqKovjQ43aDzDgicwBTty9Aqn ZHOOAbtDp1XJ4G88C3AEDEhi42shrA= X-Received: by 2002:a05:600c:8b26:b0:465:a51d:d4 with SMTP id 5b1f17b1804b1-48398a47222mr70596375e9.6.1771497274382; Thu, 19 Feb 2026 02:34:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/32] target/arm/tcg/translate.h: replace target_long with int64_t Date: Thu, 19 Feb 2026 10:34:04 +0000 Message-ID: <20260219103405.3793357-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260219103405.3793357-1-peter.maydell@linaro.org> References: <20260219103405.3793357-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771497374501158501 From: Pierrick Bouvier target_long is used to represent a pc diff. Checked all call sites to make sure we were already passing signed values, so extending works as expected. Use vaddr for pc_curr and pc_save. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-14-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a32.h | 2 +- target/arm/tcg/translate.c | 18 +++++++++--------- target/arm/tcg/translate.h | 12 ++++++------ 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h index 0b1fa57965..a8df364171 100644 --- a/target/arm/tcg/translate-a32.h +++ b/target/arm/tcg/translate-a32.h @@ -40,7 +40,7 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele,= MemOp memop); TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); void gen_set_cpsr(TCGv_i32 var, uint32_t mask); void gen_set_condexec(DisasContext *s); -void gen_update_pc(DisasContext *s, target_long diff); +void gen_update_pc(DisasContext *s, int64_t diff); void gen_lookup_tb(DisasContext *s); long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 3f57006f9d..f9d1b8897d 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -253,12 +253,12 @@ static inline int get_a32_user_mem_index(DisasContext= *s) } =20 /* The pc_curr difference for an architectural jump. */ -static target_long jmp_diff(DisasContext *s, target_long diff) +static int64_t jmp_diff(DisasContext *s, int64_t diff) { return diff + (s->thumb ? 4 : 8); } =20 -static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long di= ff) +static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, int64_t diff) { assert(s->pc_save !=3D -1); if (tb_cflags(s->base.tb) & CF_PCREL) { @@ -738,7 +738,7 @@ void gen_set_condexec(DisasContext *s) } } =20 -void gen_update_pc(DisasContext *s, target_long diff) +void gen_update_pc(DisasContext *s, int64_t diff) { gen_pc_plus_diff(s, cpu_R[15], diff); s->pc_save =3D s->pc_curr + diff; @@ -1058,7 +1058,7 @@ static void gen_exception(int excp, uint32_t syndrome) tcg_constant_i32(syndrome)); } =20 -static void gen_exception_insn_el_v(DisasContext *s, target_long pc_diff, +static void gen_exception_insn_el_v(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn, TCGv_i32 tcg_e= l) { if (s->aarch64) { @@ -1071,14 +1071,14 @@ static void gen_exception_insn_el_v(DisasContext *s= , target_long pc_diff, s->base.is_jmp =3D DISAS_NORETURN; } =20 -void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, +void gen_exception_insn_el(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn, uint32_t target_el) { gen_exception_insn_el_v(s, pc_diff, excp, syn, tcg_constant_i32(target_el)); } =20 -void gen_exception_insn(DisasContext *s, target_long pc_diff, +void gen_exception_insn(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn) { if (s->aarch64) { @@ -1313,7 +1313,7 @@ static void gen_goto_ptr(void) * cpu_loop_exec. Any live exit_requests will be processed as we * enter the next TB. */ -static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, target_long= diff) +static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, int64_t dif= f) { if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) { /* @@ -1340,7 +1340,7 @@ static void gen_goto_tb(DisasContext *s, unsigned tb_= slot_idx, target_long diff) } =20 /* Jump, specifying which TB number to use if we gen_goto_tb() */ -static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno) +static void gen_jmp_tb(DisasContext *s, int64_t diff, int tbno) { if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. = */ @@ -1383,7 +1383,7 @@ static void gen_jmp_tb(DisasContext *s, target_long d= iff, int tbno) } } =20 -static inline void gen_jmp(DisasContext *s, target_long diff) +static inline void gen_jmp(DisasContext *s, int64_t diff) { gen_jmp_tb(s, diff, 0); } diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 2c8358dd7f..3e3094a463 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -27,8 +27,8 @@ typedef struct DisasLabel { typedef struct DisasDelayException { struct DisasDelayException *next; TCGLabel *lab; - target_long pc_curr; - target_long pc_save; + vaddr pc_curr; + vaddr pc_save; int condexec_mask; int condexec_cond; uint32_t excp; @@ -359,14 +359,14 @@ static inline int curr_insn_len(DisasContext *s) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_a64_update_pc(DisasContext *s, target_long diff); +void gen_a64_update_pc(DisasContext *s, int64_t diff); extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } =20 -static inline void gen_a64_update_pc(DisasContext *s, target_long diff) +static inline void gen_a64_update_pc(DisasContext *s, int64_t diff) { } #endif @@ -377,9 +377,9 @@ void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); void gen_exception_internal(int excp); -void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, +void gen_exception_insn_el(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn, uint32_t target_el); -void gen_exception_insn(DisasContext *s, target_long pc_diff, +void gen_exception_insn(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn); TCGLabel *delay_exception_el(DisasContext *s, int excp, uint32_t syn, uint32_t target_el); --=20 2.43.0 From nobody Sun Apr 12 04:23:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771497393; cv=none; d=zohomail.com; s=zohoarc; b=ElYwXhPLUU/UOn7J9dytzkKAurAx87/xgjbEvQ0VTmBdY4DjTtDv+8yCQmI9HT+D+4FybD9GGO406c5hYPsdJgYiXHK8jWofqmPJ7NnFepmaTjj8W4aj5vNeH0JB6vlteML5N5YAfMLMhJEPQO9h2bVKks2kB/XAC2nBxo1IeJg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771497393; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DcpZ76ZwhBhm9PG+qYecXvTyPzyIf3xHlLWtAkqeRJc=; b=TxEWSIAv7I6YpSsvAA1Yao/ICXLEHIXKcuE0nYH5HSUtOjXEbvMQeiqvMid0WYoCf5BvkYXUmig6I+CHAkNo3T4Mf6weFG5aLlcqgLNySdG67z3UZAljbmk28dEdx5qr+dujKjhwab3i3UVEhiPU88cRXqdZzZxR0n/KaFPyoD0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771497393673436.147374584618; Thu, 19 Feb 2026 02:36:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vt1O5-0000kz-9Y; Thu, 19 Feb 2026 05:36:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vt1Ml-0007NC-SL for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:39 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vt1Mi-0006A3-V7 for qemu-devel@nongnu.org; Thu, 19 Feb 2026 05:34:39 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-480706554beso8865765e9.1 for ; Thu, 19 Feb 2026 02:34:36 -0800 (PST) Received: from lanath.. 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Since all arch have a single call site (in translate.c), this is as good documentation as having a single define. The notable exception is target/arm, which has two different translate files for 32/64 bits. Since it's the only one, we accept to have two call sites for this. As well, we update parameter type to use uint64_t instead of target_ulong, so it can be called from common code. Signed-off-by: Pierrick Bouvier Message-id: 20260219040150.2098396-15-pierrick.bouvier@linaro.org Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- include/tcg/tcg-op-common.h | 8 ++++++++ include/tcg/tcg-op.h | 29 ----------------------------- target/alpha/cpu-param.h | 2 -- target/alpha/translate.c | 4 ++-- target/arm/cpu-param.h | 7 ------- target/avr/cpu-param.h | 2 -- target/avr/translate.c | 2 +- target/hexagon/cpu-param.h | 2 -- target/hexagon/translate.c | 2 +- target/hppa/cpu-param.h | 2 -- target/i386/cpu-param.h | 2 -- target/i386/tcg/translate.c | 2 +- target/loongarch/cpu-param.h | 2 -- target/loongarch/tcg/translate.c | 2 +- target/m68k/cpu-param.h | 2 -- target/m68k/translate.c | 2 +- target/microblaze/cpu-param.h | 2 -- target/microblaze/translate.c | 2 +- target/mips/cpu-param.h | 2 -- target/or1k/cpu-param.h | 2 -- target/or1k/translate.c | 2 +- target/ppc/cpu-param.h | 2 -- target/ppc/translate.c | 2 +- target/riscv/cpu-param.h | 7 ------- target/rx/cpu-param.h | 2 -- target/rx/translate.c | 2 +- target/s390x/cpu-param.h | 2 -- target/sh4/cpu-param.h | 2 -- target/sh4/translate.c | 4 ++-- target/sparc/cpu-param.h | 2 -- target/sparc/translate.c | 2 +- target/tricore/cpu-param.h | 2 -- target/tricore/translate.c | 2 +- target/xtensa/cpu-param.h | 2 -- target/xtensa/translate.c | 2 +- 35 files changed, 24 insertions(+), 93 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index f752ef440b..e02f209c09 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -30,6 +30,14 @@ TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t o= ff, const char *name); TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t off, const char *na= me); =20 /* Generic ops. */ +static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, + uint64_t a2) +{ + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); + tcg_set_insn_start_param(op, 0, pc); + tcg_set_insn_start_param(op, 1, a1); + tcg_set_insn_start_param(op, 2, a2); +} =20 void gen_set_label(TCGLabel *l); void tcg_gen_br(TCGLabel *l); diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index ee379994e7..7024be938e 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -28,35 +28,6 @@ # error Mismatch with insn-start-words.h #endif =20 -#if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 -static inline void tcg_gen_insn_start(target_ulong pc) -{ - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); - tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, 0); - tcg_set_insn_start_param(op, 2, 0); -} -#elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 1 -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) -{ - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); - tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, a1); - tcg_set_insn_start_param(op, 2, 0); -} -#elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 2 -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, - target_ulong a2) -{ - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); - tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, a1); - tcg_set_insn_start_param(op, 2, a2); -} -#else -#error Unhandled TARGET_INSN_START_EXTRA_WORDS value -#endif - #if TARGET_LONG_BITS =3D=3D 32 typedef TCGv_i32 TCGv; #define tcg_temp_new() tcg_temp_new_i32() diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index a799f42db3..c9da620ab3 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -24,6 +24,4 @@ # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 4442462891..4d22d7d5a4 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2899,9 +2899,9 @@ static void alpha_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 if (ctx->pcrel) { - tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK); + tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK, 0, 0); } else { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } } =20 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 8b46c7c570..7de0099cbf 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -32,11 +32,4 @@ # define TARGET_PAGE_BITS_LEGACY 10 #endif /* !CONFIG_USER_ONLY */ =20 -/* - * ARM-specific extra insn start words: - * 1: Conditional execution bits - * 2: Partial exception syndrome for data aborts - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index f74bfc2580..ea7887919a 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -25,6 +25,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/avr/translate.c b/target/avr/translate.c index 78ae83df21..649dd4b011 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2689,7 +2689,7 @@ static void avr_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->npc); + tcg_gen_insn_start(ctx->npc, 0, 0); } =20 static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 635d509e74..45ee7b4640 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -23,6 +23,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 2fdc956bf9..8a223f6e13 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -998,7 +998,7 @@ static void hexagon_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 9bf7ac76d0..e0b2c7c915 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -19,6 +19,4 @@ =20 #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index ebb844bcc8..909bc02792 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -22,6 +22,4 @@ #endif #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7186517239..14210d569f 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3501,7 +3501,7 @@ static void i386_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) if (tb_cflags(dcbase->tb) & CF_PCREL) { pc_arg &=3D ~TARGET_PAGE_MASK; } - tcg_gen_insn_start(pc_arg, dc->cc_op); + tcg_gen_insn_start(pc_arg, dc->cc_op, 0); } =20 static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 58cc45a377..071567712b 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -13,6 +13,4 @@ =20 #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index 30f375b33f..b9ed13d19c 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -159,7 +159,7 @@ static void loongarch_tr_insn_start(DisasContextBase *d= cbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 /* diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 256a2b5f8b..7afbf6d302 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -17,6 +17,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/m68k/translate.c b/target/m68k/translate.c index a030993901..abc1c79f3c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6041,7 +6041,7 @@ static void m68k_tr_tb_start(DisasContextBase *dcbase= , CPUState *cpu) static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); } =20 static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index e0a3794513..6a0714bb3d 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -27,6 +27,4 @@ /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0be3c98dc1..2af67beece 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1630,7 +1630,7 @@ static void mb_tr_insn_start(DisasContextBase *dcb, C= PUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); =20 - tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK); + tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK, 0); } =20 static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 58f450827f..a71e7383d2 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -20,6 +20,4 @@ #endif #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/or1k/cpu-param.h b/target/or1k/cpu-param.h index b4f57bbe69..3011bf5fcc 100644 --- a/target/or1k/cpu-param.h +++ b/target/or1k/cpu-param.h @@ -12,6 +12,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/or1k/translate.c b/target/or1k/translate.c index ce2dc466dc..de81dc6ef8 100644 --- a/target/or1k/translate.c +++ b/target/or1k/translate.c @@ -1552,7 +1552,7 @@ static void openrisc_tr_insn_start(DisasContextBase *= dcbase, CPUState *cs) DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) - | (dc->base.num_insns > 1 ? 2 : 0)); + | (dc->base.num_insns > 1 ? 2 : 0), 0); } =20 static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index e4ed9080ee..ca7602d898 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -37,6 +37,4 @@ # define TARGET_PAGE_BITS 12 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e9acfa239e..a09a6df93f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6575,7 +6575,7 @@ static void ppc_tr_tb_start(DisasContextBase *db, CPU= State *cs) =20 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } =20 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index cfdc67c258..039e877891 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -17,13 +17,6 @@ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ =20 -/* - * RISC-V-specific extra insn start words: - * 1: Original instruction opcode - * 2: more information about instruction - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 - /* * The current MMU Modes are: * - U mode 0b000 diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 84934f3bca..ef1970a09e 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -24,6 +24,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/rx/translate.c b/target/rx/translate.c index 26d4154829..a245b9db8f 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2217,7 +2217,7 @@ static void rx_tr_insn_start(DisasContextBase *dcbase= , CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index abfae3bedf..a5f798eeae 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -12,6 +12,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index f328715ee8..2b6e11dd0a 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -16,6 +16,4 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/sh4/translate.c b/target/sh4/translate.c index b3ae0a3814..b1057727c5 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2181,7 +2181,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) * tb->icount * insn_start. */ for (i =3D 1; i < max_insns; ++i) { - tcg_gen_insn_start(pc + i * 2, ctx->envflags); + tcg_gen_insn_start(pc + i * 2, ctx->envflags, 0); ctx->base.insn_start =3D tcg_last_op(); } } @@ -2241,7 +2241,7 @@ static void sh4_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); + tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags, 0); } =20 static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 45eea9d6ba..6e8e2a5146 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -21,6 +21,4 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 57b50ff8b9..7e8558dbbd 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5735,7 +5735,7 @@ static void sparc_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cs) g_assert_not_reached(); } } - tcg_gen_insn_start(dc->pc, npc); + tcg_gen_insn_start(dc->pc, npc, 0); } =20 static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index eb33a67c41..790242ef3d 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -12,6 +12,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 18d8726af6..0eaf7a82f8 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8410,7 +8410,7 @@ static void tricore_tr_insn_start(DisasContextBase *d= cbase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static bool insn_crosses_page(DisasContext *ctx, CPUTriCoreState *env) diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 7a0c22c900..06d85218b8 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -16,6 +16,4 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index bb8d2ed86c..5e3707d3fd 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1159,7 +1159,7 @@ static void xtensa_tr_tb_start(DisasContextBase *dcba= se, CPUState *cpu) =20 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } =20 static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *c= pu) --=20 2.43.0