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[216.71.219.44]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1a73200asm147636225ad.36.2026.02.18.20.02.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Feb 2026 20:02:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771473730; x=1772078530; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eauig3ysS+xxOhSAgs3llLzf1uSxo9TErKgwme08ax4=; b=Kyh0lPhlw3U1+JY3DaMlTHjnH+HH0U/zGGSmT+JPhXX2CZffnmBTSxU+5dOWClpOXw h4U2pL8BjFnpZqfrvLn4gAPV+cwop6A2iigraGD+xW7O6jvkNfO0U9knbyxnx4u3v4OQ ETBRXsoT2v+W0mbRMRI4pZ9fxcxJvigGSGoqJo/R7zQBBm+vAuOsjtyQpvJqctH/8Uks 605CtQm4ezlI48Mobbl8ucxu6bBsnw6Quu75lPJm3+CTchpu37YCy5xNVI5TVZw318Cd 955Nk9xPBhmrXTVkAE5rm+gfM0ao5jAJjSQ1fdHou20g6rsqTYuwP2bF0ANgFcwCt0ip spoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771473730; x=1772078530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=eauig3ysS+xxOhSAgs3llLzf1uSxo9TErKgwme08ax4=; b=I0ZqoENOpLWoduz0SyhqoKYFjG1IDqt0m7wB3aPNEgxoeHxoDTlonR444/PK5YdXc9 eg9YJdZ7xoWN3cKvbUQh+ehn6VkmUDeK2MEZema4axowkM9cPtmJsy3ibSpGBmK9vqkJ bHlMbbFzInwz5o//EYRe0A0RVCgpyGmJmmrcIVYYfPUnnULtJU/yai3SHJzyJbFp3RdM qKW44M/EblDw1q7gUvPCn5zlM9BSUpetPQ/U7/LgqqrtUa1GKaFXy1aZwwI4xXlTEhz2 2CPQ7vgtqrvztGwFkgOftIBL4ha/fWL5X8pmc+dGogKc6VLLnzPDdrFzAFFx779297Nu O4iw== X-Gm-Message-State: AOJu0YxN1EbVqdrw6K3c+Wkv577tPyCRUIt28/vsEA3AsFUyT9u0DuC3 6fyCGed1OWlzh2G0JXqx3vhaZYUvXG+dVtINC7APR5PeHiRxN4WsDm1uQy7bl/P4VY2+duxcxts WV5qm X-Gm-Gg: AZuq6aJULMKqykIqA/IZgQPe/nD8mmpZxKiS6z5+11Wsij8KkblahJijXUqi1GYtuo+ I78ANMCPMKkD6zgkIeyZ0005ZVf4M0c7wCrsFx2brj1dPCs5KCb+YydgHMof4qKv7m4Iqen4d9u a7bPn8AzNBMeKYBMjCO+cQ0/4fkdOWYY5Ao9D3Y3s47wAHKdAhF33Jk5Cb/XWv8NToXETfku91T ssVf3kzoNKzLVMpgpsKBVpzxw1lg07PwDwI214cXIy7yHYGiOyJU5cbFmxIpn8EdzVBm1tMXbRO +1XT0cXgeUo4RMUvpvAE72jfs1BLhOf/xKDAjoqIy9iC4pPJXe1Cushgdmqv5mqdVcHUvLaBgLw tkVx3/t688tRP6p7m3YfMzqs+IMMjMQQiCD92Cxu4dktJGMR6m3vijs4/0kRhi4llD8ErXzdG2h hVbD2j/4e3AmTfeJzfD1xarr5pc1ypOaFUAmSmqMU06fknAHfJoXD/Ir8Bg4fya5ZlkU54zIoBn B1q X-Received: by 2002:a17:903:2284:b0:2aa:df82:ed7a with SMTP id d9443c01a7336-2ad17552e10mr143164445ad.58.1771473729848; Wed, 18 Feb 2026 20:02:09 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , anjo@rev.ng, Peter Maydell , Jim MacArthur Subject: [PATCH v4 01/14] target/arm: Move TCG-specific code out of debug_helper.c Date: Wed, 18 Feb 2026 20:01:37 -0800 Message-ID: <20260219040150.2098396-2-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> References: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771473850580154100 Content-Type: text/plain; charset="utf-8" From: Peter Maydell The target/arm/debug_helper.c file has some code which we need for non-TCG accelerators, but quite a lot which is guarded by a CONFIG_TCG ifdef. Move all this TCG-only code out to a new file target/arm/tcg/debug.c. In particular all the code requiring access to the TCG helper function prototypes is in the moved code, so we can drop the use of tcg/helper.h from debug_helper.c. Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/debug_helper.c | 769 ------------------------------------ target/arm/tcg/debug.c | 782 +++++++++++++++++++++++++++++++++++++ target/arm/tcg/meson.build | 2 + 3 files changed, 784 insertions(+), 769 deletions(-) create mode 100644 target/arm/tcg/debug.c diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 579516e1541..352c8e5c8e7 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -14,775 +14,6 @@ #include "exec/watchpoint.h" #include "system/tcg.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - -#ifdef CONFIG_TCG -/* Return the Exception Level targeted by debug exceptions. */ -static int arm_debug_target_el(CPUARMState *env) -{ - bool secure =3D arm_is_secure(env); - bool route_to_el2 =3D false; - - if (arm_feature(env, ARM_FEATURE_M)) { - return 1; - } - - if (arm_is_el2_enabled(env)) { - route_to_el2 =3D env->cp15.hcr_el2 & HCR_TGE || - env->cp15.mdcr_el2 & MDCR_TDE; - } - - if (route_to_el2) { - return 2; - } else if (arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && secure) { - return 3; - } else { - return 1; - } -} - -/* - * Raise an exception to the debug target el. - * Modify syndrome to indicate when origin and target EL are the same. - */ -G_NORETURN static void -raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome) -{ - int debug_el =3D arm_debug_target_el(env); - int cur_el =3D arm_current_el(env); - - /* - * If singlestep is targeting a lower EL than the current one, then - * DisasContext.ss_active must be false and we can never get here. - * Similarly for watchpoint and breakpoint matches. - */ - assert(debug_el >=3D cur_el); - syndrome |=3D (debug_el =3D=3D cur_el) << ARM_EL_EC_SHIFT; - raise_exception(env, excp, syndrome, debug_el); -} - -/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ -static bool aa64_generate_debug_exceptions(CPUARMState *env) -{ - int cur_el =3D arm_current_el(env); - int debug_el; - - if (cur_el =3D=3D 3) { - return false; - } - - /* MDCR_EL3.SDD disables debug events from Secure state */ - if (arm_is_secure_below_el3(env) - && extract32(env->cp15.mdcr_el3, 16, 1)) { - return false; - } - - /* - * Same EL to same EL debug exceptions need MDSCR_KDE enabled - * while not masking the (D)ebug bit in DAIF. - */ - debug_el =3D arm_debug_target_el(env); - - if (cur_el =3D=3D debug_el) { - return extract32(env->cp15.mdscr_el1, 13, 1) - && !(env->daif & PSTATE_D); - } - - /* Otherwise the debug target needs to be a higher EL */ - return debug_el > cur_el; -} - -static bool aa32_generate_debug_exceptions(CPUARMState *env) -{ - int el =3D arm_current_el(env); - - if (el =3D=3D 0 && arm_el_is_aa64(env, 1)) { - return aa64_generate_debug_exceptions(env); - } - - if (arm_is_secure(env)) { - int spd; - - if (el =3D=3D 0 && (env->cp15.sder & 1)) { - /* - * SDER.SUIDEN means debug exceptions from Secure EL0 - * are always enabled. Otherwise they are controlled by - * SDCR.SPD like those from other Secure ELs. - */ - return true; - } - - spd =3D extract32(env->cp15.mdcr_el3, 14, 2); - switch (spd) { - case 1: - /* SPD =3D=3D 0b01 is reserved, but behaves as 0b00. */ - case 0: - /* - * For 0b00 we return true if external secure invasive debug - * is enabled. On real hardware this is controlled by external - * signals to the core. QEMU always permits debug, and behaves - * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. - */ - return true; - case 2: - return false; - case 3: - return true; - } - } - - return el !=3D 2; -} - -/* - * Return true if debugging exceptions are currently enabled. - * This corresponds to what in ARM ARM pseudocode would be - * if UsingAArch32() then - * return AArch32.GenerateDebugExceptions() - * else - * return AArch64.GenerateDebugExceptions() - * We choose to push the if() down into this function for clarity, - * since the pseudocode has it at all callsites except for the one in - * CheckSoftwareStep(), where it is elided because both branches would - * always return the same value. - */ -bool arm_generate_debug_exceptions(CPUARMState *env) -{ - if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) { - return false; - } - if (is_a64(env)) { - return aa64_generate_debug_exceptions(env); - } else { - return aa32_generate_debug_exceptions(env); - } -} - -/* - * Is single-stepping active? (Note that the "is EL_D AArch64?" check - * implicitly means this always returns false in pre-v8 CPUs.) - */ -bool arm_singlestep_active(CPUARMState *env) -{ - return extract32(env->cp15.mdscr_el1, 0, 1) - && arm_el_is_aa64(env, arm_debug_target_el(env)) - && arm_generate_debug_exceptions(env); -} - -/* Return true if the linked breakpoint entry lbn passes its checks */ -static bool linked_bp_matches(ARMCPU *cpu, int lbn) -{ - CPUARMState *env =3D &cpu->env; - uint64_t bcr =3D env->cp15.dbgbcr[lbn]; - int brps =3D arm_num_brps(cpu); - int ctx_cmps =3D arm_num_ctx_cmps(cpu); - int bt; - uint32_t contextidr; - uint64_t hcr_el2; - - /* - * Links to unimplemented or non-context aware breakpoints are - * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or - * as if linked to an UNKNOWN context-aware breakpoint (in which - * case DBGWCR_EL1.LBN must indicate that breakpoint). - * We choose the former. - */ - if (lbn >=3D brps || lbn < (brps - ctx_cmps)) { - return false; - } - - bcr =3D env->cp15.dbgbcr[lbn]; - - if (extract64(bcr, 0, 1) =3D=3D 0) { - /* Linked breakpoint disabled : generate no events */ - return false; - } - - bt =3D extract64(bcr, 20, 4); - hcr_el2 =3D arm_hcr_el2_eff(env); - - switch (bt) { - case 3: /* linked context ID match */ - switch (arm_current_el(env)) { - default: - /* Context matches never fire in AArch64 EL3 */ - return false; - case 2: - if (!(hcr_el2 & HCR_E2H)) { - /* Context matches never fire in EL2 without E2H enabled. = */ - return false; - } - contextidr =3D env->cp15.contextidr_el[2]; - break; - case 1: - contextidr =3D env->cp15.contextidr_el[1]; - break; - case 0: - if ((hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)= ) { - contextidr =3D env->cp15.contextidr_el[2]; - } else { - contextidr =3D env->cp15.contextidr_el[1]; - } - break; - } - break; - - case 7: /* linked contextidr_el1 match */ - contextidr =3D env->cp15.contextidr_el[1]; - break; - case 13: /* linked contextidr_el2 match */ - contextidr =3D env->cp15.contextidr_el[2]; - break; - - case 9: /* linked VMID match (reserved if no EL2) */ - case 11: /* linked context ID and VMID match (reserved if no EL2) */ - case 15: /* linked full context ID match */ - default: - /* - * Links to Unlinked context breakpoints must generate no - * events; we choose to do the same for reserved values too. - */ - return false; - } - - /* - * We match the whole register even if this is AArch32 using the - * short descriptor format (in which case it holds both PROCID and ASI= D), - * since we don't implement the optional v7 context ID masking. - */ - return contextidr =3D=3D (uint32_t)env->cp15.dbgbvr[lbn]; -} - -static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) -{ - CPUARMState *env =3D &cpu->env; - uint64_t cr; - int pac, hmc, ssc, wt, lbn; - /* - * Note that for watchpoints the check is against the CPU security - * state, not the S/NS attribute on the offending data access. - */ - bool is_secure =3D arm_is_secure(env); - int access_el =3D arm_current_el(env); - - if (is_wp) { - CPUWatchpoint *wp =3D env->cpu_watchpoint[n]; - - if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) { - return false; - } - cr =3D env->cp15.dbgwcr[n]; - if (wp->hitattrs.user) { - /* - * The LDRT/STRT/LDT/STT "unprivileged access" instructions sh= ould - * match watchpoints as if they were accesses done at EL0, eve= n if - * the CPU is at EL1 or higher. - */ - access_el =3D 0; - } - } else { - uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; - - if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc !=3D pc)= { - return false; - } - cr =3D env->cp15.dbgbcr[n]; - } - /* - * The WATCHPOINT_HIT flag guarantees us that the watchpoint is - * enabled and that the address and access type match; for breakpoints - * we know the address matched; check the remaining fields, including - * linked breakpoints. We rely on WCR and BCR having the same layout - * for the LBN, SSC, HMC, PAC/PMC and is-linked fields. - * Note that some combinations of {PAC, HMC, SSC} are reserved and - * must act either like some valid combination or as if the watchpoint - * were disabled. We choose the former, and use this together with - * the fact that EL3 must always be Secure and EL2 must always be - * Non-Secure to simplify the code slightly compared to the full - * table in the ARM ARM. - */ - pac =3D FIELD_EX64(cr, DBGWCR, PAC); - hmc =3D FIELD_EX64(cr, DBGWCR, HMC); - ssc =3D FIELD_EX64(cr, DBGWCR, SSC); - - switch (ssc) { - case 0: - break; - case 1: - case 3: - if (is_secure) { - return false; - } - break; - case 2: - if (!is_secure) { - return false; - } - break; - } - - switch (access_el) { - case 3: - case 2: - if (!hmc) { - return false; - } - break; - case 1: - if (extract32(pac, 0, 1) =3D=3D 0) { - return false; - } - break; - case 0: - if (extract32(pac, 1, 1) =3D=3D 0) { - return false; - } - break; - default: - g_assert_not_reached(); - } - - wt =3D FIELD_EX64(cr, DBGWCR, WT); - lbn =3D FIELD_EX64(cr, DBGWCR, LBN); - - if (wt && !linked_bp_matches(cpu, lbn)) { - return false; - } - - return true; -} - -static bool check_watchpoints(ARMCPU *cpu) -{ - CPUARMState *env =3D &cpu->env; - int n; - - /* - * If watchpoints are disabled globally or we can't take debug - * exceptions here then watchpoint firings are ignored. - */ - if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 - || !arm_generate_debug_exceptions(env)) { - return false; - } - - for (n =3D 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) { - if (bp_wp_matches(cpu, n, true)) { - return true; - } - } - return false; -} - -bool arm_debug_check_breakpoint(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - vaddr pc; - int n; - - /* - * If breakpoints are disabled globally or we can't take debug - * exceptions here then breakpoint firings are ignored. - */ - if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 - || !arm_generate_debug_exceptions(env)) { - return false; - } - - /* - * Single-step exceptions have priority over breakpoint exceptions. - * If single-step state is active-pending, suppress the bp. - */ - if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { - return false; - } - - /* - * PC alignment faults have priority over breakpoint exceptions. - */ - pc =3D is_a64(env) ? env->pc : env->regs[15]; - if ((is_a64(env) || !env->thumb) && (pc & 3) !=3D 0) { - return false; - } - - /* - * Instruction aborts have priority over breakpoint exceptions. - * TODO: We would need to look up the page for PC and verify that - * it is present and executable. - */ - - for (n =3D 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { - if (bp_wp_matches(cpu, n, false)) { - return true; - } - } - return false; -} - -bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) -{ - /* - * Called by core code when a CPU watchpoint fires; need to check if t= his - * is also an architectural watchpoint match. - */ - ARMCPU *cpu =3D ARM_CPU(cs); - - return check_watchpoints(cpu); -} - -/* - * Return the FSR value for a debug exception (watchpoint, hardware - * breakpoint or BKPT insn) targeting the specified exception level. - */ -static uint32_t arm_debug_exception_fsr(CPUARMState *env) -{ - ARMMMUFaultInfo fi =3D { .type =3D ARMFault_Debug }; - int target_el =3D arm_debug_target_el(env); - bool using_lpae; - - if (arm_feature(env, ARM_FEATURE_M)) { - using_lpae =3D false; - } else if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el)) { - using_lpae =3D true; - } else if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V8)) { - using_lpae =3D true; - } else if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { - using_lpae =3D true; - } else { - using_lpae =3D false; - } - - if (using_lpae) { - return arm_fi_to_lfsc(&fi); - } else { - return arm_fi_to_sfsc(&fi); - } -} - -void arm_debug_excp_handler(CPUState *cs) -{ - /* - * Called by core code when a watchpoint or breakpoint fires; - * need to check which one and raise the appropriate exception. - */ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - CPUWatchpoint *wp_hit =3D cs->watchpoint_hit; - - if (wp_hit) { - if (wp_hit->flags & BP_CPU) { - bool wnr =3D (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) !=3D 0; - - cs->watchpoint_hit =3D NULL; - - env->exception.fsr =3D arm_debug_exception_fsr(env); - env->exception.vaddress =3D wp_hit->hitaddr; - raise_exception_debug(env, EXCP_DATA_ABORT, - syn_watchpoint(0, 0, wnr)); - } - } else { - uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; - - /* - * (1) GDB breakpoints should be handled first. - * (2) Do not raise a CPU exception if no CPU breakpoint has fired, - * since singlestep is also done by generating a debug internal - * exception. - */ - if (cpu_breakpoint_test(cs, pc, BP_GDB) - || !cpu_breakpoint_test(cs, pc, BP_CPU)) { - return; - } - - env->exception.fsr =3D arm_debug_exception_fsr(env); - /* - * FAR is UNKNOWN: clear vaddress to avoid potentially exposing - * values to the guest that it shouldn't be able to see at its - * exception/security level. - */ - env->exception.vaddress =3D 0; - raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); - } -} - -/* - * Raise an EXCP_BKPT with the specified syndrome register value, - * targeting the correct exception level for debug exceptions. - */ -void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) -{ - int debug_el =3D arm_debug_target_el(env); - int cur_el =3D arm_current_el(env); - - /* FSR will only be used if the debug target EL is AArch32. */ - env->exception.fsr =3D arm_debug_exception_fsr(env); - /* - * FAR is UNKNOWN: clear vaddress to avoid potentially exposing - * values to the guest that it shouldn't be able to see at its - * exception/security level. - */ - env->exception.vaddress =3D 0; - /* - * Other kinds of architectural debug exception are ignored if - * they target an exception level below the current one (in QEMU - * this is checked by arm_generate_debug_exceptions()). Breakpoint - * instructions are special because they always generate an exception - * to somewhere: if they can't go to the configured debug exception - * level they are taken to the current exception level. - */ - if (debug_el < cur_el) { - debug_el =3D cur_el; - } - raise_exception(env, EXCP_BKPT, syndrome, debug_el); -} - -void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) -{ - raise_exception_debug(env, EXCP_UDEF, syndrome); -} - -void hw_watchpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - vaddr len =3D 0; - vaddr wvr =3D env->cp15.dbgwvr[n]; - uint64_t wcr =3D env->cp15.dbgwcr[n]; - int mask; - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; - - if (env->cpu_watchpoint[n]) { - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); - env->cpu_watchpoint[n] =3D NULL; - } - - if (!FIELD_EX64(wcr, DBGWCR, E)) { - /* E bit clear : watchpoint disabled */ - return; - } - - switch (FIELD_EX64(wcr, DBGWCR, LSC)) { - case 0: - /* LSC 00 is reserved and must behave as if the wp is disabled */ - return; - case 1: - flags |=3D BP_MEM_READ; - break; - case 2: - flags |=3D BP_MEM_WRITE; - break; - case 3: - flags |=3D BP_MEM_ACCESS; - break; - } - - /* - * Attempts to use both MASK and BAS fields simultaneously are - * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, - * thus generating a watchpoint for every byte in the masked region. - */ - mask =3D FIELD_EX64(wcr, DBGWCR, MASK); - if (mask =3D=3D 1 || mask =3D=3D 2) { - /* - * Reserved values of MASK; we must act as if the mask value was - * some non-reserved value, or as if the watchpoint were disabled. - * We choose the latter. - */ - return; - } else if (mask) { - /* Watchpoint covers an aligned area up to 2GB in size */ - len =3D 1ULL << mask; - /* - * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE - * whether the watchpoint fires when the unmasked bits match; we o= pt - * to generate the exceptions. - */ - wvr &=3D ~(len - 1); - } else { - /* Watchpoint covers bytes defined by the byte address select bits= */ - int bas =3D FIELD_EX64(wcr, DBGWCR, BAS); - int basstart; - - if (extract64(wvr, 2, 1)) { - /* - * Deprecated case of an only 4-aligned address. BAS[7:4] are - * ignored, and BAS[3:0] define which bytes to watch. - */ - bas &=3D 0xf; - } - - if (bas =3D=3D 0) { - /* This must act as if the watchpoint is disabled */ - return; - } - - /* - * The BAS bits are supposed to be programmed to indicate a contig= uous - * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er - * we fire for each byte in the word/doubleword addressed by the W= VR. - * We choose to ignore any non-zero bits after the first range of = 1s. - */ - basstart =3D ctz32(bas); - len =3D cto32(bas >> basstart); - wvr +=3D basstart; - } - - cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, - &env->cpu_watchpoint[n]); -} - -void hw_watchpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* - * Completely clear out existing QEMU watchpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { - hw_watchpoint_update(cpu, i); - } -} - -void hw_breakpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - uint64_t bvr =3D env->cp15.dbgbvr[n]; - uint64_t bcr =3D env->cp15.dbgbcr[n]; - vaddr addr; - int bt; - int flags =3D BP_CPU; - - if (env->cpu_breakpoint[n]) { - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); - env->cpu_breakpoint[n] =3D NULL; - } - - if (!extract64(bcr, 0, 1)) { - /* E bit clear : watchpoint disabled */ - return; - } - - bt =3D extract64(bcr, 20, 4); - - switch (bt) { - case 4: /* unlinked address mismatch (reserved if AArch64) */ - case 5: /* linked address mismatch (reserved if AArch64) */ - qemu_log_mask(LOG_UNIMP, - "arm: address mismatch breakpoint types not implemen= ted\n"); - return; - case 0: /* unlinked address match */ - case 1: /* linked address match */ - { - /* - * Bits [1:0] are RES0. - * - * It is IMPLEMENTATION DEFINED whether bits [63:49] - * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit - * of the VA field ([48] or [52] for FEAT_LVA), or whether the - * value is read as written. It is CONSTRAINED UNPREDICTABLE - * whether the RESS bits are ignored when comparing an address. - * Therefore we are allowed to compare the entire register, which - * lets us avoid considering whether FEAT_LVA is actually enabled. - * - * The BAS field is used to allow setting breakpoints on 16-bit - * wide instructions; it is CONSTRAINED UNPREDICTABLE whether - * a bp will fire if the addresses covered by the bp and the addre= sses - * covered by the insn overlap but the insn doesn't start at the - * start of the bp address range. We choose to require the insn and - * the bp to have the same address. The constraints on writing to - * BAS enforced in dbgbcr_write mean we have only four cases: - * 0b0000 =3D> no breakpoint - * 0b0011 =3D> breakpoint on addr - * 0b1100 =3D> breakpoint on addr + 2 - * 0b1111 =3D> breakpoint on addr - * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). - */ - int bas =3D extract64(bcr, 5, 4); - addr =3D bvr & ~3ULL; - if (bas =3D=3D 0) { - return; - } - if (bas =3D=3D 0xc) { - addr +=3D 2; - } - break; - } - case 2: /* unlinked context ID match */ - case 8: /* unlinked VMID match (reserved if no EL2) */ - case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ - qemu_log_mask(LOG_UNIMP, - "arm: unlinked context breakpoint types not implemen= ted\n"); - return; - case 9: /* linked VMID match (reserved if no EL2) */ - case 11: /* linked context ID and VMID match (reserved if no EL2) */ - case 3: /* linked context ID match */ - default: - /* - * We must generate no events for Linked context matches (unless - * they are linked to by some other bp/wp, which is handled in - * updates for the linking bp/wp). We choose to also generate no e= vents - * for reserved values. - */ - return; - } - - cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); -} - -void hw_breakpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* - * Completely clear out existing QEMU breakpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { - hw_breakpoint_update(cpu, i); - } -} - -#if !defined(CONFIG_USER_ONLY) - -vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* - * In BE32 system mode, target memory is stored byteswapped (on a - * little-endian host system), and by the time we reach here (via an - * opcode helper) the addresses of subword accesses have been adjusted - * to account for that, which means that watchpoints will not match. - * Undo the adjustment here. - */ - if (arm_sctlr_b(env)) { - if (len =3D=3D 1) { - addr ^=3D 3; - } else if (len =3D=3D 2) { - addr ^=3D 2; - } - } - - return addr; -} - -#endif /* !CONFIG_USER_ONLY */ -#endif /* CONFIG_TCG */ - /* * Check for traps to "powerdown debug" registers, which are controlled * by MDCR.TDOSA diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c new file mode 100644 index 00000000000..7dfb291a9bf --- /dev/null +++ b/target/arm/tcg/debug.c @@ -0,0 +1,782 @@ +/* + * ARM debug helpers used by TCG + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "internals.h" +#include "cpu-features.h" +#include "cpregs.h" +#include "exec/watchpoint.h" +#include "system/tcg.h" + +#define HELPER_H "tcg/helper.h" +#include "exec/helper-proto.h.inc" + +/* Return the Exception Level targeted by debug exceptions. */ +static int arm_debug_target_el(CPUARMState *env) +{ + bool secure =3D arm_is_secure(env); + bool route_to_el2 =3D false; + + if (arm_feature(env, ARM_FEATURE_M)) { + return 1; + } + + if (arm_is_el2_enabled(env)) { + route_to_el2 =3D env->cp15.hcr_el2 & HCR_TGE || + env->cp15.mdcr_el2 & MDCR_TDE; + } + + if (route_to_el2) { + return 2; + } else if (arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3) && secure) { + return 3; + } else { + return 1; + } +} + +/* + * Raise an exception to the debug target el. + * Modify syndrome to indicate when origin and target EL are the same. + */ +static G_NORETURN void +raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome) +{ + int debug_el =3D arm_debug_target_el(env); + int cur_el =3D arm_current_el(env); + + /* + * If singlestep is targeting a lower EL than the current one, then + * DisasContext.ss_active must be false and we can never get here. + * Similarly for watchpoint and breakpoint matches. + */ + assert(debug_el >=3D cur_el); + syndrome |=3D (debug_el =3D=3D cur_el) << ARM_EL_EC_SHIFT; + raise_exception(env, excp, syndrome, debug_el); +} + +/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ +static bool aa64_generate_debug_exceptions(CPUARMState *env) +{ + int cur_el =3D arm_current_el(env); + int debug_el; + + if (cur_el =3D=3D 3) { + return false; + } + + /* MDCR_EL3.SDD disables debug events from Secure state */ + if (arm_is_secure_below_el3(env) + && extract32(env->cp15.mdcr_el3, 16, 1)) { + return false; + } + + /* + * Same EL to same EL debug exceptions need MDSCR_KDE enabled + * while not masking the (D)ebug bit in DAIF. + */ + debug_el =3D arm_debug_target_el(env); + + if (cur_el =3D=3D debug_el) { + return extract32(env->cp15.mdscr_el1, 13, 1) + && !(env->daif & PSTATE_D); + } + + /* Otherwise the debug target needs to be a higher EL */ + return debug_el > cur_el; +} + +static bool aa32_generate_debug_exceptions(CPUARMState *env) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 0 && arm_el_is_aa64(env, 1)) { + return aa64_generate_debug_exceptions(env); + } + + if (arm_is_secure(env)) { + int spd; + + if (el =3D=3D 0 && (env->cp15.sder & 1)) { + /* + * SDER.SUIDEN means debug exceptions from Secure EL0 + * are always enabled. Otherwise they are controlled by + * SDCR.SPD like those from other Secure ELs. + */ + return true; + } + + spd =3D extract32(env->cp15.mdcr_el3, 14, 2); + switch (spd) { + case 1: + /* SPD =3D=3D 0b01 is reserved, but behaves as 0b00. */ + case 0: + /* + * For 0b00 we return true if external secure invasive debug + * is enabled. On real hardware this is controlled by external + * signals to the core. QEMU always permits debug, and behaves + * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. + */ + return true; + case 2: + return false; + case 3: + return true; + } + } + + return el !=3D 2; +} + +/* + * Return true if debugging exceptions are currently enabled. + * This corresponds to what in ARM ARM pseudocode would be + * if UsingAArch32() then + * return AArch32.GenerateDebugExceptions() + * else + * return AArch64.GenerateDebugExceptions() + * We choose to push the if() down into this function for clarity, + * since the pseudocode has it at all callsites except for the one in + * CheckSoftwareStep(), where it is elided because both branches would + * always return the same value. + */ +bool arm_generate_debug_exceptions(CPUARMState *env) +{ + if ((env->cp15.oslsr_el1 & 1) || (env->cp15.osdlr_el1 & 1)) { + return false; + } + if (is_a64(env)) { + return aa64_generate_debug_exceptions(env); + } else { + return aa32_generate_debug_exceptions(env); + } +} + +/* + * Is single-stepping active? (Note that the "is EL_D AArch64?" check + * implicitly means this always returns false in pre-v8 CPUs.) + */ +bool arm_singlestep_active(CPUARMState *env) +{ + return extract32(env->cp15.mdscr_el1, 0, 1) + && arm_el_is_aa64(env, arm_debug_target_el(env)) + && arm_generate_debug_exceptions(env); +} + +/* Return true if the linked breakpoint entry lbn passes its checks */ +static bool linked_bp_matches(ARMCPU *cpu, int lbn) +{ + CPUARMState *env =3D &cpu->env; + uint64_t bcr =3D env->cp15.dbgbcr[lbn]; + int brps =3D arm_num_brps(cpu); + int ctx_cmps =3D arm_num_ctx_cmps(cpu); + int bt; + uint32_t contextidr; + uint64_t hcr_el2; + + /* + * Links to unimplemented or non-context aware breakpoints are + * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or + * as if linked to an UNKNOWN context-aware breakpoint (in which + * case DBGWCR_EL1.LBN must indicate that breakpoint). + * We choose the former. + */ + if (lbn >=3D brps || lbn < (brps - ctx_cmps)) { + return false; + } + + bcr =3D env->cp15.dbgbcr[lbn]; + + if (extract64(bcr, 0, 1) =3D=3D 0) { + /* Linked breakpoint disabled : generate no events */ + return false; + } + + bt =3D extract64(bcr, 20, 4); + hcr_el2 =3D arm_hcr_el2_eff(env); + + switch (bt) { + case 3: /* linked context ID match */ + switch (arm_current_el(env)) { + default: + /* Context matches never fire in AArch64 EL3 */ + return false; + case 2: + if (!(hcr_el2 & HCR_E2H)) { + /* Context matches never fire in EL2 without E2H enabled. = */ + return false; + } + contextidr =3D env->cp15.contextidr_el[2]; + break; + case 1: + contextidr =3D env->cp15.contextidr_el[1]; + break; + case 0: + if ((hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)= ) { + contextidr =3D env->cp15.contextidr_el[2]; + } else { + contextidr =3D env->cp15.contextidr_el[1]; + } + break; + } + break; + + case 7: /* linked contextidr_el1 match */ + contextidr =3D env->cp15.contextidr_el[1]; + break; + case 13: /* linked contextidr_el2 match */ + contextidr =3D env->cp15.contextidr_el[2]; + break; + + case 9: /* linked VMID match (reserved if no EL2) */ + case 11: /* linked context ID and VMID match (reserved if no EL2) */ + case 15: /* linked full context ID match */ + default: + /* + * Links to Unlinked context breakpoints must generate no + * events; we choose to do the same for reserved values too. + */ + return false; + } + + /* + * We match the whole register even if this is AArch32 using the + * short descriptor format (in which case it holds both PROCID and ASI= D), + * since we don't implement the optional v7 context ID masking. + */ + return contextidr =3D=3D (uint32_t)env->cp15.dbgbvr[lbn]; +} + +static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp) +{ + CPUARMState *env =3D &cpu->env; + uint64_t cr; + int pac, hmc, ssc, wt, lbn; + /* + * Note that for watchpoints the check is against the CPU security + * state, not the S/NS attribute on the offending data access. + */ + bool is_secure =3D arm_is_secure(env); + int access_el =3D arm_current_el(env); + + if (is_wp) { + CPUWatchpoint *wp =3D env->cpu_watchpoint[n]; + + if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) { + return false; + } + cr =3D env->cp15.dbgwcr[n]; + if (wp->hitattrs.user) { + /* + * The LDRT/STRT/LDT/STT "unprivileged access" instructions sh= ould + * match watchpoints as if they were accesses done at EL0, eve= n if + * the CPU is at EL1 or higher. + */ + access_el =3D 0; + } + } else { + uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; + + if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc !=3D pc)= { + return false; + } + cr =3D env->cp15.dbgbcr[n]; + } + /* + * The WATCHPOINT_HIT flag guarantees us that the watchpoint is + * enabled and that the address and access type match; for breakpoints + * we know the address matched; check the remaining fields, including + * linked breakpoints. We rely on WCR and BCR having the same layout + * for the LBN, SSC, HMC, PAC/PMC and is-linked fields. + * Note that some combinations of {PAC, HMC, SSC} are reserved and + * must act either like some valid combination or as if the watchpoint + * were disabled. We choose the former, and use this together with + * the fact that EL3 must always be Secure and EL2 must always be + * Non-Secure to simplify the code slightly compared to the full + * table in the ARM ARM. + */ + pac =3D FIELD_EX64(cr, DBGWCR, PAC); + hmc =3D FIELD_EX64(cr, DBGWCR, HMC); + ssc =3D FIELD_EX64(cr, DBGWCR, SSC); + + switch (ssc) { + case 0: + break; + case 1: + case 3: + if (is_secure) { + return false; + } + break; + case 2: + if (!is_secure) { + return false; + } + break; + } + + switch (access_el) { + case 3: + case 2: + if (!hmc) { + return false; + } + break; + case 1: + if (extract32(pac, 0, 1) =3D=3D 0) { + return false; + } + break; + case 0: + if (extract32(pac, 1, 1) =3D=3D 0) { + return false; + } + break; + default: + g_assert_not_reached(); + } + + wt =3D FIELD_EX64(cr, DBGWCR, WT); + lbn =3D FIELD_EX64(cr, DBGWCR, LBN); + + if (wt && !linked_bp_matches(cpu, lbn)) { + return false; + } + + return true; +} + +static bool check_watchpoints(ARMCPU *cpu) +{ + CPUARMState *env =3D &cpu->env; + int n; + + /* + * If watchpoints are disabled globally or we can't take debug + * exceptions here then watchpoint firings are ignored. + */ + if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 + || !arm_generate_debug_exceptions(env)) { + return false; + } + + for (n =3D 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) { + if (bp_wp_matches(cpu, n, true)) { + return true; + } + } + return false; +} + +bool arm_debug_check_breakpoint(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + vaddr pc; + int n; + + /* + * If breakpoints are disabled globally or we can't take debug + * exceptions here then breakpoint firings are ignored. + */ + if (extract32(env->cp15.mdscr_el1, 15, 1) =3D=3D 0 + || !arm_generate_debug_exceptions(env)) { + return false; + } + + /* + * Single-step exceptions have priority over breakpoint exceptions. + * If single-step state is active-pending, suppress the bp. + */ + if (arm_singlestep_active(env) && !(env->pstate & PSTATE_SS)) { + return false; + } + + /* + * PC alignment faults have priority over breakpoint exceptions. + */ + pc =3D is_a64(env) ? env->pc : env->regs[15]; + if ((is_a64(env) || !env->thumb) && (pc & 3) !=3D 0) { + return false; + } + + /* + * Instruction aborts have priority over breakpoint exceptions. + * TODO: We would need to look up the page for PC and verify that + * it is present and executable. + */ + + for (n =3D 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) { + if (bp_wp_matches(cpu, n, false)) { + return true; + } + } + return false; +} + +bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ + /* + * Called by core code when a CPU watchpoint fires; need to check if t= his + * is also an architectural watchpoint match. + */ + ARMCPU *cpu =3D ARM_CPU(cs); + + return check_watchpoints(cpu); +} + +/* + * Return the FSR value for a debug exception (watchpoint, hardware + * breakpoint or BKPT insn) targeting the specified exception level. + */ +static uint32_t arm_debug_exception_fsr(CPUARMState *env) +{ + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_Debug }; + int target_el =3D arm_debug_target_el(env); + bool using_lpae; + + if (arm_feature(env, ARM_FEATURE_M)) { + using_lpae =3D false; + } else if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el)) { + using_lpae =3D true; + } else if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8)) { + using_lpae =3D true; + } else if (arm_feature(env, ARM_FEATURE_LPAE) && + (env->cp15.tcr_el[target_el] & TTBCR_EAE)) { + using_lpae =3D true; + } else { + using_lpae =3D false; + } + + if (using_lpae) { + return arm_fi_to_lfsc(&fi); + } else { + return arm_fi_to_sfsc(&fi); + } +} + +void arm_debug_excp_handler(CPUState *cs) +{ + /* + * Called by core code when a watchpoint or breakpoint fires; + * need to check which one and raise the appropriate exception. + */ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + CPUWatchpoint *wp_hit =3D cs->watchpoint_hit; + + if (wp_hit) { + if (wp_hit->flags & BP_CPU) { + bool wnr =3D (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) !=3D 0; + + cs->watchpoint_hit =3D NULL; + + env->exception.fsr =3D arm_debug_exception_fsr(env); + env->exception.vaddress =3D wp_hit->hitaddr; + raise_exception_debug(env, EXCP_DATA_ABORT, + syn_watchpoint(0, 0, wnr)); + } + } else { + uint64_t pc =3D is_a64(env) ? env->pc : env->regs[15]; + + /* + * (1) GDB breakpoints should be handled first. + * (2) Do not raise a CPU exception if no CPU breakpoint has fired, + * since singlestep is also done by generating a debug internal + * exception. + */ + if (cpu_breakpoint_test(cs, pc, BP_GDB) + || !cpu_breakpoint_test(cs, pc, BP_CPU)) { + return; + } + + env->exception.fsr =3D arm_debug_exception_fsr(env); + /* + * FAR is UNKNOWN: clear vaddress to avoid potentially exposing + * values to the guest that it shouldn't be able to see at its + * exception/security level. + */ + env->exception.vaddress =3D 0; + raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); + } +} + +/* + * Raise an EXCP_BKPT with the specified syndrome register value, + * targeting the correct exception level for debug exceptions. + */ +void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) +{ + int debug_el =3D arm_debug_target_el(env); + int cur_el =3D arm_current_el(env); + + /* FSR will only be used if the debug target EL is AArch32. */ + env->exception.fsr =3D arm_debug_exception_fsr(env); + /* + * FAR is UNKNOWN: clear vaddress to avoid potentially exposing + * values to the guest that it shouldn't be able to see at its + * exception/security level. + */ + env->exception.vaddress =3D 0; + /* + * Other kinds of architectural debug exception are ignored if + * they target an exception level below the current one (in QEMU + * this is checked by arm_generate_debug_exceptions()). Breakpoint + * instructions are special because they always generate an exception + * to somewhere: if they can't go to the configured debug exception + * level they are taken to the current exception level. + */ + if (debug_el < cur_el) { + debug_el =3D cur_el; + } + raise_exception(env, EXCP_BKPT, syndrome, debug_el); +} + +void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) +{ + raise_exception_debug(env, EXCP_UDEF, syndrome); +} + +void hw_watchpoint_update(ARMCPU *cpu, int n) +{ + CPUARMState *env =3D &cpu->env; + vaddr len =3D 0; + vaddr wvr =3D env->cp15.dbgwvr[n]; + uint64_t wcr =3D env->cp15.dbgwcr[n]; + int mask; + int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + + if (env->cpu_watchpoint[n]) { + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); + env->cpu_watchpoint[n] =3D NULL; + } + + if (!FIELD_EX64(wcr, DBGWCR, E)) { + /* E bit clear : watchpoint disabled */ + return; + } + + switch (FIELD_EX64(wcr, DBGWCR, LSC)) { + case 0: + /* LSC 00 is reserved and must behave as if the wp is disabled */ + return; + case 1: + flags |=3D BP_MEM_READ; + break; + case 2: + flags |=3D BP_MEM_WRITE; + break; + case 3: + flags |=3D BP_MEM_ACCESS; + break; + } + + /* + * Attempts to use both MASK and BAS fields simultaneously are + * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, + * thus generating a watchpoint for every byte in the masked region. + */ + mask =3D FIELD_EX64(wcr, DBGWCR, MASK); + if (mask =3D=3D 1 || mask =3D=3D 2) { + /* + * Reserved values of MASK; we must act as if the mask value was + * some non-reserved value, or as if the watchpoint were disabled. + * We choose the latter. + */ + return; + } else if (mask) { + /* Watchpoint covers an aligned area up to 2GB in size */ + len =3D 1ULL << mask; + /* + * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE + * whether the watchpoint fires when the unmasked bits match; we o= pt + * to generate the exceptions. + */ + wvr &=3D ~(len - 1); + } else { + /* Watchpoint covers bytes defined by the byte address select bits= */ + int bas =3D FIELD_EX64(wcr, DBGWCR, BAS); + int basstart; + + if (extract64(wvr, 2, 1)) { + /* + * Deprecated case of an only 4-aligned address. BAS[7:4] are + * ignored, and BAS[3:0] define which bytes to watch. + */ + bas &=3D 0xf; + } + + if (bas =3D=3D 0) { + /* This must act as if the watchpoint is disabled */ + return; + } + + /* + * The BAS bits are supposed to be programmed to indicate a contig= uous + * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er + * we fire for each byte in the word/doubleword addressed by the W= VR. + * We choose to ignore any non-zero bits after the first range of = 1s. + */ + basstart =3D ctz32(bas); + len =3D cto32(bas >> basstart); + wvr +=3D basstart; + } + + cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, + &env->cpu_watchpoint[n]); +} + +void hw_watchpoint_update_all(ARMCPU *cpu) +{ + int i; + CPUARMState *env =3D &cpu->env; + + /* + * Completely clear out existing QEMU watchpoints and our array, to + * avoid possible stale entries following migration load. + */ + cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); + memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); + + for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { + hw_watchpoint_update(cpu, i); + } +} + +void hw_breakpoint_update(ARMCPU *cpu, int n) +{ + CPUARMState *env =3D &cpu->env; + uint64_t bvr =3D env->cp15.dbgbvr[n]; + uint64_t bcr =3D env->cp15.dbgbcr[n]; + vaddr addr; + int bt; + int flags =3D BP_CPU; + + if (env->cpu_breakpoint[n]) { + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); + env->cpu_breakpoint[n] =3D NULL; + } + + if (!extract64(bcr, 0, 1)) { + /* E bit clear : watchpoint disabled */ + return; + } + + bt =3D extract64(bcr, 20, 4); + + switch (bt) { + case 4: /* unlinked address mismatch (reserved if AArch64) */ + case 5: /* linked address mismatch (reserved if AArch64) */ + qemu_log_mask(LOG_UNIMP, + "arm: address mismatch breakpoint types not implemen= ted\n"); + return; + case 0: /* unlinked address match */ + case 1: /* linked address match */ + { + /* + * Bits [1:0] are RES0. + * + * It is IMPLEMENTATION DEFINED whether bits [63:49] + * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit + * of the VA field ([48] or [52] for FEAT_LVA), or whether the + * value is read as written. It is CONSTRAINED UNPREDICTABLE + * whether the RESS bits are ignored when comparing an address. + * Therefore we are allowed to compare the entire register, which + * lets us avoid considering whether FEAT_LVA is actually enabled. + * + * The BAS field is used to allow setting breakpoints on 16-bit + * wide instructions; it is CONSTRAINED UNPREDICTABLE whether + * a bp will fire if the addresses covered by the bp and the addre= sses + * covered by the insn overlap but the insn doesn't start at the + * start of the bp address range. We choose to require the insn and + * the bp to have the same address. The constraints on writing to + * BAS enforced in dbgbcr_write mean we have only four cases: + * 0b0000 =3D> no breakpoint + * 0b0011 =3D> breakpoint on addr + * 0b1100 =3D> breakpoint on addr + 2 + * 0b1111 =3D> breakpoint on addr + * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). + */ + int bas =3D extract64(bcr, 5, 4); + addr =3D bvr & ~3ULL; + if (bas =3D=3D 0) { + return; + } + if (bas =3D=3D 0xc) { + addr +=3D 2; + } + break; + } + case 2: /* unlinked context ID match */ + case 8: /* unlinked VMID match (reserved if no EL2) */ + case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ + qemu_log_mask(LOG_UNIMP, + "arm: unlinked context breakpoint types not implemen= ted\n"); + return; + case 9: /* linked VMID match (reserved if no EL2) */ + case 11: /* linked context ID and VMID match (reserved if no EL2) */ + case 3: /* linked context ID match */ + default: + /* + * We must generate no events for Linked context matches (unless + * they are linked to by some other bp/wp, which is handled in + * updates for the linking bp/wp). We choose to also generate no e= vents + * for reserved values. + */ + return; + } + + cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); +} + +void hw_breakpoint_update_all(ARMCPU *cpu) +{ + int i; + CPUARMState *env =3D &cpu->env; + + /* + * Completely clear out existing QEMU breakpoints and our array, to + * avoid possible stale entries following migration load. + */ + cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); + memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); + + for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { + hw_breakpoint_update(cpu, i); + } +} + +#if !defined(CONFIG_USER_ONLY) + +vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* + * In BE32 system mode, target memory is stored byteswapped (on a + * little-endian host system), and by the time we reach here (via an + * opcode helper) the addresses of subword accesses have been adjusted + * to account for that, which means that watchpoints will not match. + * Undo the adjustment here. + */ + if (arm_sctlr_b(env)) { + if (len =3D=3D 1) { + addr ^=3D 3; + } else if (len =3D=3D 2) { + addr ^=3D 2; + } + } + + return addr; +} + +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 1b115656c46..6e9aed3e5de 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -65,6 +65,7 @@ arm_common_ss.add(files( =20 arm_common_system_ss.add(files( 'cpregs-at.c', + 'debug.c', 'hflags.c', 'neon_helper.c', 'tlb_helper.c', @@ -72,6 +73,7 @@ arm_common_system_ss.add(files( 'vfp_helper.c', )) arm_user_ss.add(files( + 'debug.c', 'hflags.c', 'neon_helper.c', 'tlb_helper.c', --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771473808; cv=none; d=zohomail.com; s=zohoarc; b=JSLT7ropd+NLG+hbyOL7vX/9UspsVH49PFSaq5HxnOKU+/QB6Vea/ZOw4JS8oC3CrcOyA1vNU/CfL3ZlbnKdZEpSTfQJEmlWMAHhlRL1IxTdOqtFZ8f0eDqJbfgV7EQyG0z+zFI6QWvE8WyrL+xyX3sNFwTFI+1nwJIjgi0S/5Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771473808; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=X+EWQStl3OxtO/agizp2TzeqNHuyOddWzArd5felHRI=; b=KNTfqCD4ddAbJCkY1zU4y/SjTxGDPqA8COo/mrZpO+BQopgv7rCI6wfju3T/TcQhJZNg+lnG45XJu2G7J2nCbhz25PIHIlqGvfk67defMcNR2x208P2K5dd+lFzv4AN0H3cemSYdCHJPzEtdudlICDG5jZtsjP6TNMZRLmoBJsM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771473808207496.8778651054761; Wed, 18 Feb 2026 20:03:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vsvF4-0008Mb-Vg; Wed, 18 Feb 2026 23:02:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vsvF3-0008Lx-V3 for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:17 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vsvEy-0001D2-FO for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:17 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2aaf9191da3so2854115ad.2 for ; Wed, 18 Feb 2026 20:02:12 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. [216.71.219.44]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1a73200asm147636225ad.36.2026.02.18.20.02.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Feb 2026 20:02:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771473731; x=1772078531; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X+EWQStl3OxtO/agizp2TzeqNHuyOddWzArd5felHRI=; b=QWL0H7Kce/kelE9D1liCOoc+wHrwa+TpZDX/4mvSF3JWPlYnQsoFF7q/eoWNC1Eg5S S2p82B8E72nA4pcDNK8KKfWipKm46PaiTrC2lp4XIui7JcvEDrVK1TR8v8k87NqjU0Cf zUo2o52as15wgTGZpNROxyfpz2cBCrdsGvZeG6LMeXjgmRgabCgPMd597U6AA354KhZR i4f9i48ccOFL+ytLBO+3QHTB1MY+k+TpDq98V/YLmJXZ1hfHEdLaAtyquHc61XyOP/XP lFY8iajxS7U5ExZFbgUjqE9bV+ER7kM+Dq5LDTV4AQdKIn2HBV49yDpSZSZxT/9VMb00 SPNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771473731; x=1772078531; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=X+EWQStl3OxtO/agizp2TzeqNHuyOddWzArd5felHRI=; b=rSRw5VVvvZT99gABsIDOqdOQKK+b8f+aT7ylsZevPlKWLyRM5AbxFAucVCGJpph3KA PDJBH9dHwj1mf+XfFGRmPk66CisF7Ku7iRw1bppaNtSAPANq8AFJmX5Csb+vV+OYnoMa 1Kd1F2NNHob8b2bvOA8xyAGEd8sV4AaKlfEJz2izg9n7/eHwql+NI0uEjw0wheIX5VMT tsdDSfVtGrc3lP8pNrKwyoAvBZD7pnOOnuSD9ENu+pvqk7FT7pHMN0bmiVOos/hbWOr7 gHG4FZWCkornGQ9j9/AGq3Fg9fe8oIpv+fY5fNxqYLjixlva07R9m8L+WxburfcKKtMx 8vFA== X-Gm-Message-State: AOJu0YyHvUC1HvWCiR0xZ8YtC9c5N3Cme+MxiH9sdyysoVAM17uSWPBJ oDqjUB58hA6cPJqP6Qr0tbAhUkGaxN3dXfN0DWLR0dHed2PReKOIK0UdRPWYcH4yzrSF/EXaY09 /MXEW X-Gm-Gg: AZuq6aJ/gh9DpezHmjV26q2JNUYSJ9KXbrYK11Zvt5hS0mZzFqQNYjan3bGHhdPKYMN Zd2yhBB+b+clhYSZGVZTO3pWZJkMghWy2Z0tyPuMUj9P4Vx104daoF22UYb433JB/Vh/MpOlcak MZKkVDT6F1XWUytD7gqOiGFwSXeeBxl0w7m86cb39j9Bi4ITxlYWd4MQ+v2R2TM4zrDqGBe5/VE phnytbXEdPh0tZYs8sgdH+Ed7BEuwdhaGFC/ttCLLM2bbrKKspjMCbx+KlYYscFc1wejj/tMvBd d5wyXcQMlTwrkozgxVG4M/4CeJQ/wUp9fLYFMKsFgGp5TdST0Ac70pZChL+fg6yvv/Qs/3USDZV tiV4W3YcM2VcHcnXTnkywZVXKN9BftjsN3bJTJoQau6FIgEYXhHUg0ndUJ/TZ0xtotAFQnGAwrB Q++4VgtG7ocTt4RajDSu7D6jfq3Scg4nnoYuzkpjDBl1a83t/uKXLKL6RRx+H9Oo10hYC2crBE+ zRR X-Received: by 2002:a17:903:32c7:b0:2aa:d60c:d48a with SMTP id d9443c01a7336-2ad50e77664mr37975015ad.7.1771473730975; Wed, 18 Feb 2026 20:02:10 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , anjo@rev.ng, Peter Maydell , Jim MacArthur Subject: [PATCH v4 02/14] target/arm: Don't require helper prototypes in helper.c Date: Wed, 18 Feb 2026 20:01:38 -0800 Message-ID: <20260219040150.2098396-3-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> References: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771473810106154100 From: Peter Maydell In arm_cpu_do_interrupt_aarch64() we call the TCG helper function helper_rebuild_hflags_a64(), which requires helper.c to include the TCG helper function prototypes even when this file is being compiled with TCG disabled. We don't actually need to do this -- because we have already written the new EL into pstate and updated env->aarch64, we can call aarch64_rebuild_hflags() to achieve the same effect. This is the function we use everywhere else in this file to update hflags. Switch to aarch64_rebuild_hflags() and drop the include of the TCG helper headers. Signed-off-by: Peter Maydell Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8c5769477cf..033baf7e715 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -36,9 +36,6 @@ #include "target/arm/gtimer.h" #include "qemu/plugin.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - static void switch_mode(CPUARMState *env, int mode); =20 int compare_u64(const void *a, const void *b) @@ -9473,7 +9470,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) aarch64_restore_sp(env, new_el); =20 if (tcg_enabled()) { - helper_rebuild_hflags_a64(env, new_el); + arm_rebuild_hflags(env); } =20 env->pc =3D addr; --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771473812; cv=none; d=zohomail.com; s=zohoarc; b=mERO9EyXcL8U4qCElBjVp85owiIvOHqZubZN0sunACkWM/hlEmSjygcWRTlTm2q/zFyiZib1im+Asp4rI3Loj/cy8I/N6gjeQM/5IRkJeXjO31KDPWw+gc/scr7/MTJByysqNKj2GfZYeo+alm57iSjK9BoRWQ3StPGDrcPynRU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771473812; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZBh+fW1mApPtLG6aGnrKPAIWmAmzNuN5929rjSWR418=; b=TUH9PQEstbxk08qM+iC5QVZHPCjpj8qx1FIK/4dwR9UYBHt9jCcR9tOto9cSvI0l9fKOcyZQblcVbZX1ZyezhnXNAVhulspk2IpR2hhS1Yp/TR/QhBz209UDSJw5GBcvoMDtYPSTLiB7fPNAuipXcKdSda7MlYrQXlxNsRp8eOg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771473812316581.1475100693585; Wed, 18 Feb 2026 20:03:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vsvFD-0008R2-OZ; Wed, 18 Feb 2026 23:02:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vsvF4-0008MA-6q for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:18 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vsvEz-0001DO-8B for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:17 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-2a7a9b8ed69so4162255ad.2 for ; Wed, 18 Feb 2026 20:02:12 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. [216.71.219.44]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1a73200asm147636225ad.36.2026.02.18.20.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Feb 2026 20:02:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771473732; x=1772078532; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZBh+fW1mApPtLG6aGnrKPAIWmAmzNuN5929rjSWR418=; b=jubqbz5CatuhHK8bQ74J/CFroNI+AdO0ysG2eVHg7AxEvc30juLYDAgp6YlaaLt0SE RRNs3oenEIdaMccQmLIvPYsd0L2mkwgPbn/v4arTkuoM6h8uCvbyPfVT5NHv3ZGcCvsx BZbUTD5Cotdw58oHoLuEDzMDuQ6jbCFWiRlFqpsmx9VBXbmmc/Y4LYqhTic8x7xwmH7Y J0NC+VFl3yUxO772wLZ+HhytVNBdqSFuiNPekgCesG/wV0yJMph2gwqv74F3q3jkghWY xGPGUWYrIrZVn2RdaQYf7QvYnr5Xczo6W4inhslfoAckq0WddPe8/DanMg6ZLZK6n6pN Ytpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771473732; x=1772078532; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ZBh+fW1mApPtLG6aGnrKPAIWmAmzNuN5929rjSWR418=; b=Z2xslFMdTd3h2kNIlOtsDlC2ekl7gxqnzKfq8n1ZYTiHiSj8snX6MHU8HOBbKq8n4V 95wB2Pau6MPIsTisgcb8oJ+efn37ErAv3HLu1dPuqvbPI3UVAfUwfsRvtr6EpQGXLp5p ifgdI9yC1yBeOTr4ckwjYu0lAXIyfBJ+/R4xviMKGjYPo1HB/C5y9zeJ172zqxA9RXWZ vaCsC9924sYXq8WSGhfS8LyLUsQ0PlIXM39AgeuZ9KGLSCKGPjUzoxLZNxd37VmYieFm rcfo6bwDM8uBUkmpeyZlCjWslC960wbkJob3fcKlNHD71lPZc+CGLK7v6XT5BgQ1ElOx fjxQ== X-Gm-Message-State: AOJu0YzAlPGDd1B4r7Mdf/MQ4ujsSDE8GUFjjhMMSOnVebbXe3x3A/6/ Klne9pDXusHGHV2aN2Lf7ZUBBK8KMPFh4LDbsVLIzdU0Oz/cvr6SIkAs36lcyYbD2fJW1lBNut4 LXO3O X-Gm-Gg: AZuq6aKBx2FxUcL9WB6ru+ZvtaBUImTW9O4M/mx/AiEIX2dnonPPO8/X4tVcsGgUT5f i7N9E6CQtZhT085tTI1+o9doSv/abiKP0nIq1yVEyQMlcbj/ZaPGDn5rOcrh1YYsZjuUH9GI7n7 G0hmAN86k5uoChMLIuR1lFulKny7BlF4uN/3043aaeDPJPzp4GSK0nthwPaLy/fvtntv9rGZMhz 6PrZEPTS+cwCopWetJu4TuN4ovYzlOuEdr84U1NL2kawYm61czwq3GIrB1V1jUE42VerJRpLMTS saqFuaVDaupoT8YXAnpuvgSYCz/7YIQ/b8Bw+ZmnVTBp6pxWXSpq4ObTsXnVMZy9zAL1Bsq2qNM UvM6IumfWsDkSyFiru+NnWqpV0NF/Jt6dcKr8/tyY3qlx9PQHCTfwCegbnDeZ6If5QV6Dm85AE0 1LuSKxVOW+K+xZg6DaNBv4kevS76Vi0jo+i8ZJMWrx2JcxN4YbvLQsBacWjaPhz+LUhf53JyTy3 jvM X-Received: by 2002:a17:903:46cc:b0:2a9:48ce:b5f5 with SMTP id d9443c01a7336-2ad50f8e23cmr33186185ad.51.1771473731894; Wed, 18 Feb 2026 20:02:11 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , anjo@rev.ng, Peter Maydell , Jim MacArthur Subject: [PATCH v4 03/14] target/arm: extract helper-mve.h from helper.h Date: Wed, 18 Feb 2026 20:01:39 -0800 Message-ID: <20260219040150.2098396-4-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> References: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771473814694158500 Content-Type: text/plain; charset="utf-8" A few points to mention: - We mix helper prototypes and gen_helper definitions in a single header for convenience and to avoid headers boilerplate. - We rename existing tcg/helper-mve.h to helper-mve-defs.h to avoid conflict when including helper-mve.h. - We move mve helper_info definitions to tcg/mve_helper.c We'll repeat the same for other helpers. This allow to get rid of TARGET_AARCH64 in target/arm/helper.h. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper-mve.h | 14 ++++++++++++++ target/arm/helper.h | 2 -- target/arm/tcg/{helper-mve.h =3D> helper-mve-defs.h} | 0 target/arm/tcg/mve_helper.c | 4 ++++ target/arm/tcg/translate-mve.c | 1 + target/arm/tcg/translate.c | 1 + 6 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 target/arm/helper-mve.h rename target/arm/tcg/{helper-mve.h =3D> helper-mve-defs.h} (100%) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h new file mode 100644 index 00000000000..32ef3f64661 --- /dev/null +++ b/target/arm/helper-mve.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_MVE_H +#define HELPER_MVE_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-mve-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_MVE_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index f340a49a28a..44c7f3ed751 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -7,5 +7,3 @@ #include "tcg/helper-sve.h" #include "tcg/helper-sme.h" #endif - -#include "tcg/helper-mve.h" diff --git a/target/arm/tcg/helper-mve.h b/target/arm/tcg/helper-mve-defs.h similarity index 100% rename from target/arm/tcg/helper-mve.h rename to target/arm/tcg/helper-mve-defs.h diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 63ddcf3fecf..f33642df1f9 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper-mve.h" #include "internals.h" #include "vec_internal.h" #include "exec/helper-proto.h" @@ -27,6 +28,9 @@ #include "fpu/softfloat.h" #include "crypto/clmul.h" =20 +#define HELPER_H "tcg/helper-mve-defs.h" +#include "exec/helper-info.c.inc" + static uint16_t mve_eci_mask(CPUARMState *env) { /* diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index b1a8d6a65c0..4ca88f4d3a3 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "helper-mve.h" #include "translate.h" #include "translate-a32.h" =20 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index c90b0106f75..580ec86c68c 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -28,6 +28,7 @@ #include "cpregs.h" #include "exec/helper-proto.h" #include "exec/target_page.h" +#include "helper-mve.h" =20 #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 18 Feb 2026 20:02:13 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , anjo@rev.ng, Peter Maydell , Jim MacArthur Subject: [PATCH v4 04/14] target/arm: extract helper-a64.h from helper.h Date: Wed, 18 Feb 2026 20:01:40 -0800 Message-ID: <20260219040150.2098396-5-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> References: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771473941035158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper-a64.h | 14 ++++++++++++++ target/arm/helper.h | 1 - target/arm/tcg/{helper-a64.h =3D> helper-a64-defs.h} | 0 target/arm/tcg/helper-a64.c | 4 ++++ target/arm/tcg/mte_helper.c | 1 + target/arm/tcg/pauth_helper.c | 1 + target/arm/tcg/sve_helper.c | 1 + target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/vec_helper.c | 1 + 9 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 target/arm/helper-a64.h rename target/arm/tcg/{helper-a64.h =3D> helper-a64-defs.h} (100%) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h new file mode 100644 index 00000000000..cda7e039b72 --- /dev/null +++ b/target/arm/helper-a64.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_A64_H +#define HELPER_A64_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-a64-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_A64_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 44c7f3ed751..79f8de1e169 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -3,7 +3,6 @@ #include "tcg/helper.h" =20 #ifdef TARGET_AARCH64 -#include "tcg/helper-a64.h" #include "tcg/helper-sve.h" #include "tcg/helper-sme.h" #endif diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64-defs.h similarity index 100% rename from target/arm/tcg/helper-a64.h rename to target/arm/tcg/helper-a64-defs.h diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index e4d2c2e3928..07ddfb895dd 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" +#include "helper-a64.h" #include "qemu/host-utils.h" #include "qemu/log.h" #include "qemu/main-loop.h" @@ -43,6 +44,9 @@ #endif #include "vec_internal.h" =20 +#define HELPER_H "tcg/helper-a64-defs.h" +#include "exec/helper-info.c.inc" + /* C2.4.7 Multiply and divide */ /* special cases for 0 and LLONG_MIN are mandated by the standard */ uint64_t HELPER(udiv64)(uint64_t num, uint64_t den) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 08b8e7176a6..01b7f099f4a 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -31,6 +31,7 @@ #endif #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" +#include "helper-a64.h" #include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index c591c3052c3..5a20117ae89 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -22,6 +22,7 @@ #include "internals.h" #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" +#include "helper-a64.h" #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index c442fcb540d..0600eea47c7 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" +#include "helper-a64.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 7a8cd99e004..1a54337b6a8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "exec/target_page.h" +#include "helper-a64.h" #include "translate.h" #include "translate-a64.h" #include "qemu/log.h" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 33a136b90a6..7451a283efa 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "helper-a64.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 18 Feb 2026 20:02:13 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , anjo@rev.ng, Peter Maydell , Jim MacArthur Subject: [PATCH v4 05/14] target/arm: extract helper-sve.h from helper.h Date: Wed, 18 Feb 2026 20:01:41 -0800 Message-ID: <20260219040150.2098396-6-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> References: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771473933762154100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper-sve.h | 14 ++++++++++++++ target/arm/helper.h | 1 - target/arm/tcg/{helper-sve.h =3D> helper-sve-defs.h} | 0 target/arm/tcg/gengvec64.c | 3 ++- target/arm/tcg/sve_helper.c | 3 +++ target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/translate-sme.c | 2 ++ target/arm/tcg/translate-sve.c | 2 ++ target/arm/tcg/vec_helper.c | 1 + 9 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 target/arm/helper-sve.h rename target/arm/tcg/{helper-sve.h =3D> helper-sve-defs.h} (100%) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h new file mode 100644 index 00000000000..ae4f46c70a0 --- /dev/null +++ b/target/arm/helper-sve.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_SVE_H +#define HELPER_SVE_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-sve-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_SVE_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 79f8de1e169..2f724643d39 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -3,6 +3,5 @@ #include "tcg/helper.h" =20 #ifdef TARGET_AARCH64 -#include "tcg/helper-sve.h" #include "tcg/helper-sme.h" #endif diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve-defs.h similarity index 100% rename from target/arm/tcg/helper-sve.h rename to target/arm/tcg/helper-sve-defs.h diff --git a/target/arm/tcg/gengvec64.c b/target/arm/tcg/gengvec64.c index c425d2b1490..c7bdd1ea82f 100644 --- a/target/arm/tcg/gengvec64.c +++ b/target/arm/tcg/gengvec64.c @@ -18,10 +18,11 @@ */ =20 #include "qemu/osdep.h" +#include "cpu.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" =20 - static void gen_rax1_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) { tcg_gen_rotli_i64(d, m, 1); diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 0600eea47c7..16e528e41a6 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -25,6 +25,7 @@ #include "exec/target_page.h" #include "exec/tlb-flags.h" #include "helper-a64.h" +#include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" @@ -38,6 +39,8 @@ #include "user/page-protection.h" #endif =20 +#define HELPER_H "tcg/helper-sve-defs.h" +#include "exec/helper-info.c.inc" =20 /* Return a value for NZCV as per the ARM PredTest pseudofunction. * diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1a54337b6a8..31fb2ea9cc3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "exec/target_page.h" #include "helper-a64.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" #include "qemu/log.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 091c56da4f4..463ece97ab8 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -18,6 +18,8 @@ */ =20 #include "qemu/osdep.h" +#include "cpu.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" =20 diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 64adb5c1ce3..c68a44aff8c 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -18,6 +18,8 @@ */ =20 #include "qemu/osdep.h" +#include "cpu.h" +#include "helper-sve.h" #include "translate.h" #include "translate-a64.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 7451a283efa..bc64c8ff374 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "helper-a64.h" +#include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 18 Feb 2026 20:02:14 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , anjo@rev.ng, Peter Maydell , Jim MacArthur Subject: [PATCH v4 06/14] target/arm: extract helper-sme.h from helper.h Date: Wed, 18 Feb 2026 20:01:42 -0800 Message-ID: <20260219040150.2098396-7-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> References: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771473815801154100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper-sme.h | 14 ++++++++++++++ target/arm/helper.h | 4 ---- target/arm/tcg/{helper-sme.h =3D> helper-sme-defs.h} | 0 target/arm/tcg/sme_helper.c | 3 +++ target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/translate-sme.c | 1 + target/arm/tcg/translate-sve.c | 1 + target/arm/tcg/vec_helper.c | 1 + 8 files changed, 21 insertions(+), 4 deletions(-) create mode 100644 target/arm/helper-sme.h rename target/arm/tcg/{helper-sme.h =3D> helper-sme-defs.h} (100%) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h new file mode 100644 index 00000000000..27c85fdeef1 --- /dev/null +++ b/target/arm/helper-sme.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef HELPER_SME_H +#define HELPER_SME_H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-sme-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_SME_H */ diff --git a/target/arm/helper.h b/target/arm/helper.h index 2f724643d39..b1e83196b3b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1,7 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ =20 #include "tcg/helper.h" - -#ifdef TARGET_AARCH64 -#include "tcg/helper-sme.h" -#endif diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme-defs.h similarity index 100% rename from target/arm/tcg/helper-sme.h rename to target/arm/tcg/helper-sme-defs.h diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 075360d8b8a..7729732369f 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -22,6 +22,7 @@ #include "internals.h" #include "tcg/tcg-gvec-desc.h" #include "exec/helper-proto.h" +#include "helper-sme.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/helper-retaddr.h" #include "qemu/int128.h" @@ -29,6 +30,8 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" =20 +#define HELPER_H "tcg/helper-sme-defs.h" +#include "exec/helper-info.c.inc" =20 static bool vectors_overlap(ARMVectorReg *x, unsigned nx, ARMVectorReg *y, unsigned ny) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 31fb2ea9cc3..5d261a5e32b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "exec/target_page.h" #include "helper-a64.h" +#include "helper-sme.h" #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 463ece97ab8..7d25ac5a51f 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper-sme.h" #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index c68a44aff8c..db25636fa3b 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper-sme.h" #include "helper-sve.h" #include "translate.h" #include "translate-a64.h" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index bc64c8ff374..a070ac90579 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "helper-a64.h" +#include "helper-sme.h" #include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[216.71.219.44]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1a73200asm147636225ad.36.2026.02.18.20.02.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Feb 2026 20:02:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771473736; x=1772078536; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VA/qlQJvE8uq8B0wfP8QzURuC1Jx2blScgULUKFJUFo=; b=ysYNwZXvvUkAVLpk3NZdUulGXdczpr4CgAxgzvWik42ehTAoOXBFATpyXZjhHWEWAg bSLCPrf9F30qbTTrnGvi4VxzbxYzVDoRLuEvH2qbmxdfnc8H4Y818Bkl1J53XoN0hAhz Gj1xR9cG3Bd7R+UdgA86aVF2VQvHP7aDKe5wavLEdH6Q05AOaJvOONmu+YWyvwTKBpN+ HBJbvCQzOT7bL9eQEsKPvGfmqe7B2TxHWWPNndyMTRQAUSlY5HmloDrQOMNgscBqSpQm z0x3gSQEv298tgUZBbKIo4WzlaWUZTwXfKFZYrm27/7IREUXtEY6V682QK1clqW0WXGG Ku1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771473736; x=1772078536; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=VA/qlQJvE8uq8B0wfP8QzURuC1Jx2blScgULUKFJUFo=; b=XR7VSQij8w/yaDu1kTJKaORcohvkPwffWCt03+4dlgL14nffhmP1uEch8LWfhQWqtD 5uuAyRGoJhBOyzNgImmH5ngIPDV7SRhXCPC06DRL3LJTW6Iy+ryla4A89tUemkmEt0DD pI9/aJKYA5Fm92tNGKnp5qGbgVgc4fwUFEFndXM7gPT7ymd9YEGBag4TqGbSV8dfhFw8 VtvpLYRWBiZ2c1i8XZBg8Z0hTJ+TR+hw3vSmlKDkP9vxfTj73pvI/tFp9qg2bJuUY1Fx NjK5alGjIuZk0hQgUcdfvJYinpkvn/HHbp+PgW3Am8/JXGlH3rZAhAeOJo68cIKocs/l j3gQ== X-Gm-Message-State: AOJu0Yz7rRN2N0sZrGPmtwjcbDjUhVKXfIh5MBIJ+M3315bCrfyistat NIqWeERIYWQuteG7u8hzdPDmqlFF7aAsZunxjTO0gm/UOkHGUOkwVEXdJS6SVvdWIJbHVGio1k3 T/YKL X-Gm-Gg: AZuq6aL0T+LOv9eFgjcm64Lm6lbcDJRCueK7YtUO8q+UE0TGKDmRqil2TtLLgmJHwBD usL/0Ccb5VF3MSNwU+5ooqivjvYu/plR79tlJk0EwBA4BPLvFqtLNdEILjdtIx4JnVyVUL0fWMo KEc7wCaM/HDzGaQo4n4WR4enRj09DL3mVjxv9RtuLPKED0B6SC7zUFWhsV1tkHAFdCLCjYa2uPK g3C3LQ87aS3yFvR9M3zSwIrUE+qvhnV2ZzoIS523n9Fw1CkoCRGOdI8ksM4dVnUc3+3E4cr/R+m u98KtZdTcTSaM6a5icN31J8pjWNX2pCPK3NF7UKSu9e+/P+Q0yeZjUp4/6JHm0zhqD9wpR29AbS lpFtobfjm+KyBpP/aoXh3exh7Z7E9jdATYGRGpXGA03/dLZKQzds0+Q5aaEesSLtChLenoQB67f XTyc8IUcFS0OnsoVU+M75IfW4HUnPfKkXKFPdJZd6ILqS8qoAVspNyqlENaFxSIE5Ufi49bHPIJ RIz X-Received: by 2002:a17:903:320e:b0:2a9:5c0b:e5f4 with SMTP id d9443c01a7336-2ab505c0e87mr162715635ad.28.1771473735974; Wed, 18 Feb 2026 20:02:15 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , anjo@rev.ng, Peter Maydell , Jim MacArthur Subject: [PATCH v4 07/14] tcg: move tcg_use_softmmu to tcg/tcg-internal.h Date: Wed, 18 Feb 2026 20:01:43 -0800 Message-ID: <20260219040150.2098396-8-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> References: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771473877030154100 Content-Type: text/plain; charset="utf-8" In next commit, we'll apply same helper pattern for base helpers remaining. Our new helper pattern always include helper-*-common.h, which ends up including include/tcg/tcg.h, which contains one occurrence of CONFIG_USER_ONLY. Thus, common files not being duplicated between system and target relying on helpers will fail to compile. Existing occurrences are: - target/arm/tcg/arith_helper.c - target/arm/tcg/crypto_helper.c This occurrence of CONFIG_USER_ONLY is for defining variable tcg_use_softmmu, and we rely on dead code elimination with it in various tcg-target.c.inc. Thus, move its definition to tcg/tcg-internal.h, so helpers can be included by common files. Also, change it to a define, as it has fixed values for now. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- include/tcg/tcg.h | 6 ------ tcg/tcg-internal.h | 6 ++++++ tcg/tcg.c | 4 ---- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 60942ce05c2..45c7e118c3d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -445,12 +445,6 @@ static inline bool temp_readonly(TCGTemp *ts) return ts->kind >=3D TEMP_FIXED; } =20 -#ifdef CONFIG_USER_ONLY -extern bool tcg_use_softmmu; -#else -#define tcg_use_softmmu true -#endif - extern __thread TCGContext *tcg_ctx; extern const void *tcg_code_gen_epilogue; extern uintptr_t tcg_splitwx_diff; diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 2cbfb5d5caa..26156846120 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -34,6 +34,12 @@ extern TCGContext **tcg_ctxs; extern unsigned int tcg_cur_ctxs; extern unsigned int tcg_max_ctxs; =20 +#ifdef CONFIG_USER_ONLY +#define tcg_use_softmmu false +#else +#define tcg_use_softmmu true +#endif + void tcg_region_init(size_t tb_size, int splitwx, unsigned max_threads); bool tcg_region_alloc(TCGContext *s); void tcg_region_initial_alloc(TCGContext *s); diff --git a/tcg/tcg.c b/tcg/tcg.c index e7bf4dad4ee..3111e1f4265 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -236,10 +236,6 @@ static TCGAtomAlign atom_and_align_for_opc(TCGContext = *s, MemOp opc, MemOp host_atom, bool allow_two= _ops) __attribute__((unused)); =20 -#ifdef CONFIG_USER_ONLY -bool tcg_use_softmmu; -#endif - TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; =20 --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771473830; cv=none; d=zohomail.com; s=zohoarc; b=T8uNXKCJ6dcB99VRMLg0l+9Lqg2z56KNs/mzGpA7+sHBYou9vXKdPNA8EUiUGssuVD0fMEda6rR+G1vKkydvuWXMFx6gTO2aU22dE/8WT7kmyynDbcuRef+R4Ld0OQEAhelQNDwblo+U+jdUw1Ga6IXmpJSRYyJh037lhpGwLy8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771473830; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vZWRAyQhu2Io6unvYUCtXe2P61Hg6zFaFVtChf0tU2A=; b=Y6spJ92GkdZEnmnvJL/m25WjlwyVDnYkZ0wAoFUDLHwBhOzcE3JeeZwvU3i8h7Mniobpf+JA8F24fMwzcKSJxlAElTqQgnBc1WkMdseWX0e/cgsIlI3tlbheQvboUskpoSUBsKLFhl6ZoSHN77cSMHhSOaKK5IBzgtGdhwjVvxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771473830002475.37643990049037; Wed, 18 Feb 2026 20:03:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vsvFJ-0008Tp-CN; Wed, 18 Feb 2026 23:02:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vsvF7-0008P5-Hg for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:21 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vsvF4-0001Er-Lw for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:21 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2a95bfdb31eso1994075ad.3 for ; Wed, 18 Feb 2026 20:02:18 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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This way, all helpers use the same pattern, and helper include details are limited to those headers. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/helper.h | 13 ++++++++++++- target/arm/tcg/{helper.h =3D> helper-defs.h} | 0 target/arm/tcg/translate.h | 2 +- target/arm/tcg/arith_helper.c | 4 +--- target/arm/tcg/crypto_helper.c | 4 +--- target/arm/tcg/debug.c | 4 +--- target/arm/tcg/helper-a64.c | 2 +- target/arm/tcg/hflags.c | 4 +--- target/arm/tcg/m_helper.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/mve_helper.c | 2 +- target/arm/tcg/neon_helper.c | 4 +--- target/arm/tcg/op_helper.c | 2 +- target/arm/tcg/pauth_helper.c | 2 +- target/arm/tcg/psci.c | 2 +- target/arm/tcg/sme_helper.c | 2 +- target/arm/tcg/sve_helper.c | 2 +- target/arm/tcg/tlb_helper.c | 4 +--- target/arm/tcg/translate.c | 9 ++++----- target/arm/tcg/vec_helper.c | 2 +- target/arm/tcg/vfp_helper.c | 4 +--- 21 files changed, 34 insertions(+), 38 deletions(-) rename target/arm/tcg/{helper.h =3D> helper-defs.h} (100%) diff --git a/target/arm/helper.h b/target/arm/helper.h index b1e83196b3b..b1c26c180ea 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1,3 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ =20 -#include "tcg/helper.h" +#ifndef HELPER__H +#define HELPER__H + +#include "exec/helper-proto-common.h" +#include "exec/helper-gen-common.h" + +#define HELPER_H "tcg/helper-defs.h" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER__H */ diff --git a/target/arm/tcg/helper.h b/target/arm/tcg/helper-defs.h similarity index 100% rename from target/arm/tcg/helper.h rename to target/arm/tcg/helper-defs.h diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 1e30d7c77c3..027769271c9 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -6,7 +6,7 @@ #include "tcg/tcg-op-gvec.h" #include "exec/translator.h" #include "exec/translation-block.h" -#include "exec/helper-gen.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" =20 diff --git a/target/arm/tcg/arith_helper.c b/target/arm/tcg/arith_helper.c index 97c6362992c..cc081c8f966 100644 --- a/target/arm/tcg/arith_helper.c +++ b/target/arm/tcg/arith_helper.c @@ -8,11 +8,9 @@ #include "qemu/osdep.h" #include "qemu/bswap.h" #include "qemu/crc32c.h" +#include "helper.h" #include /* for crc32 */ =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* * Note that signed overflow is undefined in C. The following routines are * careful to use unsigned types where modulo arithmetic is required. diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 3428bd1bf0b..11977cb7723 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -15,11 +15,9 @@ #include "tcg/tcg-gvec-desc.h" #include "crypto/aes-round.h" #include "crypto/sm4.h" +#include "helper.h" #include "vec_internal.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - union CRYPTO_STATE { uint8_t bytes[16]; uint32_t words[4]; diff --git a/target/arm/tcg/debug.c b/target/arm/tcg/debug.c index 7dfb291a9bf..5214e3c08a8 100644 --- a/target/arm/tcg/debug.c +++ b/target/arm/tcg/debug.c @@ -8,15 +8,13 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "cpregs.h" #include "exec/watchpoint.h" #include "system/tcg.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) { diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 07ddfb895dd..2dec587d386 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -21,7 +21,7 @@ #include "qemu/units.h" #include "cpu.h" #include "gdbstub/helpers.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "helper-a64.h" #include "qemu/host-utils.h" #include "qemu/log.h" diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 5c9b9bec3b2..7e6f8d36475 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -7,15 +7,13 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "exec/translation-block.h" #include "accel/tcg/cpu-ops.h" #include "cpregs.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - static inline bool fgt_svc(CPUARMState *env, int el) { /* diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 0c3832a47fd..a0cb8cb021e 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -8,10 +8,10 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "gdbstub/helpers.h" -#include "exec/helper-proto.h" #include "qemu/main-loop.h" #include "qemu/bitops.h" #include "qemu/log.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 01b7f099f4a..a9fb979f639 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "exec/target_page.h" #include "exec/page-protection.h" @@ -32,7 +33,6 @@ #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/probe.h" #include "helper-a64.h" -#include "exec/helper-proto.h" #include "exec/tlb-flags.h" #include "accel/tcg/cpu-ops.h" #include "qapi/error.h" diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index f33642df1f9..a67d90d6c75 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -19,10 +19,10 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "helper-mve.h" #include "internals.h" #include "vec_internal.h" -#include "exec/helper-proto.h" #include "accel/tcg/cpu-ldst.h" #include "tcg/tcg.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index 8d288f3a700..69147969b23 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -9,13 +9,11 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "vec_internal.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) =20 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index c7ab462d1d1..4d708635068 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -19,8 +19,8 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "exec/target_page.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 5a20117ae89..67c0d59d9e9 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -19,11 +19,11 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "accel/tcg/cpu-ldst.h" #include "helper-a64.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" =20 diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 2d409301578..bca6058e41a 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -18,7 +18,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "kvm-consts.h" #include "qemu/main-loop.h" #include "system/runstate.h" diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 7729732369f..ab5999c5925 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -21,7 +21,7 @@ #include "cpu.h" #include "internals.h" #include "tcg/tcg-gvec-desc.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "helper-sme.h" #include "accel/tcg/cpu-ldst.h" #include "accel/tcg/helper-retaddr.h" diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 16e528e41a6..062d8881bd0 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -21,9 +21,9 @@ #include "cpu.h" #include "internals.h" #include "exec/page-protection.h" -#include "exec/helper-proto.h" #include "exec/target_page.h" #include "exec/tlb-flags.h" +#include "helper.h" #include "helper-a64.h" #include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 5c689d3b69f..565954269f9 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -7,12 +7,10 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* * Returns true if the stage 1 translation regime is using LPAE format page * tables. Used when raising alignment exceptions, whose FSR changes depen= ding diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 580ec86c68c..3f57006f9df 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -26,14 +26,10 @@ #include "arm_ldst.h" #include "semihosting/semihost.h" #include "cpregs.h" -#include "exec/helper-proto.h" #include "exec/target_page.h" +#include "helper.h" #include "helper-mve.h" =20 -#define HELPER_H "helper.h" -#include "exec/helper-info.c.inc" -#undef HELPER_H - #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ @@ -45,6 +41,9 @@ #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7) #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) =20 +#define HELPER_H "tcg/helper-defs.h" +#include "exec/helper-info.c.inc" + /* These are TCG globals which alias CPUARMState fields */ static TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index a070ac90579..1223b843bf1 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" +#include "helper.h" #include "helper-a64.h" #include "helper-sme.h" #include "helper-sve.h" diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c index e156e3774ad..45f2eb0930f 100644 --- a/target/arm/tcg/vfp_helper.c +++ b/target/arm/tcg/vfp_helper.c @@ -19,14 +19,12 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "helper.h" #include "internals.h" #include "cpu-features.h" #include "fpu/softfloat.h" #include "qemu/log.h" =20 -#define HELPER_H "tcg/helper.h" -#include "exec/helper-proto.h.inc" - /* * Set the float_status behaviour to match the Arm defaults: * * tininess-before-rounding --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771473941; cv=none; d=zohomail.com; s=zohoarc; b=RcEjkKfiBAkIR6rYp52qpMF21mhmFQPdFifxBAx6wI3vUuJPEk+YuhGcRJabj74s8YVINRLTggRDKb3Mkht8hFxXn10El8BEkMhVPm8FX27WPZeWeGl40fPth53Vh0UyA1erXzTWeTKna5GmSCSLrrUdnBZIq+OUBDDZrpp9Z10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771473941; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=uvHffU5N51i03Mxn26mXTr3v2G/A6vAtzhoWHQnpn8U=; b=g+lC5BZv/8CPxNVHu55qKxY60INlnqJJdohtwcu0CZ4RvWnQDBWjtwb4P7uhnhQle4mdussPyeE8EfvxedJLcUrl0aqlIcpXRXnYOsNR1gXJ5x1+B2VnxmFRvLaxhjY+pvUswGXywAt0cw2ApFgTL0AssRH2ICg8K+6qZUwhKGs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17714739415651001.4837126009745; Wed, 18 Feb 2026 20:05:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vsvFK-0008U0-Ix; Wed, 18 Feb 2026 23:02:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vsvF8-0008PN-02 for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:22 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vsvF5-0001FF-N8 for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:21 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2aadc18f230so2810575ad.3 for ; Wed, 18 Feb 2026 20:02:19 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier --- target/arm/tcg/psci.c | 2 +- target/arm/tcg/meson.build | 5 +---- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index bca6058e41a..56754bde951 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -68,7 +68,7 @@ void arm_handle_psci_call(ARMCPU *cpu) CPUARMState *env =3D &cpu->env; uint64_t param[4]; uint64_t context_id, mpidr; - target_ulong entry; + uint64_t entry; int32_t ret =3D 0; int i; =20 diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 6e9aed3e5de..85277dba8da 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -49,10 +49,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sve_helper.c', )) =20 -arm_system_ss.add(files( - 'psci.c', -)) - arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) =20 @@ -68,6 +64,7 @@ arm_common_system_ss.add(files( 'debug.c', 'hflags.c', 'neon_helper.c', + 'psci.c', 'tlb_helper.c', 'tlb-insns.c', 'vfp_helper.c', --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771473933; cv=none; d=zohomail.com; s=zohoarc; b=NXl9p9pVvbjmlhcP8LOYpiB4SWBFSW6pf834YkD0tFY4eTuc/WSe2C/1MhAvzARKQJeZ8a2fUfzBOoNJW10De72BFS06jm2SImNsXXjWynrkbMJqEYXHm7Ksrx5F30VbwoGyXXoXc1uSuaBPiymBYJJU/9hmXNFo9XfT+jlpVpc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771473933; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=w731RNlMT2uStSKIDhJqip6UtoYH7ZCTQWwr2BG+eck=; b=m0iBiDX9GzczB2aXnlFowJtAwLKlbX1shqlgdNIsGfHu8PX3xq9oqbZORx94EAHGlGk184E9bkzgqZ9ADpJETtTcSrkcF2+xvV6yDHSYNA6uI/pbz24SvDbqhunqmDRgABf9ZJZ4B3TGqWsc1JKYJ6nBfuBxbE6S1OT9WXzCRF0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771473933350329.76654848896385; Wed, 18 Feb 2026 20:05:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vsvFR-00005m-F5; Wed, 18 Feb 2026 23:02:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vsvF8-0008PM-0N for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:22 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vsvF6-0001Fk-Ee for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:21 -0500 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-2a95de4b5cbso4076325ad.1 for ; Wed, 18 Feb 2026 20:02:20 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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Wed, 18 Feb 2026 20:02:19 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , anjo@rev.ng, Peter Maydell , Jim MacArthur Subject: [PATCH v4 10/14] target/arm/tcg/cpu-v7m.c: make compilation unit common Date: Wed, 18 Feb 2026 20:01:46 -0800 Message-ID: <20260219040150.2098396-11-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> References: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771473935048158500 Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier --- target/arm/tcg/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 85277dba8da..cabf65e6236 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -49,7 +49,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'sve_helper.c', )) =20 -arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c')) +arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c= ')) arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c')) =20 arm_common_ss.add(zlib) --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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As well, DO_3OP_PAIR was defined twice, so rename the second variant to DO_3OP_PAIR_NO_STATUS to reflect what it does. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/tcg/vec_internal.h | 49 ++++++++ target/arm/tcg/vec_helper.c | 225 +++------------------------------- target/arm/tcg/vec_helper64.c | 142 +++++++++++++++++++++ target/arm/tcg/meson.build | 4 +- 4 files changed, 212 insertions(+), 208 deletions(-) create mode 100644 target/arm/tcg/vec_helper64.c diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h index cf41b03dbcd..4edd2b4fc18 100644 --- a/target/arm/tcg/vec_internal.h +++ b/target/arm/tcg/vec_internal.h @@ -450,4 +450,53 @@ static inline void depositn(uint64_t *p, unsigned pos, } } =20 +#define DO_3OP(NAME, FUNC, TYPE) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, = \ + float_status * stat, uint32_t desc) = \ +{ = \ + intptr_t i, oprsz =3D simd_oprsz(desc); = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + for (i =3D 0; i < oprsz / sizeof(TYPE); i++) { = \ + d[i] =3D FUNC(n[i], m[i], stat); = \ + } = \ + clear_tail(d, oprsz, simd_maxsz(desc)); = \ +} + +#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, = \ + float_status * stat, uint32_t desc) = \ +{ = \ + ARMVectorReg scratch; = \ + intptr_t oprsz =3D simd_oprsz(desc); = \ + intptr_t half =3D oprsz / sizeof(TYPE) / 2; = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + if (unlikely(d =3D=3D m)) { = \ + m =3D memcpy(&scratch, m, oprsz); = \ + } = \ + for (intptr_t i =3D 0; i < half; ++i) { = \ + d[H(i)] =3D FUNC(n[H(i * 2)], n[H(i * 2 + 1)], stat); = \ + } = \ + for (intptr_t i =3D 0; i < half; ++i) { = \ + d[H(i + half)] =3D FUNC(m[H(i * 2)], m[H(i * 2 + 1)], stat); = \ + } = \ + clear_tail(d, oprsz, simd_maxsz(desc)); = \ +} + +#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) = \ +void HELPER(NAME)(void *vd, void *vn, void *vm, = \ + float_status * stat, uint32_t desc) = \ +{ = \ + intptr_t i, j, oprsz =3D simd_oprsz(desc); = \ + intptr_t segment =3D MIN(16, oprsz) / sizeof(TYPE); = \ + intptr_t idx =3D simd_data(desc); = \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + for (i =3D 0; i < oprsz / sizeof(TYPE); i +=3D segment) { = \ + TYPE mm =3D m[H(i + idx)]; = \ + for (j =3D 0; j < segment; j++) { = \ + d[i + j] =3D ADD(d[i + j], MUL(n[i + j], mm, stat), stat); = \ + } = \ + } = \ + clear_tail(d, oprsz, simd_maxsz(desc)); = \ +} + #endif /* TARGET_ARM_VEC_INTERNAL_H */ diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 1223b843bf1..91e98d28aea 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -20,9 +20,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "helper.h" -#include "helper-a64.h" -#include "helper-sme.h" -#include "helper-sve.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" @@ -1458,18 +1455,6 @@ static float32 float32_rsqrts_nf(float32 op1, float3= 2 op2, float_status *stat) return float32_div(op1, float32_two, stat); } =20 -#define DO_3OP(NAME, FUNC, TYPE) \ -void HELPER(NAME)(void *vd, void *vn, void *vm, = \ - float_status *stat, uint32_t desc) = \ -{ = \ - intptr_t i, oprsz =3D simd_oprsz(desc); = \ - TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ - for (i =3D 0; i < oprsz / sizeof(TYPE); i++) { = \ - d[i] =3D FUNC(n[i], m[i], stat); = \ - } = \ - clear_tail(d, oprsz, simd_maxsz(desc)); = \ -} - DO_3OP(gvec_fadd_b16, bfloat16_add, float16) DO_3OP(gvec_fadd_h, float16_add, float16) DO_3OP(gvec_fadd_s, float32_add, float32) @@ -1541,49 +1526,6 @@ DO_3OP(gvec_recps_nf_s, float32_recps_nf, float32) DO_3OP(gvec_rsqrts_nf_h, float16_rsqrts_nf, float16) DO_3OP(gvec_rsqrts_nf_s, float32_rsqrts_nf, float32) =20 -#ifdef TARGET_AARCH64 -DO_3OP(gvec_fdiv_h, float16_div, float16) -DO_3OP(gvec_fdiv_s, float32_div, float32) -DO_3OP(gvec_fdiv_d, float64_div, float64) - -DO_3OP(gvec_fmulx_h, helper_advsimd_mulxh, float16) -DO_3OP(gvec_fmulx_s, helper_vfp_mulxs, float32) -DO_3OP(gvec_fmulx_d, helper_vfp_mulxd, float64) - -DO_3OP(gvec_recps_h, helper_recpsf_f16, float16) -DO_3OP(gvec_recps_s, helper_recpsf_f32, float32) -DO_3OP(gvec_recps_d, helper_recpsf_f64, float64) - -DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16) -DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32) -DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64) - -DO_3OP(gvec_ah_recps_h, helper_recpsf_ah_f16, float16) -DO_3OP(gvec_ah_recps_s, helper_recpsf_ah_f32, float32) -DO_3OP(gvec_ah_recps_d, helper_recpsf_ah_f64, float64) - -DO_3OP(gvec_ah_rsqrts_h, helper_rsqrtsf_ah_f16, float16) -DO_3OP(gvec_ah_rsqrts_s, helper_rsqrtsf_ah_f32, float32) -DO_3OP(gvec_ah_rsqrts_d, helper_rsqrtsf_ah_f64, float64) - -DO_3OP(gvec_ah_fmax_h, helper_vfp_ah_maxh, float16) -DO_3OP(gvec_ah_fmax_s, helper_vfp_ah_maxs, float32) -DO_3OP(gvec_ah_fmax_d, helper_vfp_ah_maxd, float64) - -DO_3OP(gvec_ah_fmin_h, helper_vfp_ah_minh, float16) -DO_3OP(gvec_ah_fmin_s, helper_vfp_ah_mins, float32) -DO_3OP(gvec_ah_fmin_d, helper_vfp_ah_mind, float64) - -DO_3OP(gvec_fmax_b16, bfloat16_max, bfloat16) -DO_3OP(gvec_fmin_b16, bfloat16_min, bfloat16) -DO_3OP(gvec_fmaxnum_b16, bfloat16_maxnum, bfloat16) -DO_3OP(gvec_fminnum_b16, bfloat16_minnum, bfloat16) -DO_3OP(gvec_ah_fmax_b16, helper_sme2_ah_fmax_b16, bfloat16) -DO_3OP(gvec_ah_fmin_b16, helper_sme2_ah_fmin_b16, bfloat16) - -#endif -#undef DO_3OP - /* Non-fused multiply-add (unlike float16_muladd etc, which are fused) */ static float16 float16_muladd_nf(float16 dest, float16 op1, float16 op2, float_status *stat) @@ -1769,23 +1711,6 @@ DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, H8) =20 #undef DO_MLA_IDX =20 -#define DO_FMUL_IDX(NAME, ADD, MUL, TYPE, H) = \ -void HELPER(NAME)(void *vd, void *vn, void *vm, = \ - float_status *stat, uint32_t desc) = \ -{ = \ - intptr_t i, j, oprsz =3D simd_oprsz(desc); = \ - intptr_t segment =3D MIN(16, oprsz) / sizeof(TYPE); = \ - intptr_t idx =3D simd_data(desc); = \ - TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ - for (i =3D 0; i < oprsz / sizeof(TYPE); i +=3D segment) { = \ - TYPE mm =3D m[H(i + idx)]; = \ - for (j =3D 0; j < segment; j++) { = \ - d[i + j] =3D ADD(d[i + j], MUL(n[i + j], mm, stat), stat); = \ - } = \ - } = \ - clear_tail(d, oprsz, simd_maxsz(desc)); = \ -} - #define nop(N, M, S) (M) =20 DO_FMUL_IDX(gvec_fmul_idx_b16, nop, bfloat16_mul, float16, H2) @@ -1793,14 +1718,6 @@ DO_FMUL_IDX(gvec_fmul_idx_h, nop, float16_mul, float= 16, H2) DO_FMUL_IDX(gvec_fmul_idx_s, nop, float32_mul, float32, H4) DO_FMUL_IDX(gvec_fmul_idx_d, nop, float64_mul, float64, H8) =20 -#ifdef TARGET_AARCH64 - -DO_FMUL_IDX(gvec_fmulx_idx_h, nop, helper_advsimd_mulxh, float16, H2) -DO_FMUL_IDX(gvec_fmulx_idx_s, nop, helper_vfp_mulxs, float32, H4) -DO_FMUL_IDX(gvec_fmulx_idx_d, nop, helper_vfp_mulxd, float64, H8) - -#endif - #undef nop =20 /* @@ -1812,8 +1729,6 @@ DO_FMUL_IDX(gvec_fmla_nf_idx_s, float32_add, float32_= mul, float32, H4) DO_FMUL_IDX(gvec_fmls_nf_idx_h, float16_sub, float16_mul, float16, H2) DO_FMUL_IDX(gvec_fmls_nf_idx_s, float32_sub, float32_mul, float32, H4) =20 -#undef DO_FMUL_IDX - #define DO_FMLA_IDX(NAME, TYPE, H, NEGX, NEGF) = \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, = \ float_status *stat, uint32_t desc) = \ @@ -2530,31 +2445,6 @@ void HELPER(neon_pmull_h)(void *vd, void *vn, void *= vm, uint32_t desc) clear_tail(d, 16, simd_maxsz(desc)); } =20 -#ifdef TARGET_AARCH64 -void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) -{ - int shift =3D simd_data(desc) * 8; - intptr_t i, opr_sz =3D simd_oprsz(desc); - uint64_t *d =3D vd, *n =3D vn, *m =3D vm; - - for (i =3D 0; i < opr_sz / 8; ++i) { - d[i] =3D clmul_8x4_even(n[i] >> shift, m[i] >> shift); - } -} - -void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, uint32_t desc) -{ - intptr_t sel =3D H4(simd_data(desc)); - intptr_t i, opr_sz =3D simd_oprsz(desc); - uint32_t *n =3D vn, *m =3D vm; - uint64_t *d =3D vd; - - for (i =3D 0; i < opr_sz / 8; ++i) { - d[i] =3D clmul_32(n[2 * i + sel], m[2 * i + sel]); - } -} -#endif - #define DO_CMP0(NAME, TYPE, OP) \ void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ { \ @@ -2628,26 +2518,6 @@ DO_ABA(gvec_uaba_d, uint64_t) =20 #undef DO_ABA =20 -#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ -void HELPER(NAME)(void *vd, void *vn, void *vm, = \ - float_status *stat, uint32_t desc) = \ -{ = \ - ARMVectorReg scratch; = \ - intptr_t oprsz =3D simd_oprsz(desc); = \ - intptr_t half =3D oprsz / sizeof(TYPE) / 2; = \ - TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ - if (unlikely(d =3D=3D m)) { = \ - m =3D memcpy(&scratch, m, oprsz); = \ - } = \ - for (intptr_t i =3D 0; i < half; ++i) { = \ - d[H(i)] =3D FUNC(n[H(i * 2)], n[H(i * 2 + 1)], stat); = \ - } = \ - for (intptr_t i =3D 0; i < half; ++i) { = \ - d[H(i + half)] =3D FUNC(m[H(i * 2)], m[H(i * 2 + 1)], stat); = \ - } = \ - clear_tail(d, oprsz, simd_maxsz(desc)); = \ -} - DO_3OP_PAIR(gvec_faddp_h, float16_add, float16, H2) DO_3OP_PAIR(gvec_faddp_s, float32_add, float32, H4) DO_3OP_PAIR(gvec_faddp_d, float64_add, float64, ) @@ -2668,19 +2538,7 @@ DO_3OP_PAIR(gvec_fminnump_h, float16_minnum, float16= , H2) DO_3OP_PAIR(gvec_fminnump_s, float32_minnum, float32, H4) DO_3OP_PAIR(gvec_fminnump_d, float64_minnum, float64, ) =20 -#ifdef TARGET_AARCH64 -DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2) -DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4) -DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, ) - -DO_3OP_PAIR(gvec_ah_fminp_h, helper_vfp_ah_minh, float16, H2) -DO_3OP_PAIR(gvec_ah_fminp_s, helper_vfp_ah_mins, float32, H4) -DO_3OP_PAIR(gvec_ah_fminp_d, helper_vfp_ah_mind, float64, ) -#endif - -#undef DO_3OP_PAIR - -#define DO_3OP_PAIR(NAME, FUNC, TYPE, H) \ +#define DO_3OP_PAIR_NO_STATUS(NAME, FUNC, TYPE, H) \ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \ { \ ARMVectorReg scratch; \ @@ -2700,29 +2558,29 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uin= t32_t desc) \ } =20 #define ADD(A, B) (A + B) -DO_3OP_PAIR(gvec_addp_b, ADD, uint8_t, H1) -DO_3OP_PAIR(gvec_addp_h, ADD, uint16_t, H2) -DO_3OP_PAIR(gvec_addp_s, ADD, uint32_t, H4) -DO_3OP_PAIR(gvec_addp_d, ADD, uint64_t, ) +DO_3OP_PAIR_NO_STATUS(gvec_addp_b, ADD, uint8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_addp_h, ADD, uint16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_addp_s, ADD, uint32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_addp_d, ADD, uint64_t, /**/) #undef ADD =20 -DO_3OP_PAIR(gvec_smaxp_b, MAX, int8_t, H1) -DO_3OP_PAIR(gvec_smaxp_h, MAX, int16_t, H2) -DO_3OP_PAIR(gvec_smaxp_s, MAX, int32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_smaxp_b, MAX, int8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_smaxp_h, MAX, int16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_smaxp_s, MAX, int32_t, H4) =20 -DO_3OP_PAIR(gvec_umaxp_b, MAX, uint8_t, H1) -DO_3OP_PAIR(gvec_umaxp_h, MAX, uint16_t, H2) -DO_3OP_PAIR(gvec_umaxp_s, MAX, uint32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_umaxp_b, MAX, uint8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_umaxp_h, MAX, uint16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_umaxp_s, MAX, uint32_t, H4) =20 -DO_3OP_PAIR(gvec_sminp_b, MIN, int8_t, H1) -DO_3OP_PAIR(gvec_sminp_h, MIN, int16_t, H2) -DO_3OP_PAIR(gvec_sminp_s, MIN, int32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_sminp_b, MIN, int8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_sminp_h, MIN, int16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_sminp_s, MIN, int32_t, H4) =20 -DO_3OP_PAIR(gvec_uminp_b, MIN, uint8_t, H1) -DO_3OP_PAIR(gvec_uminp_h, MIN, uint16_t, H2) -DO_3OP_PAIR(gvec_uminp_s, MIN, uint32_t, H4) +DO_3OP_PAIR_NO_STATUS(gvec_uminp_b, MIN, uint8_t, H1) +DO_3OP_PAIR_NO_STATUS(gvec_uminp_h, MIN, uint16_t, H2) +DO_3OP_PAIR_NO_STATUS(gvec_uminp_s, MIN, uint32_t, H4) =20 -#undef DO_3OP_PAIR +#undef DO_3OP_PAIR_NO_STATUS =20 #define DO_VCVT_FIXED(NAME, FUNC, TYPE) \ void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t des= c) \ @@ -2797,53 +2655,6 @@ DO_VRINT_RMODE(gvec_vrint_rm_s, helper_rints, uint32= _t) =20 #undef DO_VRINT_RMODE =20 -#ifdef TARGET_AARCH64 -void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc) -{ - const uint8_t *indices =3D vm; - size_t oprsz =3D simd_oprsz(desc); - uint32_t rn =3D extract32(desc, SIMD_DATA_SHIFT, 5); - bool is_tbx =3D extract32(desc, SIMD_DATA_SHIFT + 5, 1); - uint32_t table_len =3D desc >> (SIMD_DATA_SHIFT + 6); - union { - uint8_t b[16]; - uint64_t d[2]; - } result; - - /* - * We must construct the final result in a temp, lest the output - * overlaps the input table. For TBL, begin with zero; for TBX, - * begin with the original register contents. Note that we always - * copy 16 bytes here to avoid an extra branch; clearing the high - * bits of the register for oprsz =3D=3D 8 is handled below. - */ - if (is_tbx) { - memcpy(&result, vd, 16); - } else { - memset(&result, 0, 16); - } - - for (size_t i =3D 0; i < oprsz; ++i) { - uint32_t index =3D indices[H1(i)]; - - if (index < table_len) { - /* - * Convert index (a byte offset into the virtual table - * which is a series of 128-bit vectors concatenated) - * into the correct register element, bearing in mind - * that the table can wrap around from V31 to V0. - */ - const uint8_t *table =3D (const uint8_t *) - aa64_vfp_qreg(env, (rn + (index >> 4)) % 32); - result.b[H1(i)] =3D table[H1(index % 16)]; - } - } - - memcpy(vd, &result, 16); - clear_tail(vd, oprsz, simd_maxsz(desc)); -} -#endif - /* * NxN -> N highpart multiply * diff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c new file mode 100644 index 00000000000..249a257177e --- /dev/null +++ b/target/arm/tcg/vec_helper64.c @@ -0,0 +1,142 @@ +/* + * ARM AdvSIMD / SVE Vector Operations + * + * Copyright (c) 2026 Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "helper.h" +#include "helper-a64.h" +#include "helper-sme.h" +#include "helper-sve.h" +#include "tcg/tcg-gvec-desc.h" +#include "fpu/softfloat.h" +#include "qemu/int128.h" +#include "crypto/clmul.h" +#include "vec_internal.h" + +DO_3OP(gvec_fdiv_h, float16_div, float16) +DO_3OP(gvec_fdiv_s, float32_div, float32) +DO_3OP(gvec_fdiv_d, float64_div, float64) + +DO_3OP(gvec_fmulx_h, helper_advsimd_mulxh, float16) +DO_3OP(gvec_fmulx_s, helper_vfp_mulxs, float32) +DO_3OP(gvec_fmulx_d, helper_vfp_mulxd, float64) + +DO_3OP(gvec_recps_h, helper_recpsf_f16, float16) +DO_3OP(gvec_recps_s, helper_recpsf_f32, float32) +DO_3OP(gvec_recps_d, helper_recpsf_f64, float64) + +DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16) +DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32) +DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64) + +DO_3OP(gvec_ah_recps_h, helper_recpsf_ah_f16, float16) +DO_3OP(gvec_ah_recps_s, helper_recpsf_ah_f32, float32) +DO_3OP(gvec_ah_recps_d, helper_recpsf_ah_f64, float64) + +DO_3OP(gvec_ah_rsqrts_h, helper_rsqrtsf_ah_f16, float16) +DO_3OP(gvec_ah_rsqrts_s, helper_rsqrtsf_ah_f32, float32) +DO_3OP(gvec_ah_rsqrts_d, helper_rsqrtsf_ah_f64, float64) + +DO_3OP(gvec_ah_fmax_h, helper_vfp_ah_maxh, float16) +DO_3OP(gvec_ah_fmax_s, helper_vfp_ah_maxs, float32) +DO_3OP(gvec_ah_fmax_d, helper_vfp_ah_maxd, float64) + +DO_3OP(gvec_ah_fmin_h, helper_vfp_ah_minh, float16) +DO_3OP(gvec_ah_fmin_s, helper_vfp_ah_mins, float32) +DO_3OP(gvec_ah_fmin_d, helper_vfp_ah_mind, float64) + +DO_3OP(gvec_fmax_b16, bfloat16_max, bfloat16) +DO_3OP(gvec_fmin_b16, bfloat16_min, bfloat16) +DO_3OP(gvec_fmaxnum_b16, bfloat16_maxnum, bfloat16) +DO_3OP(gvec_fminnum_b16, bfloat16_minnum, bfloat16) +DO_3OP(gvec_ah_fmax_b16, helper_sme2_ah_fmax_b16, bfloat16) +DO_3OP(gvec_ah_fmin_b16, helper_sme2_ah_fmin_b16, bfloat16) + +#define nop(N, M, S) (M) + +DO_FMUL_IDX(gvec_fmulx_idx_h, nop, helper_advsimd_mulxh, float16, H2) +DO_FMUL_IDX(gvec_fmulx_idx_s, nop, helper_vfp_mulxs, float32, H4) +DO_FMUL_IDX(gvec_fmulx_idx_d, nop, helper_vfp_mulxd, float64, H8) + +#undef nop + +void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + int shift =3D simd_data(desc) * 8; + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 8; ++i) { + d[i] =3D clmul_8x4_even(n[i] >> shift, m[i] >> shift); + } +} + +void HELPER(sve2_pmull_d)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t sel =3D H4(simd_data(desc)); + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint32_t *n =3D vn, *m =3D vm; + uint64_t *d =3D vd; + + for (i =3D 0; i < opr_sz / 8; ++i) { + d[i] =3D clmul_32(n[2 * i + sel], m[2 * i + sel]); + } +} + +DO_3OP_PAIR(gvec_ah_fmaxp_h, helper_vfp_ah_maxh, float16, H2) +DO_3OP_PAIR(gvec_ah_fmaxp_s, helper_vfp_ah_maxs, float32, H4) +DO_3OP_PAIR(gvec_ah_fmaxp_d, helper_vfp_ah_maxd, float64, /**/) + +DO_3OP_PAIR(gvec_ah_fminp_h, helper_vfp_ah_minh, float16, H2) +DO_3OP_PAIR(gvec_ah_fminp_s, helper_vfp_ah_mins, float32, H4) +DO_3OP_PAIR(gvec_ah_fminp_d, helper_vfp_ah_mind, float64, /**/) + +void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc) +{ + const uint8_t *indices =3D vm; + size_t oprsz =3D simd_oprsz(desc); + uint32_t rn =3D extract32(desc, SIMD_DATA_SHIFT, 5); + bool is_tbx =3D extract32(desc, SIMD_DATA_SHIFT + 5, 1); + uint32_t table_len =3D desc >> (SIMD_DATA_SHIFT + 6); + union { + uint8_t b[16]; + uint64_t d[2]; + } result; + + /* + * We must construct the final result in a temp, lest the output + * overlaps the input table. For TBL, begin with zero; for TBX, + * begin with the original register contents. Note that we always + * copy 16 bytes here to avoid an extra branch; clearing the high + * bits of the register for oprsz =3D=3D 8 is handled below. + */ + if (is_tbx) { + memcpy(&result, vd, 16); + } else { + memset(&result, 0, 16); + } + + for (size_t i =3D 0; i < oprsz; ++i) { + uint32_t index =3D indices[H1(i)]; + + if (index < table_len) { + /* + * Convert index (a byte offset into the virtual table + * which is a series of 128-bit vectors concatenated) + * into the correct register element, bearing in mind + * that the table can wrap around from V31 to V0. + */ + const uint8_t *table =3D (const uint8_t *) + aa64_vfp_qreg(env, (rn + (index >> 4)) % 32); + result.b[H1(i)] =3D table[H1(index % 16)]; + } + } + + memcpy(vd, &result, 16); + clear_tail(vd, oprsz, simd_maxsz(desc)); +} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index cabf65e6236..5f591560551 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -33,7 +33,6 @@ arm_ss.add(files( 'm_helper.c', 'mve_helper.c', 'op_helper.c', - 'vec_helper.c', )) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( @@ -47,6 +46,7 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'pauth_helper.c', 'sme_helper.c', 'sve_helper.c', + 'vec_helper64.c', )) =20 arm_common_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c= ')) @@ -67,6 +67,7 @@ arm_common_system_ss.add(files( 'psci.c', 'tlb_helper.c', 'tlb-insns.c', + 'vec_helper.c', 'vfp_helper.c', )) arm_user_ss.add(files( @@ -74,5 +75,6 @@ arm_user_ss.add(files( 'hflags.c', 'neon_helper.c', 'tlb_helper.c', + 'vec_helper.c', 'vfp_helper.c', )) --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771473940; cv=none; d=zohomail.com; s=zohoarc; b=HtxuCMOCvB7snQD8epeh9g0I9DkyMIdWnlDf2uGguk9qp2I/x+tEfZ0m74hfwOLignoA+AQEbjM1qeJB86rUIJOj3T9iUUqlEY5welqZ2klHKHanY+Yv+Pr6i3rtuWfRLTAmLBFGVCAhlWI98MTOTiMZOyLYSvG+FgRon47vWTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771473940; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=P+C4usfFJxntIkaYUwqttNHLWY0mMsZx1f8GtcALX8k=; b=Pn+WbEho/xyiaqRZxzdqW69ktWgA1GVsetLCY9s4eTcIJBhcNBAeJVNeKRzpisF3QYCEF3T69UI/mkKGP3dMErD8yx7cDoFJmBU5XchRCZ/ZfTRdNLXQbTPI3AVun38FSLIW9HbxoZnTb9YhTB7+YVdSwJWfG57Up7j5tDB/JgA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771473940984886.6243373264059; Wed, 18 Feb 2026 20:05:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vsvFH-0008TN-M5; Wed, 18 Feb 2026 23:02:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vsvFA-0008Q6-5U for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:24 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vsvF8-0001GQ-Nl for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:23 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-2ad22a5e245so3450675ad.2 for ; Wed, 18 Feb 2026 20:02:21 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. [216.71.219.44]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1a73200asm147636225ad.36.2026.02.18.20.02.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Feb 2026 20:02:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1771473741; x=1772078541; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P+C4usfFJxntIkaYUwqttNHLWY0mMsZx1f8GtcALX8k=; b=GxTnLFwjBB3f4g7D5kvDDilPjfhJXtgJoOW46N/O5LqVJiNOUX/mUqXJEcaJXZ3/tx mFaxCGiA+gMx2n3FSngIMx3qROL3cYNNQ+pap5j2op0fiegGGnd+Lhex2Gj2y5o8VVQS dJL7fAdH60dxvDW45A0Ea/5fyGguyIV0GxsLxrCsL49z+yo6ONqGe8N2Q1rPWMnsHz5z dxWOl93L1BFJ+ZHWwmNJ80yssrxTYwg41ReMTnPCgsraMd7GpYMjQTFosctGkVSdKb/2 X+seJVEDVHbDZVKUHBbe9mWZYS7CcA0n2Dw/CMjiT74ApK0Tv8Np9u/NVDLdUdzy2lg2 T0QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771473741; x=1772078541; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=P+C4usfFJxntIkaYUwqttNHLWY0mMsZx1f8GtcALX8k=; b=fi24AgSUGCnGK/zhqBHMIbReFEqjcY0S5gg+0vbOI+xmHna2ev56JQYyyGHa/v389l XvrFjHWwRiVAUoUrcRCP0QTRx4M7dcmCl1f38uadFAHP/9+XSIv960O7LkrvvW9D53be cFPmP735w4YHasiIeIDSUCZeLLQTkC2lt6Orff+8FyMUajl5bij75uZUC/OrJP3ckDBC qQ48WPzcPh3Q1f6qf5cxu4H6UorDHAKFEx9UimmahFawD5iHG8fls5BFRrzPkMl1s8XP EUrDOb44+0e/oMrgpU65EhVxeMB9ZcbmV69UngiD97qDpl8RbekEzswDMGzxIr1vIveL 1r3A== X-Gm-Message-State: AOJu0YwEGPj+cRk0aNMOL2qROsORGo/K/Prr1MoJcgyl5dgIVMolMxQx ovDscEqnbhEI+qJsHL0ihT4NcSYDeiTQVOeACjB5ItRVO7PeLKe7pavqMRJGaJVW+ykxVBSGShM 9zj8T X-Gm-Gg: AZuq6aJrWXXbZXGHmpDR+xu9FwWzWuRwG/9J0czw6miOcy9Oa4UBHUZHrJA38WbODCH Q4bjR8z07fV2DKHrN2cSffbWPjrVFDaGGgAhQdndXXnYYOnUO4RJ66FUB0a9EqV24OFWUEPb59o 6O1REF6WGafeECi+z5ztCfcboP3XtWipHShdRIK99pYe1zstr24XSLbCnVZ++P4Pb5jyAS8BVX5 dUlVPwz5Sk9WPETREWu5e6FDJOoWTVabKTlIMVO4/uiJ0Cs1Bq05Edem6jSPx7GCRPjGoCLdKK0 nNBfLQ2J77Vi9rdVw0Ppp6EBZqcfEYjIycDBLjJfn9Aun9Lh3LbOur6qgIe628yipTdVzfHjaMP rMb+h0YRdiHfxI9/Nmxnh9X38EHQupNY8me9UKMSKNHz2fzyBKbmVjXZomF3wFrUG+3lh2VVSs7 uTcSH+GlPher+YTY9oS0CyyvX36Z07vjfkFoo1IQ1ij8ywKuBa64D55Lq/sDrl4bEnN1QZ1CXdn sNE X-Received: by 2002:a17:902:f687:b0:295:99f0:6c66 with SMTP id d9443c01a7336-2ad50f63477mr40064175ad.36.1771473740760; Wed, 18 Feb 2026 20:02:20 -0800 (PST) From: Pierrick Bouvier To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Pierrick Bouvier , Paolo Bonzini , qemu-arm@nongnu.org, kvm@vger.kernel.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , anjo@rev.ng, Peter Maydell , Jim MacArthur Subject: [PATCH v4 12/14] target/arm/tcg/translate.h: replace target_ulong with vaddr Date: Wed, 18 Feb 2026 20:01:48 -0800 Message-ID: <20260219040150.2098396-13-pierrick.bouvier@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> References: <20260219040150.2098396-1-pierrick.bouvier@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1771473943018158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- target/arm/tcg/translate.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 027769271c9..2c8358dd7fa 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -18,7 +18,7 @@ */ typedef struct DisasLabel { TCGLabel *label; - target_ulong pc_save; + vaddr pc_save; } DisasLabel; =20 /* @@ -42,7 +42,7 @@ typedef struct DisasContext { DisasDelayException *delay_excp_list; =20 /* The address of the current instruction being translated. */ - target_ulong pc_curr; + vaddr pc_curr; /* * For CF_PCREL, the full value of cpu_pc is not known * (although the page offset is known). For convenience, the @@ -56,8 +56,8 @@ typedef struct DisasContext { * pc_save contains -1 to indicate that relative updates are no * longer possible. */ - target_ulong pc_save; - target_ulong page_start; + vaddr pc_save; + vaddr page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ int condjmp; --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771473932; cv=none; d=zohomail.com; s=zohoarc; b=dsELJI2UN4u6w03+qndpbtd/KsVL/aIm60+kZidqs3lPfJHz5p0Dcx4Iqriift7ZdoN79/FULe3LMnBx/0CO2CjdfeHvtWTMHXJCL1feyWX4R8rNZMRBv27WkVLfo3NonFX8Vjg440q4nX4bUxwH7WZu0n/pFqOSQPvQEm2aB6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771473932; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8BtQ7bhjPsJSS0UXCY2rgGt0bRWuOuYRQy8L3yquKrE=; b=n2KLvnRKVCPoCLiqjGFKkDIqEmM8Z1V4an/nYiW20/oAzrFe6pkCWjGcoOG2eNOIDeKAOTmnGxwaboFAG2VzbuwG71CI+rB/daWjub7Saaf9iv7KLV2CqzcuutSaiP+zs5goD/wt+qVGxQEzHZSzXsgC8f+g0paFI5u8OzsjUqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771473932728551.5496747222444; Wed, 18 Feb 2026 20:05:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vsvFR-00005V-A5; Wed, 18 Feb 2026 23:02:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vsvFC-0008RA-0l for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:27 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vsvF9-0001Gz-3m for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:25 -0500 Received: by mail-pl1-x644.google.com with SMTP id d9443c01a7336-2aae146b604so3195915ad.3 for ; Wed, 18 Feb 2026 20:02:22 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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Checked all call sites to make sure we were already passing signed values, so extending works as expected. Use vaddr for pc_curr and pc_save. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Pierrick Bouvier --- target/arm/tcg/translate-a32.h | 2 +- target/arm/tcg/translate.h | 12 ++++++------ target/arm/tcg/translate.c | 18 +++++++++--------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h index 0b1fa57965c..a8df364171b 100644 --- a/target/arm/tcg/translate-a32.h +++ b/target/arm/tcg/translate-a32.h @@ -40,7 +40,7 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele,= MemOp memop); TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs); void gen_set_cpsr(TCGv_i32 var, uint32_t mask); void gen_set_condexec(DisasContext *s); -void gen_update_pc(DisasContext *s, target_long diff); +void gen_update_pc(DisasContext *s, int64_t diff); void gen_lookup_tb(DisasContext *s); long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 2c8358dd7fa..3e3094a463e 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -27,8 +27,8 @@ typedef struct DisasLabel { typedef struct DisasDelayException { struct DisasDelayException *next; TCGLabel *lab; - target_long pc_curr; - target_long pc_save; + vaddr pc_curr; + vaddr pc_save; int condexec_mask; int condexec_cond; uint32_t excp; @@ -359,14 +359,14 @@ static inline int curr_insn_len(DisasContext *s) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_a64_update_pc(DisasContext *s, target_long diff); +void gen_a64_update_pc(DisasContext *s, int64_t diff); extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } =20 -static inline void gen_a64_update_pc(DisasContext *s, target_long diff) +static inline void gen_a64_update_pc(DisasContext *s, int64_t diff) { } #endif @@ -377,9 +377,9 @@ void arm_gen_test_cc(int cc, TCGLabel *label); MemOp pow2_align(unsigned i); void unallocated_encoding(DisasContext *s); void gen_exception_internal(int excp); -void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, +void gen_exception_insn_el(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn, uint32_t target_el); -void gen_exception_insn(DisasContext *s, target_long pc_diff, +void gen_exception_insn(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn); TCGLabel *delay_exception_el(DisasContext *s, int excp, uint32_t syn, uint32_t target_el); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 3f57006f9df..f9d1b8897d2 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -253,12 +253,12 @@ static inline int get_a32_user_mem_index(DisasContext= *s) } =20 /* The pc_curr difference for an architectural jump. */ -static target_long jmp_diff(DisasContext *s, target_long diff) +static int64_t jmp_diff(DisasContext *s, int64_t diff) { return diff + (s->thumb ? 4 : 8); } =20 -static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long di= ff) +static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, int64_t diff) { assert(s->pc_save !=3D -1); if (tb_cflags(s->base.tb) & CF_PCREL) { @@ -738,7 +738,7 @@ void gen_set_condexec(DisasContext *s) } } =20 -void gen_update_pc(DisasContext *s, target_long diff) +void gen_update_pc(DisasContext *s, int64_t diff) { gen_pc_plus_diff(s, cpu_R[15], diff); s->pc_save =3D s->pc_curr + diff; @@ -1058,7 +1058,7 @@ static void gen_exception(int excp, uint32_t syndrome) tcg_constant_i32(syndrome)); } =20 -static void gen_exception_insn_el_v(DisasContext *s, target_long pc_diff, +static void gen_exception_insn_el_v(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn, TCGv_i32 tcg_e= l) { if (s->aarch64) { @@ -1071,14 +1071,14 @@ static void gen_exception_insn_el_v(DisasContext *s= , target_long pc_diff, s->base.is_jmp =3D DISAS_NORETURN; } =20 -void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, +void gen_exception_insn_el(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn, uint32_t target_el) { gen_exception_insn_el_v(s, pc_diff, excp, syn, tcg_constant_i32(target_el)); } =20 -void gen_exception_insn(DisasContext *s, target_long pc_diff, +void gen_exception_insn(DisasContext *s, int64_t pc_diff, int excp, uint32_t syn) { if (s->aarch64) { @@ -1313,7 +1313,7 @@ static void gen_goto_ptr(void) * cpu_loop_exec. Any live exit_requests will be processed as we * enter the next TB. */ -static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, target_long= diff) +static void gen_goto_tb(DisasContext *s, unsigned tb_slot_idx, int64_t dif= f) { if (translator_use_goto_tb(&s->base, s->pc_curr + diff)) { /* @@ -1340,7 +1340,7 @@ static void gen_goto_tb(DisasContext *s, unsigned tb_= slot_idx, target_long diff) } =20 /* Jump, specifying which TB number to use if we gen_goto_tb() */ -static void gen_jmp_tb(DisasContext *s, target_long diff, int tbno) +static void gen_jmp_tb(DisasContext *s, int64_t diff, int tbno) { if (unlikely(s->ss_active)) { /* An indirect jump so that we still trigger the debug exception. = */ @@ -1383,7 +1383,7 @@ static void gen_jmp_tb(DisasContext *s, target_long d= iff, int tbno) } } =20 -static inline void gen_jmp(DisasContext *s, target_long diff) +static inline void gen_jmp(DisasContext *s, int64_t diff) { gen_jmp_tb(s, diff, 0); } --=20 2.47.3 From nobody Fri Mar 27 02:38:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1771473798; cv=none; d=zohomail.com; s=zohoarc; b=SY55+Hmw11SNYnvqXLCwIftwVUZtrGL6c8kO7aTZRnbfJsfPNlRR0aphC5pmdAZ8OAJOlyPerRdtJG9vc9mU4MXXNSx7/h4XIs/VL4aMi5PpBF+yG52QN71qLDBK5EHva86xFZBazoPcgpf9//YdS4ByZzfk/7wvND4WdRpVqqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1771473798; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WTZflre1420AW/UKhqUXzYtghEaZbDSYkcNh+uvH6MI=; b=Ubp3OicO0Nty753t4A2pn7jlYrfILbA7Skb+BbV5S/uRxhmQd46RMhcKvJT2668j20UceWUTII/Lo6xsDmgFUEfYrcARNY4XD+VXUFTZQghGAVHy/j4ZoHSTz5LkLY/n4yhcsx+R9gvhiNn7NXtkK8bb6vfRbLAxcZMAliuEae0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1771473798839213.76936872741555; Wed, 18 Feb 2026 20:03:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vsvFS-00006V-0P; Wed, 18 Feb 2026 23:02:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vsvFE-0008SF-5p for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:29 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vsvFA-0001HC-2y for qemu-devel@nongnu.org; Wed, 18 Feb 2026 23:02:27 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-2a79ded11a2so2819845ad.3 for ; Wed, 18 Feb 2026 20:02:23 -0800 (PST) Received: from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net. 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Since all arch have a single call site (in translate.c), this is as good documentation as having a single define. The notable exception is target/arm, which has two different translate files for 32/64 bits. Since it's the only one, we accept to have two call sites for this. As well, we update parameter type to use uint64_t instead of target_ulong, so it can be called from common code. Signed-off-by: Pierrick Bouvier --- include/tcg/tcg-op-common.h | 8 ++++++++ include/tcg/tcg-op.h | 29 ----------------------------- target/alpha/cpu-param.h | 2 -- target/arm/cpu-param.h | 7 ------- target/avr/cpu-param.h | 2 -- target/hexagon/cpu-param.h | 2 -- target/hppa/cpu-param.h | 2 -- target/i386/cpu-param.h | 2 -- target/loongarch/cpu-param.h | 2 -- target/m68k/cpu-param.h | 2 -- target/microblaze/cpu-param.h | 2 -- target/mips/cpu-param.h | 2 -- target/or1k/cpu-param.h | 2 -- target/ppc/cpu-param.h | 2 -- target/riscv/cpu-param.h | 7 ------- target/rx/cpu-param.h | 2 -- target/s390x/cpu-param.h | 2 -- target/sh4/cpu-param.h | 2 -- target/sparc/cpu-param.h | 2 -- target/tricore/cpu-param.h | 2 -- target/xtensa/cpu-param.h | 2 -- target/alpha/translate.c | 4 ++-- target/avr/translate.c | 2 +- target/hexagon/translate.c | 2 +- target/i386/tcg/translate.c | 2 +- target/loongarch/tcg/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/or1k/translate.c | 2 +- target/ppc/translate.c | 2 +- target/rx/translate.c | 2 +- target/sh4/translate.c | 4 ++-- target/sparc/translate.c | 2 +- target/tricore/translate.c | 2 +- target/xtensa/translate.c | 2 +- 35 files changed, 24 insertions(+), 93 deletions(-) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index f752ef440b2..e02f209c093 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -30,6 +30,14 @@ TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t o= ff, const char *name); TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t off, const char *na= me); =20 /* Generic ops. */ +static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1, + uint64_t a2) +{ + TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); + tcg_set_insn_start_param(op, 0, pc); + tcg_set_insn_start_param(op, 1, a1); + tcg_set_insn_start_param(op, 2, a2); +} =20 void gen_set_label(TCGLabel *l); void tcg_gen_br(TCGLabel *l); diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index ee379994e76..7024be938e6 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -28,35 +28,6 @@ # error Mismatch with insn-start-words.h #endif =20 -#if TARGET_INSN_START_EXTRA_WORDS =3D=3D 0 -static inline void tcg_gen_insn_start(target_ulong pc) -{ - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); - tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, 0); - tcg_set_insn_start_param(op, 2, 0); -} -#elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 1 -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) -{ - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); - tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, a1); - tcg_set_insn_start_param(op, 2, 0); -} -#elif TARGET_INSN_START_EXTRA_WORDS =3D=3D 2 -static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, - target_ulong a2) -{ - TCGOp *op =3D tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS); - tcg_set_insn_start_param(op, 0, pc); - tcg_set_insn_start_param(op, 1, a1); - tcg_set_insn_start_param(op, 2, a2); -} -#else -#error Unhandled TARGET_INSN_START_EXTRA_WORDS value -#endif - #if TARGET_LONG_BITS =3D=3D 32 typedef TCGv_i32 TCGv; #define tcg_temp_new() tcg_temp_new_i32() diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index a799f42db31..c9da620ab3e 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -24,6 +24,4 @@ # define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 8b46c7c5708..7de0099cbfa 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -32,11 +32,4 @@ # define TARGET_PAGE_BITS_LEGACY 10 #endif /* !CONFIG_USER_ONLY */ =20 -/* - * ARM-specific extra insn start words: - * 1: Conditional execution bits - * 2: Partial exception syndrome for data aborts - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index f74bfc25804..ea7887919a7 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -25,6 +25,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 24 #define TARGET_VIRT_ADDR_SPACE_BITS 24 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 635d509e743..45ee7b46409 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -23,6 +23,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 36 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 9bf7ac76d0c..e0b2c7c9157 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -19,6 +19,4 @@ =20 #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index ebb844bcc83..909bc027923 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -22,6 +22,4 @@ #endif #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h index 58cc45a377e..071567712b3 100644 --- a/target/loongarch/cpu-param.h +++ b/target/loongarch/cpu-param.h @@ -13,6 +13,4 @@ =20 #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h index 256a2b5f8b2..7afbf6d302d 100644 --- a/target/m68k/cpu-param.h +++ b/target/m68k/cpu-param.h @@ -17,6 +17,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h index e0a37945136..6a0714bb3d7 100644 --- a/target/microblaze/cpu-param.h +++ b/target/microblaze/cpu-param.h @@ -27,6 +27,4 @@ /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */ #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 58f450827f7..a71e7383d24 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -20,6 +20,4 @@ #endif #define TARGET_PAGE_BITS 12 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/or1k/cpu-param.h b/target/or1k/cpu-param.h index b4f57bbe692..3011bf5fcca 100644 --- a/target/or1k/cpu-param.h +++ b/target/or1k/cpu-param.h @@ -12,6 +12,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h index e4ed9080ee9..ca7602d8983 100644 --- a/target/ppc/cpu-param.h +++ b/target/ppc/cpu-param.h @@ -37,6 +37,4 @@ # define TARGET_PAGE_BITS 12 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index cfdc67c258c..039e877891a 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -17,13 +17,6 @@ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ =20 -/* - * RISC-V-specific extra insn start words: - * 1: Original instruction opcode - * 2: more information about instruction - */ -#define TARGET_INSN_START_EXTRA_WORDS 2 - /* * The current MMU Modes are: * - U mode 0b000 diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h index 84934f3bcaf..ef1970a09e9 100644 --- a/target/rx/cpu-param.h +++ b/target/rx/cpu-param.h @@ -24,6 +24,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h index abfae3bedfb..a5f798eeae7 100644 --- a/target/s390x/cpu-param.h +++ b/target/s390x/cpu-param.h @@ -12,6 +12,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 64 #define TARGET_VIRT_ADDR_SPACE_BITS 64 =20 -#define TARGET_INSN_START_EXTRA_WORDS 2 - #endif diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h index f328715ee86..2b6e11dd0ac 100644 --- a/target/sh4/cpu-param.h +++ b/target/sh4/cpu-param.h @@ -16,6 +16,4 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h index 45eea9d6bac..6e8e2a51469 100644 --- a/target/sparc/cpu-param.h +++ b/target/sparc/cpu-param.h @@ -21,6 +21,4 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 1 - #endif diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h index eb33a67c419..790242ef3d2 100644 --- a/target/tricore/cpu-param.h +++ b/target/tricore/cpu-param.h @@ -12,6 +12,4 @@ #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h index 7a0c22c9005..06d85218b84 100644 --- a/target/xtensa/cpu-param.h +++ b/target/xtensa/cpu-param.h @@ -16,6 +16,4 @@ #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 -#define TARGET_INSN_START_EXTRA_WORDS 0 - #endif diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 4442462891e..4d22d7d5a45 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2899,9 +2899,9 @@ static void alpha_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 if (ctx->pcrel) { - tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK); + tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK, 0, 0); } else { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } } =20 diff --git a/target/avr/translate.c b/target/avr/translate.c index 78ae83df219..649dd4b0112 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2689,7 +2689,7 @@ static void avr_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->npc); + tcg_gen_insn_start(ctx->npc, 0, 0); } =20 static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 2fdc956bf99..8a223f6e13e 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -998,7 +998,7 @@ static void hexagon_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7186517239c..14210d569f7 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3501,7 +3501,7 @@ static void i386_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) if (tb_cflags(dcbase->tb) & CF_PCREL) { pc_arg &=3D ~TARGET_PAGE_MASK; } - tcg_gen_insn_start(pc_arg, dc->cc_op); + tcg_gen_insn_start(pc_arg, dc->cc_op, 0); } =20 static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/transl= ate.c index 30f375b33f0..b9ed13d19c6 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -159,7 +159,7 @@ static void loongarch_tr_insn_start(DisasContextBase *d= cbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 /* diff --git a/target/m68k/translate.c b/target/m68k/translate.c index a0309939012..abc1c79f3cd 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6041,7 +6041,7 @@ static void m68k_tr_tb_start(DisasContextBase *dcbase= , CPUState *cpu) static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0); } =20 static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 0be3c98dc17..2af67beecec 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1630,7 +1630,7 @@ static void mb_tr_insn_start(DisasContextBase *dcb, C= PUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); =20 - tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK); + tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK, 0); } =20 static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) diff --git a/target/or1k/translate.c b/target/or1k/translate.c index ce2dc466dc7..de81dc6ef8d 100644 --- a/target/or1k/translate.c +++ b/target/or1k/translate.c @@ -1552,7 +1552,7 @@ static void openrisc_tr_insn_start(DisasContextBase *= dcbase, CPUState *cs) DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) - | (dc->base.num_insns > 1 ? 2 : 0)); + | (dc->base.num_insns > 1 ? 2 : 0), 0); } =20 static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e9acfa239ec..a09a6df93fd 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6575,7 +6575,7 @@ static void ppc_tr_tb_start(DisasContextBase *db, CPU= State *cs) =20 static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } =20 static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) diff --git a/target/rx/translate.c b/target/rx/translate.c index 26d41548294..a245b9db8fe 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2217,7 +2217,7 @@ static void rx_tr_insn_start(DisasContextBase *dcbase= , CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index b3ae0a3814c..b1057727c55 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2181,7 +2181,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) * tb->icount * insn_start. */ for (i =3D 1; i < max_insns; ++i) { - tcg_gen_insn_start(pc + i * 2, ctx->envflags); + tcg_gen_insn_start(pc + i * 2, ctx->envflags, 0); ctx->base.insn_start =3D tcg_last_op(); } } @@ -2241,7 +2241,7 @@ static void sh4_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); + tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags, 0); } =20 static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 57b50ff8b9a..7e8558dbbd8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5735,7 +5735,7 @@ static void sparc_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cs) g_assert_not_reached(); } } - tcg_gen_insn_start(dc->pc, npc); + tcg_gen_insn_start(dc->pc, npc, 0); } =20 static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 18d8726af6d..0eaf7a82f87 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8410,7 +8410,7 @@ static void tricore_tr_insn_start(DisasContextBase *d= cbase, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 - tcg_gen_insn_start(ctx->base.pc_next); + tcg_gen_insn_start(ctx->base.pc_next, 0, 0); } =20 static bool insn_crosses_page(DisasContext *ctx, CPUTriCoreState *env) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index bb8d2ed86cf..5e3707d3fdf 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1159,7 +1159,7 @@ static void xtensa_tr_tb_start(DisasContextBase *dcba= se, CPUState *cpu) =20 static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { - tcg_gen_insn_start(dcbase->pc_next); + tcg_gen_insn_start(dcbase->pc_next, 0, 0); } =20 static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *c= pu) --=20 2.47.3